TWI433262B - Gate structure and method for trimming spacer - Google Patents

Description

Gate structure and method for trimming spacer

The present invention relates to a method of trimming a spacer and a gate structure. In particular, the present invention relates to a method of trimming a spacer to eliminate flaws and a gate structure to which the method is applied.

In the fabrication of a semiconductor device, it is generally necessary to form a plurality of spacers having a protective function, a self-aligning function, and the like on the peripheral side of the device in the semiconductor device, such as the peripheral side of the gate. However, when forming a spacer, it is often accompanied by some side effects.

First, the newly formed spacers on the sides of the gates create new stresses on the substrate, especially at the intersection of the spacers and the substrate. If the magnitude or direction of the stress is incorrect, it will adversely affect the carrier mobility in the substrate and the gate channel.

Second, the newly formed spacers on the sides of the gate change the nature of the substrate. For example, the dislocation phenomenon caused by the formation of the spacers may cause the original alignment rules of the germanium substrate atoms to be destroyed or disturbed. What's more, the poor discharge phenomenon causes the atomic arrangement of the ruthenium substrate to be broken to produce defects and cracks, and in the process of forming a metal salicide in the future, the metal atom is organically smeared and can be along these defects. The resulting cracks penetrate into the substrate, causing a pipeping effect, even deep into the direction of the gate channel. As a result, the leakage current of the element increases, which deteriorates the operability of the element, which is disadvantageous for the electrical performance of the MOS.

Thus, there is an urgent need for a technical solution that can alleviate the adverse effects of the spacers on the substrate to maintain the good performance of the semiconductor device.

The present invention thus proposes a method of trimming a spacer and a gate structure using the same. The method of the invention can effectively alleviate the stress generated by the spacer on the original substrate, avoid affecting the performance of the component in the substrate and the mobility of the carrier in the gate channel, and avoid the difference between the barrier substrate and the component. The leakage current is increased to maintain good performance of the semiconductor component.

The present invention first proposes a method of trimming a spacer. The method of dressing the spacers of the present invention initially provides a gate structure. The gate structure comprises a gate on the substrate, a first spacer on the substrate and surrounding the sidewall of the gate, the first spacer has an L-shaped section, and is located on the first spacer and surrounds the gate The second spacer. Next, a trimming process is performed such that the height of the second spacer is lower than the height of the first spacer. Preferably, the trimming process is performed using a dry or wet etching process such that the height of the second spacer is less than one half of the height of the first spacer or the height of the second spacer is equal to the height of the first spacer. Does not change continuously.

The invention further proposes a gate structure. The gate structure of the present invention comprises a gate on the substrate, a first spacer on the substrate and surrounding the sidewall of the gate, the first spacer has an L-shaped section and is located on the first spacer and Around the second spacer of the gate, the height of the second spacer is lower than the height of the first spacer. Preferably, the height of the second spacer is less than one half of the height of the first spacer, or the height of the second spacer is discontinuously different from the height of the first spacer.

In view of the prior art, the spacer may stress the original substrate, on the one hand, the component performance in the substrate and the carrier mobility in the gate channel, and on the other hand, the difference in the germanium substrate. The phenomenon and the leakage current of the element increase, which deteriorates the operability of the element, which is disadvantageous for the electrical performance of the MOS. The present invention thus provides a technical solution that alleviates the incorrect stress generated by the spacers on the substrate to solve the above problems.

1 to 4 are views showing a preferred embodiment of the method of trimming the spacer of the present invention. Referring to Figure 1, the substrate 101 is first provided. The gate structure 110 is located on the substrate 101. The gate structure 110 includes a gate 120, a first spacer 130, and a second spacer 140. In addition, the gate structure 110 may further include a gate insulating layer 111 and a liner 112. The gate insulating layer 111 is interposed between the gate 120 and the substrate 101 and typically comprises tantalum oxide or a high dielectric material. The pad layer 112 is located between the gate 120 and the first spacer 130, and may include germanium nitride or tantalum oxide. A lightly doped drain (LDD) may also be formed in advance before the formation of the spacer. At this point, the fabrication of the gate 120 and the gate insulating layer 111 is well known to those skilled in the art, and thus details will not be described herein.

The gate 120 is located above the substrate 101. Substrate 101 is typically a semiconductor substrate such as tantalum. Around the gate 120, it is first surrounded by the pad layer 112. This is followed by a first spacer 130 that is also on the substrate 101 and surrounds the sidewalls of the gate 120. In other words, the pad layer 112 is located between the gate 120 and the first spacer 130. The second spacer wall 140 is located on the first spacer 130 and surrounds the gate 120. The liner layer 112 can be a single layer or multiple layers. For example, the double liner layer 112 can be fabricated as described below. First, the preliminary shape of the gate 120 is defined. Next, an oxide layer is formed to cover the gate 120 by thermal oxide deposition. Next, a layer of oxide or nitride is formed by chemical vapor deposition (CVD) to cover the thermal oxide layer. Finally, the double liner layer 112 is completed via etch back.

The method of fabricating the first spacer 130 and the second spacer 140 may be as follows. After the gate 120 is completed, a first spacer material layer and a second spacer material layer of a suitable thickness are deposited on the substrate 101 and the gate 120, respectively. Then, the first spacer material layer and the second spacer material layer on the substrate 101 are subjected to an etching process, thereby leaving the first spacer 130 and the second spacer 140 around the gate 120. Also due to the etch back process of the second spacer 140, the first spacer 131 surrounding the gate structure 110 has an L-shaped plane, that is, the first spacer 130 includes a horizontal portion 132 and a contact substrate 101. Vertical portion 131.

As described in the prior art, the first spacers 130 and the second spacers 140 newly formed on the sides of the gate 120 generate new stress on the substrate 101 and locally change the nature of the substrate 101, so the present invention A finishing process is performed to adjust the height of the second spacer 140 to reduce the influence of the newly added stress on the substrate 101. A plurality of ways of adjusting the height of the second spacer 140 will be described below.

Referring to FIG. 2, in a preferred embodiment of the present invention, an etching selectivity ratio is provided between the first spacer 130 and the second spacer 140. A selective etch can then be used in the trim process to reduce the vertical height of the second spacer 140. For example, if the first spacers 130 are oxides, the second spacers 140 may be nitrides. Thus, using a dry or wet etch, such as hot phosphoric acid, the vertical height of the second spacers 140 can be effectively reduced to mitigate the effects of new stress on the substrate 101. In this way, the height of the second spacer 140 is lower than the height of the first spacer 130, so that the height of the second spacer 140 and the height of the first spacer 130 may exhibit discontinuous changes, such as Figure 2 shows. Preferably, the height of the second spacer 140 after the trimming process is lower than the height of the first spacer 130 or the gate 120. Alternatively, wet etching may be utilized to cause the first spacers 130 to be lower than the second spacers 140 to form a set of discontinuous spacers (not shown).

Referring to FIG. 3, in another preferred embodiment of the present invention, a third spacer 150 is further formed on the substrate 101. The third spacer 150 is located on the second spacer 140 and surrounds the gate 120, so that the second spacer 140 is also L-shaped, having a vertical portion and a horizontal portion. At this time, the cut surface of the third spacer 150 is D-shaped. In other words, the third spacer 150 has an arc-shaped side wall.

Similarly, the first spacer 130, the second spacer 140, and the third spacer 150 each have an etching selectivity ratio therebetween. For example, if the second spacer 140 contains nitride, the first spacer 130 and the third spacer 150 contain an oxide. Thus, the trim process can use selective etching to reduce only the vertical height of the second spacer 140, as shown in FIG. Due to the etching selection ratio, the height of the second spacer 140 may be lower than the height of the first spacer 130 and the third spacer 150. However, the first spacer 130, the second spacer 140, and the third spacer 150 may be independently yttrium oxide or tantalum nitride.

In the fabrication of a typical MOS semiconductor, after completing the gate structure 110, that is, the gate and the spacer, a source and drain ion implantation step is usually performed to form a source on both sides of the gate structure 110. Extreme and bungee, and then quickly annealed (RTP). In addition, in order to increase the channel stress, different technical solutions such as stress memorization technique (SMT) can also be used. Therefore, in a further preferred embodiment of the invention, the trimming process can be performed prior to the source and drain ion implantation steps or after the source and drain ion implantation steps. If the trimming process is performed prior to the source and drain ion implantation steps, it is recommended to leave enough spacers as a mask for the source and drain ion implantation steps. If the trimming process is performed after the source and drain ion implantation steps, the trimming process can be adjusted as appropriate to remove a sufficient amount of spacers.

For example, referring to FIG. 5, if stress memory technology is used, a pre-amorphous implant (PAI) may be performed to destroy the surface of the substrate 101. Then, referring to Fig. 6, a stress film deposition 160 is established. Again, stress layer 160 establishes the desired stress (denoted by symbol X) for the gate channel via annealing. Subsequently, referring to Fig. 7, the stress layer 160 can be removed while leaving the stress applied in the gate channel.

On the other hand, as shown in FIG. 8, it is also possible to establish a contact etch stop layer 170 (CESL) covering the gate structure 110 after the completion of the entire MOS. The contact hole etch stop layer 170 can be used as an etch stop layer on the one hand, and can also generate the required stress on the gate channel by a suitable means. The contact hole etch stop layer 170 is typically not removed compared to the stressor layer 160.

After the method of trimming the spacers by the above-described present invention, a gate structure can be obtained. 2 and 4 also illustrate a preferred embodiment of the gate structure of the present invention. As shown in FIG. 2, the semiconductor structure 100 of the present invention includes a substrate 101 and a gate structure 110. The gate structure 110 includes a gate 120, a first spacer 130, and a second spacer 140. The gate structure 110 is located on the substrate 101. In addition, the gate structure 110 may further include a gate insulating layer 111 and a pad layer 112. The gate insulating layer 111 is interposed between the gate 120 and the substrate 101 and typically comprises tantalum oxide or a high dielectric material. The pad layer 112 is between the gate 120 and the first spacer 130 and contains germanium nitride or tantalum oxide. The gate insulating layer 111 and the pad layer 112 are well known to those skilled in the art, so details will not be described herein.

The gate 120 is located above the substrate 101. Substrate 101 is typically a semiconductor substrate such as tantalum. Around the gate 120, it is first surrounded by the pad layer 112. This is followed by a first spacer 130 that is also on the substrate 101 and surrounds the sidewalls of the gate 120. In other words, the pad layer 112 is located between the gate 120 and the first spacer 130. The second spacer wall 140 is located on the first spacer 130 and surrounds the gate 120. The first spacer wall 130 has an L-shaped cut surface, that is, the first spacer wall 130 includes a vertical portion 131 and a horizontal portion 132 of the contact substrate 101.

It is desirable to slow the new stress generated by the newly formed first spacer 130 and the second spacer 140 on the side of the gate 120 and maintain the nature of the substrate. The second gap in the gate structure 100 of the present invention The height of the wall 140 is lower than the height of the first spacer 130. Preferably, the height of the second spacer 140 is also lower than one half of the height of the first spacer 130 to reduce the influence of the new stress on the substrate 101. . What is more, the height of the second spacer 140 and the height of the first spacer 130 may exhibit discontinuous changes.

Referring to FIG. 2, in a preferred embodiment of the present invention, the cut surface of the second spacer 140 is D-shaped. In other words, the second spacer 140 has curved sidewalls such that the vertical height of the second spacer 140 is The vertical height is lower than the first spacer 130. If the first spacers 130 are oxides, the second spacers 140 may be nitrides. As such, the height of the second spacer 140 and the height of the first spacer 130 may also exhibit discontinuous changes.

Referring to FIG. 4, in another preferred embodiment of the present invention, the semiconductor structure 100 of the present invention further includes a third spacer 150. The third spacer 150 is located on the second spacer 140 and surrounds the gate 120, so that the cut surface of the second spacer 140 is also L-shaped, having a vertical portion and a horizontal portion.

The cut surface of the third spacer 150 is D-shaped. In other words, the third spacer 150 has curved side walls as shown in FIG. Since the height of the second spacer 140 in the gate structure 110 of the present invention is lower than the height of the first spacer 130, the height of the second spacer 140 may be higher than that of the first spacer 130 and the third spacer 150 at the same time. The height is low. If the second spacers 140 are nitrides, the first spacers 130 and the third spacers 150 may be oxides.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Semiconductor structure

101. . . Substrate

110. . . Gate structure

111. . . Gate insulation

112. . . Liner layer

120. . . Gate

130. . . First spacer

131. . . Vertical part

132. . . Horizontal part

140. . . Second spacer

150. . . Third spacer

160. . . Stress layer

170. . . Contact hole etch stop layer

1 to 4 are schematic views showing a preferred embodiment of the method of trimming the spacer of the present invention.

Figures 5 through 8 illustrate schematic views of various embodiments of the present invention for forming a stressor layer.

100. . . Semiconductor structure

101. . . Substrate

110. . . Gate structure

111. . . Gate insulation

112. . . Liner layer

120. . . Gate

130. . . First spacer

131. . . Vertical part

132. . . Horizontal part

140. . . Second spacer

Claims (23)

A gate structure comprising: a gate on a substrate; a first spacer on the substrate surrounding the sidewall of the gate, the first spacer being L-shaped; and a second gap a wall located on the first spacer and surrounding the gate, the height of the second spacer being lower than the height of the first spacer and the second spacer extending radially to the first spacer One side of the L-shaped bottom is flush. The gate structure of claim 1, further comprising: a liner disposed between the gate and the first spacer and comprising a nitride or an oxide. The gate structure of claim 1, wherein an etching selectivity ratio is provided between the first spacer and the second spacer. The gate structure of claim 1, wherein the first spacer comprises a vertical portion and a horizontal portion contacting the substrate. The gate structure of claim 1, wherein the height of the second spacer is less than one half of the height of the first spacer. The gate structure of claim 1, wherein the second spacer is L-shaped. The gate structure of claim 6, further comprising: a third spacer on the second spacer and surrounding the gate. The gate structure of claim 7, wherein the third spacer has an etch selectivity ratio between the second spacer and the third spacer comprises an oxide or a nitride. The gate structure of claim 7, wherein the height of the second spacer is lower than the height of the first spacer and the third spacer. The gate structure of claim 1, wherein the height of the second spacer is discontinuously different from the height of the first spacer. A method of trimming a spacer, comprising: providing a gate structure comprising: a gate on a substrate; a first spacer on the substrate surrounding the gate The first spacer is L-shaped; and a second spacer is located on the first spacer and surrounds the gate, and the second spacer extends radially to the bottom of the first spacer L-shaped One side is flush: and a trimming process is performed such that the height of the second spacer is lower than the height of the first spacer. The method of claim 11, the gate structure further comprising: a liner disposed between the gate and the first spacer and comprising a nitride or an oxide. The method of claim 11, wherein the first spacer and the second spacer have an etch selectivity ratio. The method of claim 13, wherein the trimming process is performed using a wet etch. The method of claim 11, further comprising: performing a source/drain ion implantation step. The method of claim 15, wherein the trimming process is performed prior to the source/drain ion implantation step. The method of claim 15, wherein the trimming process is performed after the source/drain ion implantation step. The method of claim 17, wherein the height of the second spacer is less than one half of the height of the first spacer. The method of claim 11, wherein the second spacer is L-shaped. The method of claim 19, further comprising: forming a third spacer on the second spacer and surrounding the gate such that an etching selectivity ratio is formed between the third spacer and the second spacer, wherein The third spacer comprises an oxide or nitride. The method of claim 20, wherein the height of the second spacer is lower than the height of the first spacer and the third spacer. The method of claim 11, wherein the height of the second spacer is discontinuously different from the height of the first spacer. The method of claim 11, wherein the first spacer comprises contacting a vertical portion and a horizontal portion of the substrate.