TWI431756B - Low-voltage structure for high-voltage electrostatic discharge protection - Google Patents

Description

Low voltage structure for high voltage electrostatic discharge protection

Embodiments of the present invention relate to a semiconductor device, and more particularly to a low voltage structure of a high voltage electrostatic discharge (ESD).

In recent years, almost all electronic devices have been manufactured toward the goal of miniaturization. Smaller electronic devices are more popular than electronic devices that have the same function but are large and bulky. Since the miniaturization device needs to be composed of minute components, the ability to manufacture miniaturized components will obviously make the production of the miniaturization device easier. However, many electronic devices are currently required to have circuit devices that can perform actuation functions and data processing or other decision functions, and devices that can perform driving functions are, for example, switching devices. It is not always possible to manufacture such dual-function devices using Low Voltage Complementary Metal-Oxide Semiconductor (CMOS) technology. Therefore, high voltage (or high power) devices have been developed to handle many applications that cannot be implemented with low voltage operation.

The effectiveness of electrostatic discharge (ESD) of a typical high voltage device often depends on all widths and surface or side rules of the corresponding device. Therefore, for miniaturization devices, the effectiveness of electrostatic discharge is generally more critical. A typical characteristic of a high voltage device is that it has a low on-state resistance (Rdson), a high breakdown voltage, and a low holding voltage. During the event of an electrostatic discharge, the low on-resistance can concentrate the current of the electrostatic discharge on the surface of the device or on the edge of the drain region of the device. The action of high current and strong electric field will cause physical damage to the surface joint of the device. Surface or side rules may no longer increase due to the typical condition that low on-resistance must be met. Therefore, the protection of electrostatic discharge will be a big challenge.

In general, the high breakdown voltage characteristic of the high voltage device indicates that the breakdown voltage is higher than the operating voltage, and the trigger voltage Vt1 (trigger voltage, Vt1) is higher than the breakdown voltage. Therefore, the internal circuitry of the high voltage device may be at risk of damage during the electrostatic discharge before the high voltage device turns on the electrostatic discharge protection. The low-maintenance voltage characteristics of high-voltage devices cause power-on peak voltage or surge voltage to cause noise, and also make high-voltage devices in normal operation, possibly due to noise. Triggered, causing a latch-up. Since the distribution of the electric field is sensitive to circuit wiring, such that the high voltage device may experience a field plate effect, during the event of the electrostatic discharge, the current of the electrostatic discharge is concentrated on the surface of the device or the bungee Possible on the edge of the area.

Techniques for improving the effectiveness of electrostatic discharge in high voltage devices include adding reticle use or adding other steps to create a larger size in a Bipolar Junction Transistor (BJT) component. Polar bodies, and/or in metal oxide semiconductor transistors (MOS transistors), increase their surface or side rules.

Therefore, improving the structure for providing electrostatic discharge protection is a subject worthy of development.

Some embodiments of the present invention are directed to low voltage structures for high voltage ESD protection. In some cases, at least part of the process of Bipolar Complementary Metal-oxide Semiconductor (BiCMOS) Diffusion Metal-oxide Semiconductor (DMOS) can be modified to provide static electricity. Discharge protection, wherein the process can include an epi process.

In one embodiment, a high voltage electrostatic discharge (ESD) guard is provided. (In the example, "the embodiment" means "providing an example" or "description"). The high voltage ESD protection device can include a substrate, an N+ doped buried layer, an N-type well region, and a P-well region. The N+ doped buried layer can be placed close to the substrate. The N-type well region may be disposed adjacent to a portion of the N+ doped buried layer to form a Collector Region. The P-type well region may be disposed adjacent to the remaining portion of the N+ doped buried layer, and has at least one P+ doped plate corresponding to a base region, and a plurality of dispersed N+ doped plate segments corresponding to an emitter region ( Emitter Region).

In order to better understand the above and other aspects of the present invention, various embodiments are described below, and in conjunction with the accompanying drawings,

Some embodiments in accordance with the present invention will utilize a BCD process to provide a relatively small size, low voltage structure for use as a high voltage electrostatic discharge protection. Moreover, some embodiments in accordance with the present invention will provide a structure having a total area less than the BJT and MOS of the diode to provide the same ESD performance. Some embodiments may also have a breakdown voltage and a trigger voltage that is close to the operating voltage of the high voltage device and the trigger voltage is lower than the breakdown voltage of the high voltage device. In addition, an embodiment of the present invention can provide a relatively high sustain voltage compared to the use of a Silicon Controlled Rectifier (SCR), which can more easily avoid the occurrence of latch-up effects. In some cases, standard BCD processes can be utilized without the need for additional masks or process steps to provide several embodiments of the present invention.

The polycrystalline germanium used in some embodiments can be divided into several groups by parasitic devices through the hard reticle when ion implantation is performed. Some embodiments can effectively turn on multiple devices to reduce the current or strong electric field of the electrostatic discharge, and the current of the electrostatic discharge and the electric field are concentrated on the surface of the device during the electrostatic discharge.

The trigger voltage of some embodiments may be between a high voltage breakdown voltage and an operating voltage. This trigger voltage can effectively reduce the risk of damage to the guard or internal circuitry before the device turns on ESD protection during the event of an electrostatic discharge. As such, embodiments of the present invention may provide multiple snapbacks and trigger voltages, and may also provide relatively high sustain voltages. These features can reduce the incidence of latch-up effects under normal operating conditions. Moreover, embodiments can avoid field plate effects and are therefore relatively unaffected by circuit routing.

1 is a longitudinal cross-sectional view of a conventional bi-carrier junction transistor (BJT) for comparison with an embodiment. As shown in Fig. 1, an N+ buried layer 12 is provided on the P-type material substrate 10 or an epitaxially-grown P-layer (P-epi). An N-well 14 can be circumferentially disposed on the outer edge of the P-well 16. The collector of the bi-carrier junction transistor can be associated with the N-well 14 and the N+ buried layer 12. The emitter of the bipolar junction transistor can be associated with the N+ doped plate 18, and the N+ doped plate 18 is disposed proximate to the P-well 16. Field-oxide films (FOXs) may be disposed between the N+ doped plate 18 and the P+ doped plate 22, and the P+ doped plate 22 corresponding to the base of the bipolar junction transistor is disposed. On opposite sides of the N+ doped plate 18. Field oxide layers 24 (FOXs) may be disposed between the P+ doped plates 22 and the N+ doped plates 26 of the base, and the N+ doped plates 26 are associated with the collectors of the bipolar junction transistors. As shown in Fig. 1, two transistors 28 can be formed in this structure. Therefore, during the event of electrostatic discharge, part of the stress will be distributed between the two transistors 28.

2 is a cross-sectional view showing the structure of an embodiment of the present invention for providing high voltage electrostatic discharge protection. As shown in FIG. 2, an N+ buried layer 42 is provided on the P-type material substrate 40 or an epitaxially-grown P-layer (P-epi). An N-well 44 can be circumferentially disposed on the outer edge of the P-well 46. The collector of the bi-carrier junction transistor can be associated with the N-well 44 and the N+ buried layer (NBL). The emitter of the bipolar junction transistor can be associated with a plurality of discrete N+ doped plate segments 48, and the dispersed N+ doped plate segments 48 are disposed proximate to the P-well 46. The discrete N+ doped plate segments 48 can be disposed separately from one another by the separation of the P-wells 46, and the gates 50 can be formed over individual portions of the P-wells 46. The gate 50 is formed between the dispersed N+ doped plate section 48 and the polysilicon 54 and the dispersed N+ doped plate section 48 may include a gate oxide layer 52, wherein the polysilicon 54 may be provided as an ion implant Hard reticle. The gate 50 allows the dispersed N+ doped plate segments 48 to be effectively collectively operated as a single emitter of the plurality of bi-carrier junction transistor structures formed in FIG.

Field oxide layers 60 (FOXs) may be disposed between the ends of the dispersed N+ doped plate segments 48 and the ends of the P+ doped plates 62, and the P+ doped plates 62 correspond to the bases of the bipolar junction transistors. The P+ doped plate 62 may be disposed on both sides of the dispersed N+ doped plate section 48. The field oxide layer 64 can also be disposed between the P+ doped plate 62 and the N+ doped plate 66 of the base, and the N+ doped plate 66 is associated with the collector of the bipolar junction transistor. As shown in Fig. 2, a plurality of transistors 68 (6 transistors are provided in this embodiment) can be efficiently formed in the structure. Thus, during an electrostatic discharge event, stress will be distributed over the plurality of transistors 68 that are effectively formed, and the current of the electrostatic discharge can be dissipated such that the likelihood of structural damage is reduced. An additional bias voltage can be provided at the gate 50 (or at the base) to open the embodiment of the present invention early so that the current of the electrostatic discharge can be dissipated more efficiently.

The material of the N+ buried layer 42 may be an N-epi layer, a deep N-type well, or a plurality of stacked N+ buried layers. The P-well 46 can be stacked with a P-well and a P+ buried layer or a P-implant. In some cases, the N-well 44 can also be an N-implant.

3 is a top plan view of a layout in accordance with an embodiment of the present invention. This embodiment provides a relatively small size and low voltage structure, and the structure is similar to the structure of FIG. In Fig. 3, a collector region 100 is disposed at a peripheral portion of the structure. The collector region 100 can extend around the structure, and the collector region 100 is spaced apart from the base region 110 by an oxidized region (this oxidized region is, for example, the field oxide layer 64 of FIG. 2). The base region 110 can extend over a portion of the structure that is the location where the gate region 120 and the emitter region 130 are formed. Further, in some cases, the base region 110 may have a common center with the collector region 100.

The gate region 120 and the emitter region 130 may be disposed within a boundary defined by the base region 110 and separated from the base region 110 by an oxidized region, such as the field oxide layer 60 of FIG. As shown in FIG. 3, the gate region 120 and the emitter region 130 may be disposed close to each other, and portions of the gate region 120 extend substantially in parallel to portions of the emitter region 130, and the emitter is Many portions of region 130 are separated into segments (eg, forming a dispersed N+ doped plate segment 48 as in Figure 2).

4 is a top plan view of a layout in accordance with another embodiment of the present invention. This embodiment provides a relatively small size and low voltage structure, and the structure is similar to the structure of FIG. In FIG. 4, the collector region 200 is disposed at a peripheral portion of the structure and extends around the structure, and the collector region 200 is spaced apart from the base region 210 by an oxidized region (the oxidized region is, for example, the field of FIG. 2) Oxide layer 64). The base region 210 can extend over a portion of the structure that is the location where the gate region 220 and the emitter region 230 are formed. Moreover, in some examples, the base region 210 can have a common center with the collector region 200.

The gate region 220 and the emitter region 230 may be disposed within a boundary defined by the base region 210 and may be separated from the base region 110 by an oxidized region (for example, the field oxide layer 60 of FIG. 2). ). The gate region 220 can include an outer edge that has a common center with the collector region 200. In some examples, the gate region 220 and the emitter region 230 can be disposed in close proximity to one another, as shown in FIG. 4, and portions of the gate region 220 extend perpendicular to each other (eg, one of the gate regions 220) The portions extend in a horizontal direction and some portions extend in a vertical direction, and portions of the emitter region 230 fill a gap between a plurality of portions of the gate structure 220 extending vertically to define a grid shape structure. At this time, the emitter region 120 may be divided into segments of a plurality of rows and columns (a structure of 5 by 5 is provided in this embodiment) (for example, a plurality of dispersed N+ dopings as shown in FIG. 2 are formed). A section of the panel section 48).

Although the shape of the collector region, the base region, the gate region, and the emitter region defined in FIGS. 3 and 4 is a linear shape (or in some cases even a square or a rectangle), some others In the embodiment, the above region may be implemented by using other shapes instead. For example, FIG. 5 illustrates a top view of a layout in accordance with another embodiment of the present invention. This embodiment provides a structure of a smaller size and a lower voltage similar to FIG. 2. In FIG. 5, a collector region 300 is disposed at a peripheral portion of the structure and extends around the structure, and the collector region 300 is spaced apart from the base region 310 by an oxidized region (the oxidized region corresponds, for example, to 2 field oxide layer 64). The base region 310 can extend around a portion of the structure, and the gate region 320 and the emitter region 330 are formed in this portion. The collector region 300, the base region 310, the gate region 320, and the emitter region 330 are each a circle, and in this embodiment all of the circles have a common center.

The gate region 320 and the emitter region 330 may be disposed within a boundary defined by the base region 310. The gate region 320 and the emitter region 330 may be spaced apart from the base region 310 by an oxidized region (eg, an oxidized region such as It is the field oxide layer 60 of Figure 2. The gate region 320 and the emitter region 330 can each include a plurality of alternating circular portions such that respective circular (or annular) portions of the emitter region 330 and the next circular (or annular) portion of the emitter region 330, A plurality of separate rings of the emitter region may be formed by the respective circular (or annular) portions of the gate region 320, the separate rings corresponding to the plurality of discrete N+ doped regions of FIG. Paragraph 48.

FIG. 6 is a plan view showing a structure according to another embodiment of the present invention. The structure of this embodiment is similar to that of FIG. 5, and the difference between the two is that the gate region 340 of FIG. 6 is non-annular. For example, in FIG. 6, the gate region 340 includes a plurality of circular portions and a plurality of bisectors 350 having a shape of a circular portion and a plurality of annular structures disposed similar to the gate region 320 of FIG. Here, the structure of the plurality of circular portions of the emitter region 360 of FIG. 6 is substantially the same as the plurality of ring structures of the emitter region 330 of FIG. 5, and the plurality of circular regions of the emitter region 360 of FIG. The portion is further divided by a plurality of bisectors 350 in a manner passing through the center of the structure, and each of the divided portions has substantially the same central angle of the angle. The bisector 350 further divides the emitter region 360 into a plurality of portions (the portions correspond to the plurality of discrete N+ doped plate segments 48 of FIG. 2).

Figure 7 is a diagram showing a comparison of a conventional bipolar junction transistor (BJT) and an embodiment for cell pitch, holding voltage, and weakened leakage current by an experiment. (soft fail current leakage), and the comparison result of the second breakdown trigger current. As shown in the table in Figure 7, the experimental data in this example reduces the component spacing by 40% while increasing the 20% hold voltage, 58% weakened leakage current, and 25% breakdown trigger current. .

Thus, it can be seen that embodiments of the present invention provide a relatively small size and low voltage structure as a high voltage electrostatic discharge protection. Moreover, embodiments of the present invention can use standard BCD processes without the need for additional mask steps. Embodiments of the present invention may also use different high voltage BCD processes to provide different electrostatic protection operating voltages in the same process steps by the N+ buried layer or N-type well manufacturing process. Therefore, high voltage static electricity protection of a relatively small size and low voltage MOS structure is provided, and such high voltage static electricity protection is generally used for a device that is prone to high voltage setting of an electrostatic discharge event. Some embodiments of the invention may also be used in the operation of a typical DC circuit.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10. . . Substrate

12, 42. . . N+ buried layer (NBL)

14, 44. . . N-type well

16, 46. . . P-well

18, 26, 66. . . N+ doped plate

20, 24, 60, 64. . . Field oxide layer (FOXs)

22, 62. . . P+ doped plate

28, 68. . . Transistor

40. . . P-type material substrate

48. . . Decentralized N+ doped plate section

50. . . Gate

52. . . Gate oxide layer

54. . . Polycrystalline layer

100, 200, 300. . . Collective region

110, 210, 310. . . Base area

120, 220, 320, 340. . . Gate region

130, 230, 330, 360. . . Emitter region

350. . . Bisection line

1 is a longitudinal cross-sectional view of a conventional bi-carrier junction transistor (BJT) for comparison with an embodiment of the present invention.

2 is a cross-sectional view showing the structure of an embodiment of the present invention for providing high voltage electrostatic discharge protection.

3 is a top plan view of a layout in accordance with an embodiment of the present invention. This embodiment provides a relatively small size and low voltage structure, and the structure is similar to the structure of FIG.

4 is a top plan view of a layout in accordance with another embodiment of the present invention. This embodiment provides a relatively small size and low voltage structure, and the structure is similar to the structure of FIG.

Figure 5 is a top plan view of a layout in accordance with another embodiment of the present invention. This embodiment provides a structure of a smaller size and a lower voltage similar to Figure 2.

FIG. 6 is a top view of another embodiment of the present invention. The structure of this embodiment is similar to that of FIG. 5, and the difference from FIG. 5 is that the gate region 340 of FIG. 6 is non-annular.

Figure 7 is a diagram showing a comparison of a conventional bipolar junction transistor (BJT) and an embodiment for cell pitch, holding voltage, and weakening leakage by an experiment. The result of soft fail current leakage and second breakdown trigger current.

40. . . P-type material substrate

42. . . N+ buried layer (NBL)

44. . . N-type well

46. . . P-well

48. . . Decentralized N+ doped plate section

50. . . Gate

52. . . Gate oxide layer

54. . . Polycrystalline layer

60, 64. . . Field oxide layer (FOXs)

62. . . P+ doped plate

66. . . N+ doped plate

68. . . Transistor

Claims (15)

An electrostatic discharge protection (ESD) device includes: a substrate; an N+ doped buried layer disposed proximate to the substrate, and the N+ doped buried layer has a first portion and a second portion; an N-type well region a first portion of the N+ doped buried layer to form a collector region; and a P-type well region disposed proximate to the second portion of the N+ doped buried layer, the P-well The region has at least one P+ doped plate and a plurality of dispersed N+ doped plate segments, the P+ doped plate corresponding to a base region, and the dispersed N+ doped plate segments corresponding to an emitter region, The dispersed N+ doped plate segments are respectively separated by a plurality of individual portions of the P-type well region, and a gate structure is disposed above each of the individual portions, and the gate structures are mutually Electrical connection. The electrostatic discharge protection device of claim 1, wherein the N-type well region comprises two portions disposed on opposite sides of the P-type well region. The electrostatic discharge protection device of claim 1, wherein the gate structures each have a gate oxide layer and a polysilicon layer for supplying a bias signal to thereby cause the device to be The current of the electrostatic discharge is dissipated by the dispersed plurality of transistors to enable early protection of the electrostatic discharge. The electrostatic discharge protection device of claim 1, wherein the geometry of the collector region and the geometry of the base region have a common center. The electrostatic discharge protection device of claim 4, wherein the collector region, the base region, the emitter region, and a gate region are a plurality of circles having a common center, and the gate region A plurality of portions of the emitter region are disposed to form the dispersed N+ doped plate segments. The electrostatic discharge protection device of claim 4, wherein the collector region, the base region, and the emitter region are a plurality of common center circles, and by passing through a center of the emitter region And the plurality of radially extending lines define a gate region, and wherein the lines are spaced apart from one another by substantially equal central angles to form a plurality of discrete N+ doped plate segments. The electrostatic discharge protection device of claim 4, wherein the collector region and the base region surround a gate region, the gate region dividing the emitter region into the dispersed N+ doped plates Section. The electrostatic discharge protection device of claim 7, wherein the gate region comprises a plurality of linearly extending portions, the portions being respectively disposed in parallel between the plurality of linearly extending portions of the emitter region, And the gate region divides the emitter region into the dispersed N+ doped plate segments. The electrostatic discharge protection (ESD) device of claim 7, wherein the gate region comprises a grid-like structure comprising a plurality of linearly extending portions, the linearly extending portion A first group and a second group are disposed substantially perpendicular to each other to divide the emitter region into the dispersed N+ doped plate segments, and the distributed N+ doped plate segments are in a plurality of rows and a way of plural columns formed on the grid Inside the structure. The electrostatic discharge protection device of claim 1, wherein the N-type well region comprises an N-type implant material. The electrostatic discharge protection device of claim 1, wherein the P-type well region comprises a stacked structure, the stacked structure is formed by stacking a P-type well with a P+ buried layer or a P-type implant layer. . The electrostatic discharge protection device of claim 1, wherein the N+ doped buried layer comprises an N-type material formed by upper epitaxy or a deep N-type well. The electrostatic discharge protection device of claim 1, wherein the N+ doped buried layer comprises a plurality of stacked N+ buried layers. The electrostatic discharge protection device of claim 1, wherein the dispersed N+ doped plate segments are each associated with one of a plurality of independent electrostatic discharge current dissipation paths. An electrostatic discharge protection (ESD) device includes: a substrate; an N+ doped buried layer disposed proximate to the substrate, and the N+ doped buried layer has a first portion and a second portion; an N-type well region a first portion of the N+ doped buried layer to form a collector region; a P-type well region disposed proximate to the second portion of the N+ doped buried layer, the P-well region Having at least one P+ doped plate and a plurality of discrete N+ doped plate segments, the P+ doped plate corresponding to a base region, and the dispersed N+ doped plate segments corresponding to an emitter region, wherein The Each of the dispersed N+ doped plate segments is associated with one of a plurality of independent electrostatic discharge current dissipation paths; and a gate disposed in the dispersed N+ doped plate segments Therefore, during an electrostatic discharge event, the gate can separately open the independent electrostatic discharge current dissipation paths.