TWI431582B - Display devices and driving circuits - Google Patents
Display devices and driving circuits Download PDFInfo
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- TWI431582B TWI431582B TW099113636A TW99113636A TWI431582B TW I431582 B TWI431582 B TW I431582B TW 099113636 A TW099113636 A TW 099113636A TW 99113636 A TW99113636 A TW 99113636A TW I431582 B TWI431582 B TW I431582B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
本發明係關於一種顯示裝置，特別關於一種具有整合式時序控制器與源極驅動器之顯示裝置。The present invention relates to a display device, and more particularly to a display device having an integrated timing controller and a source driver.
由於具有反應速度快、輕薄、高亮度、低消耗功率、以及可高度擴展之顯示面積等特性，使得液晶顯示器近年來越來越受歡迎。為了增加液晶顯示器的面板解析度，以及達到高畫質的效果，源極驅動器的數量以及時序控制器與源極驅動器之間的傳輸速率都必須增加。Liquid crystal displays have become increasingly popular in recent years due to their fast response, lightness, high brightness, low power consumption, and highly expandable display area. In order to increase the panel resolution of the liquid crystal display and achieve high image quality, the number of source drivers and the transfer rate between the timing controller and the source driver must be increased.
傳統液晶顯示器的時序控制器配置於印刷電路板上，並且耦接於用以提供影像資料的主機與源極驅動器之間。時序控制器自主機端接收時序訊號與影像資料，將時序訊號與影像資料經轉換後傳送至源極驅動器。然而，由於傳輸線的長度隨著液晶顯示器的尺寸增加而變長，造成了傳輸錯誤率的增加，因而導致傳輸效能下降。此外，隨著液晶顯示器的尺寸增加，印刷電路板的時序控制器尺寸也會跟著增加，因而增加製造成本。因此，需要一種全新的驅動電路結構，其可降低製造成本，並且可進一步改善高畫質液晶顯示器的傳輸效能。The timing controller of the conventional liquid crystal display is disposed on the printed circuit board and coupled between the host and the source driver for providing image data. The timing controller receives the timing signal and the image data from the host end, and converts the timing signal and the image data to the source driver. However, since the length of the transmission line becomes longer as the size of the liquid crystal display increases, an increase in the transmission error rate is caused, resulting in a decrease in transmission efficiency. In addition, as the size of the liquid crystal display increases, the size of the timing controller of the printed circuit board also increases, thereby increasing the manufacturing cost. Therefore, there is a need for a completely new driving circuit structure which can reduce manufacturing costs and further improve the transmission performance of a high definition liquid crystal display.
根據本發明之一實施例，一種顯示裝置，包括一面板、複數源極驅動器晶片、一閘極驅動器晶片、一印刷電路板以及複數傳輸線。面板包括複數發光元件與顯示單元，其中顯示單元耦接至複數資料線與閘極線。源極驅動器晶片用以輸出複數像素訊號至資料線，其中至少一源極驅動器晶片包括一時序控制器整合於其中，用以根據一主機所提供之一影像控制訊號產生複數時序控制訊號與像素訊號。閘極驅動器晶片用以輸出對應之掃描訊號至閘極線。傳輸線配置於印刷電路板上，並且耦接源極驅動器晶片。According to an embodiment of the invention, a display device includes a panel, a plurality of source driver chips, a gate driver chip, a printed circuit board, and a plurality of transmission lines. The panel includes a plurality of light emitting elements and a display unit, wherein the display unit is coupled to the plurality of data lines and the gate lines. The source driver chip is configured to output a plurality of pixel signals to the data line, wherein the at least one source driver chip includes a timing controller integrated therein for generating a plurality of timing control signals and pixel signals according to an image control signal provided by a host . The gate driver chip is configured to output a corresponding scan signal to the gate line. The transmission line is disposed on the printed circuit board and coupled to the source driver chip.
根據本發明之另一實施例，一種驅動器電路，輸出複數像素訊號用以控制一液晶顯示面板，其中液晶顯示面板包括複數發光元件與顯示單元分別耦接至複數資料線與閘極線，驅動器電路包括複數源極驅動器晶片、一印刷電路板、以及複數傳輸線。源極驅動器晶片用以輸出像素訊號至資料線，其中源極驅動器晶片之一者包括一時序控制器整合於其中，用以根據一主機所提供之一影像控制訊號產生複數時序控制訊號與像素訊號。傳輸線配置於印刷電路板上，並且耦接源極驅動器晶片。According to another embodiment of the present invention, a driver circuit outputs a plurality of pixel signals for controlling a liquid crystal display panel, wherein the liquid crystal display panel includes a plurality of light emitting elements and a display unit respectively coupled to the plurality of data lines and the gate lines, and the driver circuit A plurality of source driver chips, a printed circuit board, and a plurality of transmission lines are included. The source driver chip is configured to output a pixel signal to the data line, wherein one of the source driver chips includes a timing controller integrated therein for generating a plurality of timing control signals and pixel signals according to an image control signal provided by a host . The transmission line is disposed on the printed circuit board and coupled to the source driver chip.
為使本發明之製造、操作方法、目標和優點能更明顯易懂，下文特舉幾個較佳實施例，並配合所附圖式，作詳細說明如下：In order to make the manufacturing, operating methods, objects and advantages of the present invention more apparent, the following detailed description of the preferred embodiments and the accompanying drawings
第1圖係顯示根據本發明之一實施例所述之顯示裝置100方塊圖。如圖所示，液晶顯示面板1由複數交織的資料線(D1,D2...Dm)與閘極線(G1,G2...Gn)所形成，並且各組資料線與閘極線用以控制一顯示單元。例如，交織的資料線D1與閘極線G1控制顯示單元200。閘極驅動器晶片10耦接至液晶顯示面板1，並且輸出對應的掃描訊號至閘極線G1,G2...Gn。源極驅動器晶片20-1與20-2輸出複數像素訊號至資料線D1,D2...Dm。根據本發明之一實施例，至少一源極驅動器晶片包括一時序控制器整合於其中，用以根據一主機(圖未示)所提供之一影像控制訊號產生複數時序控制訊號與像素訊號，其中主機可以是電腦、顯示卡、或其它類似的裝置。1 is a block diagram showing a display device 100 according to an embodiment of the present invention. As shown in the figure, the liquid crystal display panel 1 is formed by a plurality of interleaved data lines (D1, D2 ... Dm) and gate lines (G1, G2 ... Gn), and each group of data lines and gate lines is used. To control a display unit. For example, the interleaved data line D1 and the gate line G1 control the display unit 200. The gate driver chip 10 is coupled to the liquid crystal display panel 1 and outputs corresponding scan signals to the gate lines G1, G2 . . . Gn. The source driver chips 20-1 and 20-2 output complex pixel signals to the data lines D1, D2, ... Dm. According to an embodiment of the present invention, at least one source driver chip includes a timing controller integrated therein for generating a plurality of timing control signals and pixel signals according to an image control signal provided by a host (not shown), wherein The host can be a computer, a display card, or other similar device.
第2圖係顯示根據本發明之一實施例所述之源極驅動器晶片30之方塊圖，其中包含了源極驅動器301與時序控制器302整合於其中。根據本發明之一實施例，由於源極驅動器301與時序控制器302被整合在一起，原本所需分別內建於源極驅動器與時序控制器的傳送器與接收器在此便不再需要了。如此一來，可進一步降低源極驅動器與時序控制器的製造成本。第3圖顯示根據本發明之一第一實施例所述之驅動電路佈局圖，其中驅動電路可使用如第2圖所示之源極驅動器晶片30。值得注意的是，為簡化說明，僅與本發明所提出之佈局結構相關的元件會被討論。任何熟習此項技藝者當可根據第3圖所示之電路推導出其它相關但未示於圖中的元件，因此本發明之圖示與相關介紹並非用以限定本發明的範圍。2 is a block diagram showing a source driver chip 30 in accordance with an embodiment of the present invention, including a source driver 301 and a timing controller 302 integrated therein. According to an embodiment of the present invention, since the source driver 301 and the timing controller 302 are integrated, the transmitters and receivers originally required to be built in the source driver and the timing controller are no longer needed here. . As a result, the manufacturing cost of the source driver and the timing controller can be further reduced. Fig. 3 is a view showing a layout of a driving circuit according to a first embodiment of the present invention, in which a driving circuit can use a source driver chip 30 as shown in Fig. 2. It is to be noted that, for simplicity of explanation, only elements related to the layout structure proposed by the present invention will be discussed. Any other person skilled in the art can derive other related components, which are not shown in the drawings, according to the circuit shown in FIG. 3, and thus the illustration and related description of the present invention are not intended to limit the scope of the present invention.
如第3圖所示，驅動電路包括一印刷電路板300、複數源極驅動器晶片30-1,30-2,....,30-N、配置於印刷電路板上並且耦接至源極驅動器晶片之複數傳輸線33、以及配置於印刷電路板上並且耦接至主機36與至少一源極驅動器晶片之連接器35。根據本發明之第一實施例，各源極驅動器晶片包括一時序控制器整合於其中，因此標示為「源極驅動器-時序控制器」。如圖所示，各源極驅動器晶片透過傳輸線33耦接至連接器35。關於包括時序控制器整合於其中之源極驅動器晶片30-1,30-2,....,30-N的結構可參考至第2圖與相關介紹段落，於此不再贅述。根據本發明之一實施例，源極驅動器晶片30-1,30-2,....,30-N自連接器35接收主機36所提供之影像控制訊號，產生對應之時序控制訊號與像素訊號，並且根據時序控制訊號與像素訊號輸出對應之像素資料至如第1圖所示之資料線D1,D2,...,Dm。時序控制訊號可包括一起始脈衝訊號(例如，EIO訊號)，用以為各源極驅動器晶片指示出開始擷取像素資料的時間。時序控制訊號可更包括一像素時脈訊號，用以指示像素訊號之一像素資料傳輸頻率。根據本發明之另一實施例，可以僅致能其中一個源極驅動器晶片內的時序控制器，例如僅致能源極驅動器晶片30-1內的時序控制器，並且使得其它源極驅動器晶片30-2,....,30-N內的時序控制器失能。如此一來，源極驅動器晶片30-2,....,30-N所需的時序控制訊號與像素訊號可均接收自源極驅動器晶片30-1。根據本發明之一實施例，傳輸線33可以是差動匯流排，例如低電壓差動訊號(Low Voltage Differential Signaling，LVDS)匯流排，或其它類似的差動匯流排。源極驅動器晶片30-1,30-2,....,30-N可經由薄膜覆晶封裝(Chip On Film，COF)或玻璃覆晶基板(Chip On Glass，COG)等技術封裝於印刷電路板300上。如圖所示，由於時序控制器被整合於源極驅動器內，傳統因配置時序控制器所需之印刷電路板面積可因此減少。As shown in FIG. 3, the driving circuit includes a printed circuit board 300, a plurality of source driver chips 30-1, 30-2, ..., 30-N, disposed on the printed circuit board and coupled to the source. A plurality of transmission lines 33 of the driver chip, and a connector 35 disposed on the printed circuit board and coupled to the host 36 and the at least one source driver chip. In accordance with a first embodiment of the present invention, each of the source driver chips includes a timing controller integrated therein, and is therefore labeled "source driver-timing controller." As shown, each of the source driver wafers is coupled to the connector 35 via a transmission line 33. The structure of the source driver chips 30-1, 30-2, ..., 30-N including the timing controller integrated therein can be referred to FIG. 2 and related introductory paragraphs, and details are not described herein again. According to an embodiment of the invention, the source driver chips 30-1, 30-2, . . ., 30-N receive the image control signals provided by the host 36 from the connector 35, and generate corresponding timing control signals and pixels. The signal, and according to the timing control signal and the pixel signal output corresponding pixel data to the data lines D1, D2, ..., Dm as shown in Figure 1. The timing control signal can include a start pulse signal (eg, an EIO signal) to indicate to each source driver chip the time at which pixel data is initially captured. The timing control signal may further include a pixel clock signal for indicating a pixel data transmission frequency of the pixel signal. In accordance with another embodiment of the present invention, only timing controllers within one of the source driver wafers can be enabled, such as only timing controllers within the energy source driver chip 30-1, and other source driver wafers 30- 2, ...., the timing controller in 30-N is disabled. As a result, the timing control signals and pixel signals required for the source driver chips 30-2, . . . , 30-N can all be received from the source driver chip 30-1. According to an embodiment of the invention, the transmission line 33 may be a differential bus, such as a Low Voltage Differential Signaling (LVDS) bus, or other similar differential bus. The source driver chips 30-1, 30-2, . . . , 30-N can be packaged in printing via a technology such as a chip on film (COF) or a chip on glass (Chip On Glass, COG). On the circuit board 300. As shown, since the timing controller is integrated into the source driver, the traditional printed circuit board area required to configure the timing controller can be reduced.
第4圖顯示根據本發明之一第二實施例所述之驅動電路佈局圖。值得注意的是，為簡化說明，僅與本發明所提出之佈局結構相關的元件會被討論。任何熟習此項技藝者當可根據第4圖所示之電路推導出其它相關但未示於圖中的元件，因此本發明之圖示與相關介紹並非用以限定本發明的範圍。如第4圖所示，驅動電路包括一印刷電路板400、複數源極驅動器晶片40-1,40-2,....,40-N、配置於印刷電路板上並且耦接至源極驅動器晶片之複數傳輸線41與42、以及配置於印刷電路板上並且耦接至主機46與至少一源極驅動器晶片之連接器45。根據本發明之第二實施例，各源極驅動器晶片包括一時序控制器整合於其中，因此標示為「源極驅動器-時序控制器」。僅一個源極驅動器晶片40-1透過傳輸線41耦接至連接器45，並且源極驅動器晶片40-1,40-2,....,40-N透過傳輸線42互相耦接。Fig. 4 is a view showing a layout of a driving circuit according to a second embodiment of the present invention. It is to be noted that, for simplicity of explanation, only elements related to the layout structure proposed by the present invention will be discussed. Any other person skilled in the art can derive other related components, which are not shown in the drawings, according to the circuit shown in FIG. 4, and thus the illustration and related description of the present invention are not intended to limit the scope of the present invention. As shown in FIG. 4, the driving circuit includes a printed circuit board 400, a plurality of source driver chips 40-1, 40-2, ..., 40-N, disposed on the printed circuit board and coupled to the source. The plurality of transmission lines 41 and 42 of the driver chip, and the connector 45 disposed on the printed circuit board and coupled to the host 46 and the at least one source driver chip. In accordance with a second embodiment of the present invention, each of the source driver chips includes a timing controller integrated therein, and is therefore labeled "Source Driver - Timing Controller." Only one source driver chip 40-1 is coupled to the connector 45 through the transmission line 41, and the source driver chips 40-1, 40-2, . . . , 40-N are coupled to each other through the transmission line 42.
根據本發明之一實施例，源極驅動器晶片40-1的時序控制器自連接器45接收由主機46所提供之影像控制訊號，並且根據影像控制訊號產生時序控制訊號與像素訊號。源極驅動器晶片40-1更將時序控制訊號與像素訊號傳送至未與連接器45耦接之且源極驅動器晶片40-2,....,40-N。根據本發明之一實施例，時序控制訊號可包括一起始脈衝訊號(例如，EIO訊號)，用以為各源極驅動器晶片指示出開始擷取像素資料的時間、一像素時脈訊號，用以指示像素訊號之一像素資料傳輸頻率、以及一資料致能訊號，用以指示是否像素訊號之素資料為有效資料或空白資料。源極驅動器晶片40-1,40-2,....,40-N接著根據時序控制訊號與像素訊號輸出對應之像素資料至如第1圖所示之資料線D1,D2,...,Dm。由於各源極驅動器晶片40-1,40-2,....,40-N包括時序控制器整合於其中，該等時序控制器可分別產生其餘所須知時序控制訊號。因此，可進一步減少傳輸線42上所需傳輸的資料量。According to an embodiment of the invention, the timing controller of the source driver chip 40-1 receives the image control signal provided by the host 46 from the connector 45, and generates timing control signals and pixel signals according to the image control signals. The source driver chip 40-1 further transmits the timing control signal and the pixel signal to the source driver chips 40-2, . . . , 40-N that are not coupled to the connector 45. According to an embodiment of the invention, the timing control signal may include a start pulse signal (for example, an EIO signal) for indicating, for each source driver chip, a time when the pixel data is started to be extracted, and a pixel clock signal for indicating A pixel data transmission frequency of a pixel signal and a data enable signal for indicating whether the pixel signal data is valid data or blank data. The source driver chips 40-1, 40-2, . . . , 40-N then output the pixel data corresponding to the timing signal and the pixel signal output to the data lines D1, D2, ... as shown in FIG. , Dm. Since each of the source driver chips 40-1, 40-2, . . . , 40-N includes a timing controller integrated therein, the timing controllers can respectively generate the remaining required timing control signals. Therefore, the amount of data to be transmitted on the transmission line 42 can be further reduced.
根據本發明之一實施例，傳輸線41之一傳輸速率可高於傳輸線42之一傳輸速率。例如，傳輸線41可為一低電壓差動訊號(LVDS)匯流排，而傳輸線42可為一縮小擺幅差動訊號(Reduced Swing Differential Signaling，RSDS)匯流排。傳輸線42也可是比傳統傳輸線具有更少資料線的傳輸介面。根據本發明之另一實施例，未耦接至連接器45之源極驅動器晶片40-2,....,40-N內的時序控制器也可被失能。如此一來，源極驅動器晶片40-2,....,40-N所需的時序控制訊號與像素訊號可均接收自源極驅動器晶片40-1。根據本發明之實施例，源極驅動器晶片40-1,40-2,....,40-N可經由薄膜覆晶封裝(Chip On Film，COF)或玻璃覆晶基板(Chip On Glass，COG)等技術封裝於印刷電路板400上。如圖所示，由於時序控制器被整合於源極驅動器內，傳統因配置時序控制器所需之印刷電路板面積可因此減少。According to an embodiment of the invention, one of the transmission lines 41 may have a higher transmission rate than one of the transmission lines 42. For example, the transmission line 41 can be a low voltage differential signaling (LVDS) bus, and the transmission line 42 can be a reduced Swing Differential Signaling (RSDS) bus. Transmission line 42 can also be a transmission interface that has fewer data lines than conventional transmission lines. According to another embodiment of the present invention, the timing controllers within the source driver chips 40-2, . . . , 40-N that are not coupled to the connector 45 can also be disabled. As a result, the timing control signals and pixel signals required for the source driver chips 40-2, . . . , 40-N can all be received from the source driver chip 40-1. According to an embodiment of the present invention, the source driver wafers 40-1, 40-2, . . . , 40-N may be via a Chip On Film (COF) or a Chip On Glass (Chip On Glass, Technology such as COG) is packaged on the printed circuit board 400. As shown, since the timing controller is integrated into the source driver, the traditional printed circuit board area required to configure the timing controller can be reduced.
第5顯示根據本發明之一第三實施例所述之驅動電路佈局圖。值得注意的是，為簡化說明，僅與本發明所提出之佈局結構相關的元件會被討論。任何熟習此項技藝者當可根據第5圖所示之電路推導出其它相關但未示於圖中的元件，因此本發明之圖示與相關介紹並非用以限定本發明的範圍。如第5圖所示，驅動電路包括一印刷電路板500、複數源極驅動器晶片50-1,50-2,....,50-N、配置於印刷電路板上並且耦接至源極驅動器晶片之複數傳輸線51與52、以及配置於印刷電路板上並且耦接至主機56與至少一源極驅動器晶片之連接器55。據本發明之第三實施例，僅一個源極驅動器晶片包括一時序控制器整合於其中，因此標示為「源極驅動器-時序控制器」。源極驅動器晶片50-1透過傳輸線51耦接至連接器55。未耦接至連接器的源極驅動器晶片則標示為「源極驅動器」。所有的源極驅動器晶片50-1,50-2,....,50-N透過傳輸線52互相耦接。Fig. 5 shows a layout of a driving circuit according to a third embodiment of the present invention. It is to be noted that, for simplicity of explanation, only elements related to the layout structure proposed by the present invention will be discussed. Any other person skilled in the art can derive other related components, which are not shown in the drawings, according to the circuit shown in FIG. 5, and thus the illustration and related description of the present invention are not intended to limit the scope of the present invention. As shown in FIG. 5, the driving circuit includes a printed circuit board 500, a plurality of source driver chips 50-1, 50-2, ..., 50-N, disposed on the printed circuit board and coupled to the source. The plurality of transmission lines 51 and 52 of the driver chip, and the connector 55 disposed on the printed circuit board and coupled to the host 56 and the at least one source driver chip. According to a third embodiment of the present invention, only one source driver chip includes a timing controller integrated therein, and is therefore labeled "source driver-timing controller". The source driver chip 50-1 is coupled to the connector 55 through the transmission line 51. The source driver chip that is not coupled to the connector is labeled as "source driver." All of the source driver chips 50-1, 50-2, . . . , 50-N are coupled to each other through the transmission line 52.
根據本發明之一實施例，源極驅動器晶片50-1的時序控制器自連接器55接收由主機56所提供之影像控制訊號，並且根據影像控制訊號產生時序控制訊號與像素訊號。源極驅動器晶片50-1更將時序控制訊號與像素訊號傳送至未與連接器55耦接之且源極驅動器晶片50-2,....,50-N。根據本發明之一實施例，時序控制訊號可包括一起始脈衝訊號(例如，EIO訊號)，用以為各源極驅動器晶片指示出開始擷取像素資料的時間、一像素時脈訊號，用以指示像素訊號之一像素資料傳輸頻率、以及一資料致能訊號，用以指示是否像素訊號之素資料為有效資料或空白資料。源極驅動器晶片50-1,50-2,....,50-N接著根據時序控制訊號與像素訊號輸出對應之像素資料至如第1圖所示之資料線D1,D2,...,Dm。According to an embodiment of the invention, the timing controller of the source driver chip 50-1 receives the image control signal provided by the host 56 from the connector 55, and generates timing control signals and pixel signals according to the image control signals. The source driver chip 50-1 further transmits the timing control signal and the pixel signal to the source driver chips 50-2, . . . , 50-N that are not coupled to the connector 55. According to an embodiment of the invention, the timing control signal may include a start pulse signal (for example, an EIO signal) for indicating, for each source driver chip, a time when the pixel data is started to be extracted, and a pixel clock signal for indicating A pixel data transmission frequency of a pixel signal and a data enable signal for indicating whether the pixel signal data is valid data or blank data. The source driver chips 50-1, 50-2, . . . , 50-N then output the pixel data corresponding to the pixel signal output according to the timing control signal to the data lines D1, D2, ... as shown in FIG. , Dm.
根據本發明之一實施例，傳輸線51之一傳輸速率可高於傳輸線52之一傳輸速率。例如，傳輸線51可為一低電壓差動訊號(LVDS)匯流排，而傳輸線52可為一縮小擺幅差動訊號(RSDS)匯流排。傳輸線52也可是比傳統傳輸線具有更少資料線的傳輸介面。根據本發明之實施例，源極驅動器晶片50-1,50-2,....,50-N可經由薄膜覆晶封裝(Chip On Film，COF)或玻璃覆晶基板(Chip On Glass，COG)等技術封裝於印刷電路板500上。如圖所示，由於時序控制器被整合於源極驅動器內，傳統因配置時序控制器所需之印刷電路板面積可因此減少。According to an embodiment of the invention, one of the transmission lines 51 may have a higher transmission rate than one of the transmission lines 52. For example, the transmission line 51 can be a low voltage differential signaling (LVDS) bus, and the transmission line 52 can be a reduced swing differential signal (RSDS) bus. Transmission line 52 can also be a transmission interface that has fewer data lines than conventional transmission lines. According to an embodiment of the present invention, the source driver wafers 50-1, 50-2, ..., 50-N may be via a chip on film (COF) or a chip on glass substrate (Chip On Glass, Technology such as COG) is packaged on the printed circuit board 500. As shown, since the timing controller is integrated into the source driver, the traditional printed circuit board area required to configure the timing controller can be reduced.
第6顯示根據本發明之一第四實施例所述之驅動電路佈局圖。值得注意的是，為簡化說明，僅與本發明所提出之佈局結構相關的元件會被討論。任何熟習此項技藝者當可根據第6圖所示之電路推導出其它相關但未示於圖中的元件，因此本發明之圖示與相關介紹並非用以限定本發明的範圍。如第6圖所示，驅動電路包括一印刷電路板600、複數源極驅動器晶片60-1,60-2,....,60-N、配置於印刷電路板上並且耦接至源極驅動器晶片之複數傳輸線61與62、以及配置於印刷電路板上並且耦接至主機66與至少一源極驅動器晶片之連接器65。據本發明之第四實施例，僅一個源極驅動器晶片60-1包括一時序控制器整合於其中，因此標示為「源極驅動器-時序控制器」。源極驅動器晶片60-1透過傳輸線61耦接至連接器65。其餘未耦接至連接器65的源極驅動器晶片則標示為「源極驅動器」。每對相鄰之源極驅動器晶片(例如，60-1與60-2、60-2與60-3、...60-(N-1)與60-N)透過傳輸線62彼此互相耦接。Fig. 6 shows a layout of a driving circuit according to a fourth embodiment of the present invention. It is to be noted that, for simplicity of explanation, only elements related to the layout structure proposed by the present invention will be discussed. Any other person skilled in the art can derive other related components, which are not shown in the drawings, according to the circuit shown in FIG. 6, and thus the illustration and related description of the present invention are not intended to limit the scope of the present invention. As shown in FIG. 6, the driving circuit includes a printed circuit board 600, a plurality of source driver chips 60-1, 60-2, ..., 60-N, disposed on the printed circuit board and coupled to the source. The plurality of transmission lines 61 and 62 of the driver chip, and the connector 65 disposed on the printed circuit board and coupled to the host 66 and the at least one source driver chip. According to a fourth embodiment of the present invention, only one source driver chip 60-1 includes a timing controller integrated therein, and is therefore labeled "source driver-timing controller". The source driver chip 60-1 is coupled to the connector 65 through the transmission line 61. The remaining source driver chips that are not coupled to the connector 65 are labeled as "source drivers." Each pair of adjacent source driver chips (eg, 60-1 and 60-2, 60-2 and 60-3, ... 60-(N-1) and 60-N) are coupled to each other via a transmission line 62 .
根據本發明之一實施例，源極驅動器晶片60-1的時序控制器自連接器65接收由主機66所提供之影像控制訊號，並且根據影像控制訊號產生時序控制訊號與像素訊號。源極驅動器晶片60-1更將時序控制訊號與像素訊號傳送至相鄰且未與連接器65耦接之且源極驅動器晶片60-2。未耦接至該連接器之源極驅動器晶片一個接著一個將接收到的時序控制訊號與像素訊號傳遞至與其相鄰之源極驅動器晶片。根據本發明之一實施例，時序控制訊號可包括一起始脈衝訊號(例如，EIO訊號)，用以為各源極驅動器晶片指示出開始擷取像素資料的時間、一像素時脈訊號，用以指示像素訊號之一像素資料傳輸頻率、以及一資料致能訊號，用以指示是否像素訊號之素資料為有效資料或空白資料。源極驅動器晶片60-1,60-2,....,60-N接著根據時序控制訊號與像素訊號輸出對應之像素資料至如第1圖所示之資料線D1,D2,...,Dm。According to an embodiment of the invention, the timing controller of the source driver chip 60-1 receives the image control signal provided by the host 66 from the connector 65, and generates timing control signals and pixel signals according to the image control signals. The source driver chip 60-1 further transmits the timing control signal and the pixel signal to the source driver chip 60-2 adjacent to the connector 65 and not coupled to the connector 65. The source driver wafers not coupled to the connector pass the received timing control signals and pixel signals one after another to the source driver wafers adjacent thereto. According to an embodiment of the invention, the timing control signal may include a start pulse signal (for example, an EIO signal) for indicating, for each source driver chip, a time when the pixel data is started to be extracted, and a pixel clock signal for indicating A pixel data transmission frequency of a pixel signal and a data enable signal for indicating whether the pixel signal data is valid data or blank data. The source driver chips 60-1, 60-2, . . . , 60-N then output the pixel data corresponding to the timing signal and the pixel signal output to the data lines D1, D2, ... as shown in FIG. , Dm.
根據本發明之一實施例，傳輸線61之一傳輸速率可高於傳輸線62之一傳輸速率。例如，傳輸線61可為一低電壓差動訊號(LVDS)匯流排，而傳輸線62可為一縮小擺幅差動訊號(RSDS)匯流排。傳輸線62也可是比傳統傳輸線具有更少資料線的傳輸介面。根據本發明之實施例，源極驅動器晶片60-1,60-2,....,60-N可經由薄膜覆晶封裝(Chip On Film，COF)或玻璃覆晶基板(Chip On Glass，COG)等技術封裝於印刷電路板600上。如圖所示，由於時序控制器被整合於源極驅動器內，傳統因配置時序控制器所需之印刷電路板面積可因此減少。因此印刷電路板的面積可進一步被縮小。According to an embodiment of the invention, one of the transmission lines 61 may have a higher transmission rate than one of the transmission lines 62. For example, the transmission line 61 can be a low voltage differential signaling (LVDS) bus, and the transmission line 62 can be a reduced swing differential signal (RSDS) bus. Transmission line 62 can also be a transmission interface that has fewer data lines than conventional transmission lines. According to an embodiment of the present invention, the source driver wafers 60-1, 60-2, ..., 60-N may be via a chip on film (COF) or a chip on glass substrate (Chip On Glass, Technology such as COG) is packaged on the printed circuit board 600. As shown, since the timing controller is integrated into the source driver, the traditional printed circuit board area required to configure the timing controller can be reduced. Therefore, the area of the printed circuit board can be further reduced.
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
1．．．液晶顯示面板1. . . LCD panel
10．．．閘極驅動器晶片10. . . Gate driver chip
20-1、20-2、30、30-1、30-2、30-N、40-1、40-2、40-N、50-1、50-2、50-N、60-1、60-2、60-N．．．源極驅動器晶片20-1, 20-2, 30, 30-1, 30-2, 30-N, 40-1, 40-2, 40-N, 50-1, 50-2, 50-N, 60-1, 60-2, 60-N. . . Source driver chip
33、41、42、51、52、61、62．．．傳輸線33, 41, 42, 51, 52, 61, 62. . . Transmission line
35、45、55、65．．．連接器35, 45, 55, 65. . . Connector
36、46、56、66．．．主機36, 46, 56, 66. . . Host
100．．．顯示裝置100. . . Display device
200．．．顯示單元200. . . Display unit
300、400、500、600．．．印刷電路板300, 400, 500, 600. . . A printed circuit board
301‧‧‧源極驅動器301‧‧‧Source Driver
302‧‧‧時序控制器302‧‧‧Sequence Controller
D1、Dk、Dk+1、Dm‧‧‧資料線D1, Dk, Dk+1, Dm‧‧‧ data lines
G1、G2、Gn‧‧‧閘極線G1, G2, Gn‧‧‧ gate line
第1圖係顯示根據本發明之一實施例所述之顯示裝置方塊圖。1 is a block diagram showing a display device according to an embodiment of the present invention.
第2圖係顯示根據本發明之一實施例所述之源極驅動器晶片之方塊圖。2 is a block diagram showing a source driver chip in accordance with an embodiment of the present invention.
第3圖顯示根據本發明之一第一實施例所述之驅動電路佈局圖。Figure 3 is a diagram showing the layout of a driving circuit according to a first embodiment of the present invention.
第4圖顯示根據本發明之一第二實施例所述之驅動電路佈局圖。Fig. 4 is a view showing a layout of a driving circuit according to a second embodiment of the present invention.
第5顯示根據本發明之一第三實施例所述之驅動電路佈局圖。Fig. 5 shows a layout of a driving circuit according to a third embodiment of the present invention.
第6顯示根據本發明之一第四實施例所述之驅動電路佈局圖。Fig. 6 shows a layout of a driving circuit according to a fourth embodiment of the present invention.
1．．．液晶顯示面板1. . . LCD panel
10．．．閘極驅動器晶片10. . . Gate driver chip
20-1、20-2．．．源極驅動器晶片20-1, 20-2. . . Source driver chip
100．．．顯示裝置100. . . Display device
200．．．顯示單元200. . . Display unit
D1、Dk、Dk+1、...Dm．．．資料線D1, Dk, Dk+1, ... Dm. . . Data line
G1、G2...Gn．．．閘極線G1, G2...Gn. . . Gate line
Claims (2)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/648,016 US20110157103A1 (en) | 2009-12-28 | 2009-12-28 | Display Device and Driving Circuit |
Publications (2)
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| TW201123134A TW201123134A (en) | 2011-07-01 |
| TWI431582B true TWI431582B (en) | 2014-03-21 |
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| TW099113636A TWI431582B (en) | 2009-12-28 | 2010-04-29 | Display devices and driving circuits |
Country Status (3)
| Country | Link |
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| US (2) | US20110157103A1 (en) |
| CN (1) | CN102110404B (en) |
| TW (1) | TWI431582B (en) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101237702B1 (en) * | 2010-11-19 | 2013-02-27 | 주식회사 실리콘웍스 | Circuit for controlling non-signal of plat panel display device |
| US9053673B2 (en) | 2011-03-23 | 2015-06-09 | Parade Technologies, Ltd. | Scalable intra-panel interface |
| US9106770B2 (en) * | 2011-06-21 | 2015-08-11 | Parade Technologies, Ltd. | Column drivers with embedded high-speed video interface timing controller |
| TWI441130B (en) * | 2011-10-18 | 2014-06-11 | Au Optronics Corp | Intergrated source driving system and displayer comprising the same |
| TWI434258B (en) * | 2011-12-09 | 2014-04-11 | Au Optronics Corp | Data driving apparatus, corresponding operation method and corresponding display |
| KR101941447B1 (en) | 2012-04-18 | 2019-01-23 | 엘지디스플레이 주식회사 | Flat display device |
| KR101987191B1 (en) | 2012-08-31 | 2019-09-30 | 엘지디스플레이 주식회사 | Liquid crystal display device and method for driving the same |
| TWI464731B (en) | 2012-09-20 | 2014-12-11 | Au Optronics Corp | Display-driving structure and signal transmission method thereof, displaying device and manufacturing method thereof |
| US8988416B2 (en) | 2012-12-14 | 2015-03-24 | Parade Technologies, Ltd. | Power reduction technique for digital display panel with point to point intra panel interface |
| TWI557705B (en) * | 2013-03-11 | 2016-11-11 | 瑞鼎科技股份有限公司 | Source driving circuit and data transmission method thereof |
| US9536495B2 (en) * | 2014-01-31 | 2017-01-03 | Samsung Display Co., Ltd. | System for relayed data transmission in a high-speed serial link |
| US10216302B2 (en) * | 2014-07-22 | 2019-02-26 | Synaptics Incorporated | Routing for an integrated display and input sensing device |
| KR101698930B1 (en) * | 2014-11-11 | 2017-01-23 | 삼성전자 주식회사 | Display driving device, display device and Opertaing method thereof |
| US9805693B2 (en) * | 2014-12-04 | 2017-10-31 | Samsung Display Co., Ltd. | Relay-based bidirectional display interface |
| CN204302618U (en) * | 2015-01-04 | 2015-04-29 | 京东方科技集团股份有限公司 | A kind of display device |
| KR102367246B1 (en) * | 2015-07-27 | 2022-02-25 | 삼성디스플레이 주식회사 | Display device |
| CN105405384A (en) * | 2015-12-31 | 2016-03-16 | 深圳市华星光电技术有限公司 | Display control circuit and display device |
| US10921855B1 (en) * | 2019-08-29 | 2021-02-16 | Synaptics Incorporated | Interposer for a display driver integrated circuit chip |
| CN111048030A (en) * | 2020-01-02 | 2020-04-21 | 昆山国显光电有限公司 | Drive chip and display device |
| KR102780731B1 (en) * | 2020-08-04 | 2025-03-12 | 엘지디스플레이 주식회사 | Interface Device And Method Of Display Device Including The Same |
| CN116504193B (en) * | 2022-01-26 | 2025-11-21 | 奇景光电股份有限公司 | Large-size touch display integration system and driving signal processing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100430097B1 (en) * | 1999-04-06 | 2004-05-03 | 엘지.필립스 엘시디 주식회사 | Driving Circuit of Monitor for Liquid Crystal Display |
| JP3508837B2 (en) * | 1999-12-10 | 2004-03-22 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Liquid crystal display device, liquid crystal controller, and video signal transmission method |
| US7098901B2 (en) * | 2000-07-24 | 2006-08-29 | Sharp Kabushiki Kaisha | Display device and driver |
| KR100864918B1 (en) * | 2001-12-26 | 2008-10-22 | 엘지디스플레이 주식회사 | Data driving device of liquid crystal display |
| TWI331743B (en) * | 2005-03-11 | 2010-10-11 | Chimei Innolux Corp | Driving system in a liquid crystal display |
| JP4567356B2 (en) * | 2004-03-31 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | Data transfer method and electronic apparatus |
| KR101090248B1 (en) * | 2004-05-06 | 2011-12-06 | 삼성전자주식회사 | Column driver and flat panel display having the same |
| TWI336876B (en) * | 2004-11-10 | 2011-02-01 | Himax Tech Inc | Data driving system and display having adjustable common voltage |
| US20060232579A1 (en) * | 2005-04-14 | 2006-10-19 | Himax Technologies, Inc. | WOA panel architecture |
| TWI348671B (en) * | 2006-08-16 | 2011-09-11 | Au Optronics Corp | A circuit for driving an lcd panel and a method thereof |
| TWI382390B (en) * | 2008-01-29 | 2013-01-11 | Novatek Microelectronics Corp | Impuls-type driving method and circuit for liquid crystal display |
-
2009
- 2009-12-28 US US12/648,016 patent/US20110157103A1/en not_active Abandoned
-
2010
- 2010-04-29 TW TW099113636A patent/TWI431582B/en active
- 2010-07-27 CN CN201010239601XA patent/CN102110404B/en not_active Expired - Fee Related
-
2012
- 2012-09-06 US US13/605,788 patent/US20130002621A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| CN102110404B (en) | 2013-04-24 |
| US20130002621A1 (en) | 2013-01-03 |
| TW201123134A (en) | 2011-07-01 |
| CN102110404A (en) | 2011-06-29 |
| US20110157103A1 (en) | 2011-06-30 |
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