TWI431299B - Multiple scan tree synthesis method and chip test device - Google Patents

Description

Test synthesis method for multi-scan tree test structure and wafer test device

The present invention relates to a test synthesis method and a wafer test apparatus for a multi-scan tree test structure, and in particular to a test synthesis method and a wafer test apparatus for simultaneously considering the position and number of winding lengths and scan outputs.

With the advancement of process technology, the testability design of the system is becoming more and more important. Compared to the multi-scan chain method, the traditional single scan chain test architecture has the disadvantages of long test data and long test time. The scan chain length is positively related to the test time. The multi-scan chain method can decompose the original single scan chain into multiple scan chains, which reduces the overall length of the scan chain, thereby greatly reducing the required test time. However, the multi-scan chain method has the disadvantage that the winding length is too long and the number of scan outs is excessive.

In addition, the amount of test data will increase greatly as the circuit becomes larger, and the architecture of the scan chain requires a large amount of test data to be tested in a single scan chain or multiple scan chains in today's complex ultra-large integrated circuit design. The tester memory requirements and test time increase with the amount of test data also increases the cost of testing. Therefore, the importance of compression of test data is increasing.

Therefore, an aspect of the present invention is to provide a test synthesis method for a multi-scan tree test structure and a wafer test device for testing a wafer, thereby simultaneously considering the length of the winding and the position and number of scan outputs, thereby greatly reducing scanning. The length of the winding required for the tree is up to the limit of the original output.

According to an embodiment of the present invention, the test synthesis method of the multi-scan tree test structure of the present invention is for testing a wafer, comprising the steps of: (a) dividing the circuit of the wafer into a plurality of partitions, wherein each Each of the divided regions has the same area, and each of the divided regions has a plurality of scanned cells; (b) in each of the divided regions, a plurality of original inputs according to each of the divided regions (Primary In And a plurality of positions of the primary output determine a scanning direction; (c) dividing the scanning cells into a plurality of points according to the positions of the scanned cells and the scanning direction of each of the divided regions a layer group, wherein the number of the scanned cells in each of the hierarchical groups is a predetermined multiple of the number of the scanned cells in the previous hierarchical group; (d) Each of the hierarchical groups finds a plurality of compatible groups having a minimum path length, wherein the number of scan outs of the compatible groups is less than a threshold; (e) Some compatible groups are connected in order to A plurality of scan tree; the plurality of scan cells, and (f) does not belong to the group of the plurality of connection to a compatible scan chain.

In an embodiment of the invention, in each of the divided regions, the scanning direction is toward the most densely spaced locations.

In an embodiment of the present invention, before finding the compatible groups, a compatible group map is established, and the relationship between the compatible groups is found in the compatible group map.

In an embodiment of the present invention, when the circuit is divided, the order of the division is determined by the number of the original outputs, and the segmentation is sequentially performed according to the number of the original outputs from large to small.

In one embodiment of the invention, the segmentation area located in the middle of the circuit is the last synthesis of the scan tree.

In an embodiment of the present invention, the step (f) includes: inserting the scan cells not belonging to the compatible groups into the scan tree according to a test application time limit; and leaving the scans remaining The cells are ligated to form a multi-scan strand.

In an embodiment of the present invention, after the step (a), the divided area having the maximum number of outputs and having not synthesized the scan trees is found.

In an embodiment of the present invention, after the step (e), it is checked whether the number of the scan trees in the divided regions is less than a predefined number of scan trees.

Moreover, according to an embodiment of the present invention, a wafer testing apparatus according to the present invention includes a scan input, a scan output, a division unit, a scanning direction determining unit, a hierarchical group unit, a compatible group generating unit, and a scanning cell connecting unit. The dividing portion is configured to divide the circuit of the wafer into a plurality of divided regions, wherein each of the divided regions has the same area, and each of the divided regions has a plurality of scanned cells. The scanning direction determining unit is configured to determine a scanning direction according to a plurality of original inputs and a plurality of original output positions of each of the divided regions in each of the divided regions. The layered group is configured to divide the scanned cells into a plurality of hierarchical groups according to the positions of the scanned cells and the scanning direction of each of the divided regions, wherein each of the hierarchical groups The number of the scanned cells within the previous one is a predetermined multiple of the number of the scanned cells in the previous hierarchical group. The compatible group generating unit is configured to find, in each of the hierarchical groups, a plurality of compatible groups having a minimum path length, wherein the number of the scan outputs of the compatible groups is less than a threshold. The scanning cell junction is used to sequentially connect the compatible groups to synthesize a plurality of scanning trees, and connect the scanning cells not belonging to the compatible groups into a scan chain.

Therefore, the test synthesis method and the wafer test apparatus of the multi-scan tree test structure of the present invention can simultaneously consider the winding length and the position and number of scan outputs to reduce the cost required to use the multi-scan tree test architecture. Moreover, the present invention can greatly reduce the length of the winding required for scanning the tree and reach the limit of the original output, and the synthesized scanning tree still has excellent results in the test time and the amount of test data.

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. It is to be understood that the embodiments are merely illustrative of the embodiments of the invention and are not intended to limit the invention.

Please refer to FIG. 1, which shows a block diagram of a test apparatus in accordance with an embodiment of the present invention. Test device 200 is used to test a wafer 100. Wafer 100, for example, can include a plurality of logic gates that can form a plurality of logic circuits for performing various functions. Since the number of logic gates constituting the logic circuit is rather large, in order to test whether the logic gate can operate normally, the test apparatus 200 can be provided to scan whether the circuit of the wafer 100 is operating normally.

Since the number of circuits (such as the number of logic gates) of the wafer 100 to be tested may be quite large, in order to save test time, multiple scan trees can be applied to reduce the test time. Among them, the Scan Tree is an architecture used to increase the compression of test data.

As shown in FIG. 1, the wafer testing apparatus 200 includes a plurality of scan inputs SI (Scan In) SI, a plurality of scan outputs (Scan Out) SO, a dividing unit 202, a scanning direction determining unit 204, a hierarchical grouping unit 206, and a phase. The volume generating unit 208 and the scanning cell connecting unit 210. The dividing portion 202 is configured to divide the circuit of the wafer 100 into a plurality of partitions 212, wherein each of the divided regions 212 has the same area, and each of the divided regions 212 has a plurality of scanning cells 214, wherein each scan Unit 214 can be viewed as a logic gate or line to be tested. The scanning direction determining unit 204 is configured to determine a scanning direction in each divided area 212 based on the positions of the primary input PI and the primary output PO of the divided area. The hierarchical grouping unit 206 is configured to divide the scanned cells into a plurality of hierarchical groups 216 according to the position of the scanned cells 214 and the scanning direction of the divided regions 212, wherein the scanning in each hierarchical group 216 The number of cells 214 is a predetermined multiple of the number of scanned cells 214 in the previous stratified group 216. The compatible group generation unit 208 is configured to find a plurality of compatible groups 218 having the least path length in each hierarchical group 216, wherein the number of scan output SOs of the compatible group 218 is less than a threshold (Threshold) ). The scanning cell connection unit 210 is configured to sequentially connect the compatible groups 218 to synthesize a plurality of scanning trees (Scan Tree, ST), and connect the scanning cells 214 not belonging to the compatible group 218 into a scan chain (Scan Chain) ).

Referring to FIG. 2 and FIG. 3, FIG. 2 is a flowchart showing a test synthesis method of a multi-scan tree test structure according to an embodiment of the present invention, and FIG. 3 is a view showing a wafer splitting and determining a scan direction according to an embodiment of the present invention. schematic diagram. When performing the test synthesis method of the multi-scan tree test structure of the present embodiment, first, the circuit of the wafer 100 is divided into a plurality of divided regions 212, wherein each of the divided regions 212 has the same area, and each of the divided regions 212 has A plurality of scanned cells are detected (step S301). In order to have a shorter winding distance, in the present embodiment, a circuit is partitioned so that the area of each divided area 212 is equal, but the scanned cells 214 and the original input contained in each divided area 212 are included. The number of PIs and the original output PO may not be the same. In the present embodiment, when the division of the circuit is performed, the order of division is determined by the number of original output POs, and the division is sequentially performed according to the number of original output POs from large to small. Therefore, the scan area synthesis method is performed by first finding the divided area 212 having the largest number of output pads and having not synthesized the scan tree (step S307).

As shown in FIGS. 2 and 3, next, in this divided area 212, a scanning direction is determined in accordance with the original input PI of the divided area 212 and the position of the original output PO (step S302). When the scan test is performed, the test data is input to the circuit from the original input PI, and is output from the original output PO to the outside of the circuit after the test is completed. Therefore, when synthesizing the scan tree, the scan input SI should be made as close as possible to the original input PI, and the scan output SO should be as close as possible to the original output PO to minimize the required winding path between the scan input and output and the boundary in the test architecture. The length of the winding path required to reduce the scanning tree is long. Therefore, the synthesis of the scanning tree needs to be directional, which is referred to herein as the scan direction.

As shown in FIG. 3, in the present embodiment, the scanning direction is defined as the direction in which test data is transmitted on the circuit. The test data is passed from left to right from the original input PI to the original output PO. In the actual design, the number of original input PIs is mostly greater than the number of scan trees. In terms of number, the original input PI does not impose restrictions on the synthesis of the scan tree. In contrast, in the scan tree architecture, the number of scan outputs SO of the scan tree is more than one hundred times the number of scan inputs SI, but the circuit of the chip 100 does not necessarily have a corresponding number of original output PO numbers for scan output. SO use. Therefore, in the method of the embodiment, the position and quantity of the original output PO are mainly used as a main reference, so that the scan output SO of the synthesized scan tree can be as close as possible to the original output PO, thereby obtaining fewer windings. The path is long.

Please refer to FIG. 4A, FIG. 4B and FIG. 4C, which are schematic diagrams showing the synthesis of a scan tree according to an embodiment of the present invention. When determining the scanning direction, first find the most dense division of the original output PO, and set the scanning direction to face the original output PO. Therefore, scan tree synthesis can be performed according to this direction and the original output PO of this divided region 212. After the scanning tree synthesis is finished, the used original output PO is excluded, and the original output PO in the remaining divided area 212 is found to be the most dense, to re-set the scanning direction, and continue to synthesize the next scanning tree. Taking FIG. 3 as an example, the divided area 212 at the lower right corner has the most scanned cells 214, and therefore, the segmentation is performed at the earliest. In this divided area 212, the right side has five original output POs in the most number of directions, so the scanning direction is to the right, that is, the scanning direction of the scanning tree is from left to right. However, it can be observed from FIG. 3 that the original output PO cannot be found in the middle of the divided area 212. Such a divided area 212 may be referred to as an internal partition. In the internal partition, since the scanning direction cannot be determined by the number of original output POs, in the present embodiment, a pseudo pad method is proposed so that the internal partition can also perform the scanning tree synthesis method normally.

As shown in FIG. 4A, FIG. 4B and FIG. 4C, it can be known from the execution order of the divided regions 212 that the internal partition is the last execution. When the internal partition is executed, the scan tree generated by the adjacent partition area 212 can be obtained first. Then, by scanning the scan tree in the scan tree in the adjacent divided regions 212, the scan tree of the scan output is connected to the boundary of the internal partition to become a virtual pad, and the virtual pads can be It is treated as the original output PO of the internal partition, and then the synthetic scan tree method is executed, and the connection is made after the scan tree is established.

Please refer to FIG. 2 and FIG. 5. FIG. 5 is a schematic diagram showing a hierarchical group of wafers according to an embodiment of the present invention. Next, the scanned cells 214 are divided into a plurality of hierarchical groups 216 according to the position of the scanned cells 214 and the scanning direction of the divided regions 212, wherein the number of scanned cells 214 in each hierarchical group 216 is the previous layer. A predetermined multiple of the number of scanned cells 214 within the group 216 (step S303). The compatibility between the scanned cells 214 depends on the corresponding test vector. Generally, when the compatible group 218 is searched in a group of scanned cells 214, the more than 214 cells are scanned, the chance of finding a larger compatible group is greater. Big. Thus, in this embodiment, a density-directed scan cell partition can be utilized to effectively control the number of scanned cells 214 in each hierarchical level 216, which can be followed in subsequent steps. Find the expected compatibility group 218 size.

In scanning tree synthesis, the size of the compatible group 218 within each hierarchical group 216 may exhibit a non-decreasing order in accordance with the scanning direction. If there are n scan tree hierarchical groups 216 (Level ₀ ~ Level _n-1 ) from the scan input SI to the scan output SO in the scan tree, it is assumed that the hierarchical group 216 (Level ₀ ~ Level _n-1 ) has The scanning cells are N ₀ ~N _n-1 , then N ₀ ≦N ₁ ≦...≦N _n-1 .

The primary purpose of performing density directed segmentation is to effectively control the number of cells scanned within each hierarchical group 216 within the scan tree. In density-oriented levelizing, the number of scanned cells 214 per stratified group 216 must be proportional to the number of scanned cells 214 in the previous hierarchical group 216. . Assuming that the common ratio is α (that is, a preset multiple), the equivalence relation can be expressed by the following formula (1):

N _{i +1} =N _i ×α,α≧1 (1)

Thus, by scanning the coordinates of the cells 214, n hierarchical groups 216 can be cut in accordance with the scanning direction.

The number of scanned cells 214 in each hierarchical group 216 is a multiple of the previous hierarchical group 216. For example, under the condition of α=1.1 and level=3, N ₀ =5, then N ₁ =5×1.1=6, N ₂ =6×1.1=7, and finally the remaining scanned cells 214 are assigned to the last. A hierarchical group 216, therefore, the last number of N ₂ is 8.

After leveling, it is known that each scanned cell 214 is in that hierarchical group 216, which facilitates the consideration of routing in the subsequent step of finding a compatible group 218.

As shown in FIG. 2, next, in each hierarchical group 216, a compatible group 218 having the least path length is sought, wherein the number of scan outputs SO of the compatible group 218 is less than the threshold value (step S304). In order not to increase the number of scan output SOs, the following formula (2) must be met when building the scan tree:

CG ₀ ≦ CG ₁ ≦...≦ CG _{n - 1} (2)

CG _i represents the size of the compatible group 218 found in a certain hierarchical group 216.

In step S303, information of each of the scanned cells 214 and the segmentation region 212 is obtained. Defining a ratio λ, when looking for the compatible group 218 of the hierarchical group 216, the number of scanned cells 214 in the contig group 216 in the compatible group 218 needs to be greater than the size of the entire compatible group 218. Times, λ is between 0 and 1. When λ=0, it means that the proportion of the layered group 216 in which the scanned cells 214 are located in the compatible group 218 is not limited, and if there is a large compatible group size, there is a better test compression ratio. In contrast, since there is no need to consider the position of the scanned cells 214, there may be a poor winding length. When λ = 1, it means that the scanned cells 214 within the compatible group 218 in each hierarchical group 216 are strictly limited to be in the same hierarchical group 216. Since the same compatible group 218 needs to be selected, the size of the compatible group 218 found will be smaller and have more test data. But at the same time, it will have less winding length. When 0<λ<1, it means that a certain proportion of scanned cells 214 will be located in the same hierarchical group 216, which has an influence on the winding and the amount of test data. Therefore, the lambda value can be flexibly adjusted to meet the actual demand. .

Please refer to FIG. 6, which shows a schematic diagram of a compatible group diagram in accordance with an embodiment of the present invention. To limit the number of scan outputs SO for each scan tree, set a threshold, initially the number of scan output pads. Before finding the compatible group 218, a compatible group map can be established, and then the relationship is found in the compatible group map. As shown in Fig. 6, the 12 points in Fig. 6 can represent the scanned cells 214, and the lines between the points represent the compatibility of the scanned cells 214. If there is compatibility, the lines are connected, and the hatching points of the points represent the points. Layer group 216, the same hatching represents the same hierarchical group 216. In the hierarchical group 216 (level _n-1 ), the largest compatible group (CG) 218 smaller than the threshold value is searched, and the proportion of the scanned cells 214 in the compatible group 218 located in the level _n-1 needs to be larger than the overall size. λ times. Then set the threshold to the size of CG. Continue to find the compatible group 218 of level _n-2 to level ₀ in the same way.

Please refer to FIG. 7, which shows a schematic diagram of a compatible group in accordance with an embodiment of the present invention. For example, when λ=0.5 and looking for a compatible group of level ₂ , the compatible group 218 in the dotted line at this time is the compatible group 218 conforming to the λ limit, and then the compatible group 218 having the largest size is selected. For what you ask for. Figure 7 is a complete view of finding a compatible group 218, where λ = 0.5, level = 3, so there will be a total of three compatible groups 218.

Please refer to FIG. 2 and FIG. 8. FIG. 8 is a schematic diagram showing a connection compatible group according to an embodiment of the present invention. Next, the compatible groups 218 are sequentially connected (step S305) to synthesize a plurality of scan trees. In step S304 compatible group found 218 are in compliance with Equation (2), therefore, to be connected to _I if CG CG _{i + 1,} the scan cells CG _I must be connected to all scan cells CG _{i + 1} of 214,214 Thereby, the scan output SO is not generated in the CG _i . This problem can therefore be considered as an assignment problem, so the Hungarian method can be used to solve the algorithm for this assignment problem. The Hungarian algorithm was proposed by Harold Kuhn in 1955. It has a time complexity of polynomial time, so it can quickly solve the assignment problem and reduce the overall cost. The execution steps of the Hungarian algorithm are as follows:

1. Establish a distance matrix

Assuming |CG _i |=n, |CG _i+1 |=m, a distance matrix is created which records the distance between two compatible group of scanned cells, CG _i and CG _i+1 . However, the square matrix is applicable to the Hungarian algorithm, so it is necessary to fill the smaller cell CG with the pseudo cell until the square matrix is formed.

2. Reduction of the distance matrix

Find the smallest value from each row and subtract all the elements of the row from this minimum. This step is called column reducing. Then, as in the above formula, find a small value from each column and subtract it. This step is called row reducing.

3. Find the biggest match

Find the largest matching from the 0 in the distance matrix of column and row reducing. Each time you find a matching, observe the column and column containing the value. If the column contains more 0, , then mark all the columns, if it is a row, mark the row. If the maximum number of matching found is equal to the number of rows, the algorithm ends, otherwise the next step is taken.

4. Find the biggest match

At this point, the distance matrix needs to be modified to produce more zero values. Modified conditions: (1) Select a minimum value from the elements that have not been marked, and then subtract all the elements that have not been marked. (2) Add this minimum value to any two elements that mark their intersection. (3) Other elements that are within the mark and that are not intersecting remain unchanged. When this step is completed, skip to step 3 to continue.

Hungarian algorithm after the above steps, to ensure that all scan cells _I CG are connected CG _{+. 1} scan cells in _I. The remaining CG _i+1 has not been connected to the scanned cells, just look for the nearest scanned cells to connect, as shown in Figure 1. Thereafter, it is checked whether the number of scan trees in the divided area 212 is less than a predefined number of scan trees (step S308). If it is less than the predefined number of scan trees, then return to step S302 to continue to find a tree. If it is equal to the number of custom scan trees, confirm whether all the split regions have been executed. If all the split regions have been executed, proceed to the next step. If the split region is not executed, find the next one with the most output. The scan tree synthesis method is performed by dividing the number of regions and not dividing the segmentation area 212 of the scan tree.

As shown in FIG. 2, next, the scanned cells 214 (scattered points) not belonging to the compatible groups 218 are connected into a scan chain (step S306). In order to consider the winding and test application time (TAT), a TAT value is set as a limitation of TAT. Then, according to the available scan output SO number, the remaining scanned cells 214 are established as a scan chain, and the overall scan output SO number cannot exceed the number of original output POs. In this embodiment, the processing steps are divided into two types: A. Inserting into a scan tree; B. Establishing a multi-scan chain.

A. Insert into the scan tree

This step is divided into two parts. The first part is to insert the scattered point into the tree according to the TAT limit. Here, assuming a TAT limitation, it is hoped that all scan trees and the established scan chains will not exceed the limit of this TAT. At this point, a scattered point is inserted for each tree so that the tree height of each tree is equal to TAT. The method of inserting starts to find the closest scattered point of the scan input input SI or the scan output SO. The height of the scan tree is increased by 1 every time a scattered point is connected, and stops when the height of the tree is equal to TAT. The second part is to perform the compatibility group test on all the tree levels in the remaining scattered point. If the test result is compatible, it means that the scattered point can be inserted into the tree level, and each time a scattered point is inserted. Add a scan output SO, so you must limit the number of inserts. The maximum value of the number of scan output SO is equal to the number of original output PO of the circuit. Under this condition, if the number of scan output SO is still smaller than the original output PO, then:

Where R _so represents the number of scan output SOs that can be further increased. However, some scan output SO numbers are reserved for use in multiple scan chains. Let #sca be the number of scattered points remaining at this time, then we can calculate:

# SC =# sca/TAT (4)

Among them, #SC represents the initial number of scan chains. Let Tsp be the total number that can be inserted, and know from (3)(4):

T _sp =R _SO -#SC (5)

Thus, the _Tsp value can be obtained. When doing the tree level compatibility group test, the added winding length will be recorded. After the compatible group test is completed at each scattered point, the winding length is sorted from small to large, and the pre-T _sp scattered points are taken for insertion, thereby avoiding exceeding the limit of the overall original output PO.

B. Establish multiple scan chains

This part is to connect the remaining scattered points to form a multiple scan chain. It is known from (5) that T _sp scattered points have been used, so the number of scan chains at this time is:

Where #SC' is the number of scan chains to be established. The established scan chain preferably needs to meet the following restrictions:

1) The height of each tree should be the same, and the height should not exceed Hmax.

2) Have a shorter winding length.

3) The two ends of each scan chain can be as close as possible to the interface.

Referring to Figures 9A through 9C, there are shown schematic views of scanned cells in accordance with an embodiment of the present invention. In order to satisfy the above limitation, in the present embodiment, an algorithm for considering both the winding and the boundary limit is proposed. This algorithm is divided into the following three parts:

1) Modified DB scan

For any one scan chain SC _i , look for any PI and PO on the circuit as the SI and SO of the scan chain. It is assumed here that a _i , b _i (such as a ₁ , a ₂ , b ₁ , b ₂ ) are the found scan input SI and the scan output SO, and connect a _i and b _i (ab), and then find two The parallel lines P _i , Q _i (such as P ₁ , P ₂ , Q ₁ , Q ₂ ) are each at a distance of 1 from ab, and the scattered points in P _i and Q _i are added to their weights by one. As shown in Figure 9A. The weight of each scattered point represents the number of times this scattered point is contained by P _i , Q _i , and the initial value is 0. Then, using the above method, the execution is repeated until all the trees are found. At this point, there are still some scattered points that have not passed, as shown in Figure 9B, thus increasing the value of 1 and repeating the above actions until all scattered point index values > 0 are stopped, as shown in Figure 9C.

2) Select the point of the scan chain

From the previous step, it can be known that each scan chain has its own scattered points included in a, b, and P, and Q. H _max is the length of the scan chain required for the scan chain i, and then the scattered point between P _i and Q _i is selected, and the weight values are sequentially selected until the H _{max is} satisfied.

3) Connect the scanned cells 214 into a scan chain

In the above step, the scanned cells 214 required for each scan chain are obtained, and then these scanned cells 214 are joined into a scan chain. In the case of fixed scan in/out, it is ensured that the length of the connected scan chain is the shortest, so that the connection order of a set of scan chains can be obtained and the winding distance is the shortest. Finally, the scanning cells 14 are connected in accordance with this connection sequence, thus completing the scan chain.

It can be seen from the above embodiments of the present invention that the test synthesis method and the wafer test apparatus of the multi-scan tree test structure for testing a wafer of the present invention can simultaneously consider the position and number of the winding length and the scan output to reduce the use of the multi-scan tree. The cost of testing the architecture. Compared with the conventional testing method and device, the invention can greatly reduce the length of the winding required for scanning the tree and meet the limitation of the original output, and the synthesized scanning tree is still excellent in the test time and the amount of test data. the result of. Furthermore, since the present invention also considers the distance between the scan output of the scan tree and the original output, it has a shorter winding distance and maintains the advantages of high data compression rate and low test time of the scan tree.

In view of the above, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the invention, and the present invention may be made without departing from the spirit and scope of the invention. Various modifications and refinements are made, and the scope of the present invention is defined by the scope of the appended claims.

PI. . . Original input

PO. . . Raw output

SI. . . Scan input

SO. . . Scan output

100. . . Wafer

200. . . Test device

202. . . Division

204. . . Scanning direction decision

206. . . Hierarchical group

208. . . Compatible group generation

210. . . Scanning cell junction

212. . . Split area

214. . . Scanning cells

216. . . Hierarchical group

218. . . Compatible group

S301. . . Dividing the circuit of the wafer into multiple divided regions

S302. . . Determine the scanning direction

S303. . . Split the scanned cells into a plurality of hierarchical groups

S304. . . Find compatible groups

S305. . . Connect the compatible groups sequentially

S306. . . Connect scanned cells that are not part of a compatible group into a scan chain

S307. . . Find the partition with the most output and not yet synthesized the scan tree

S308. . . Whether the number of scan trees in the split area is less than the number of predefined scan trees

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

1 shows a block diagram of a test apparatus in accordance with an embodiment of the present invention.

2 is a flow chart showing a test synthesis method of a multi-scan tree test structure in accordance with an embodiment of the present invention.

3 is a schematic diagram showing the division of a wafer and determining the scanning direction in accordance with an embodiment of the present invention.

4A, 4B and 4C are schematic diagrams showing the synthesis of a scan tree in accordance with an embodiment of the present invention.

Figure 5 shows a schematic diagram of a hierarchical group of wafers in accordance with an embodiment of the present invention.

Figure 6 shows a schematic diagram of a compatible group map in accordance with an embodiment of the present invention.

Figure 7 shows a schematic diagram of a compatible group in accordance with an embodiment of the present invention.

Figure 8 shows a schematic diagram of a connection compatible group in accordance with an embodiment of the present invention.

9A-9C show schematic views of scanned cells in accordance with an embodiment of the present invention.

SI. . . Scan input

SO. . . Scan output

100. . . Wafer

200. . . Test device

202. . . Division

204. . . Scanning direction decision

206. . . Hierarchical group

208. . . Compatible group generation

210. . . Scanning cell junction

Claims (9)

A test synthesis method for a multi-scan tree test structure for testing a wafer comprising the steps of: (a) dividing a circuit of the wafer into a plurality of partitions, wherein the area of each of the divided regions All of the same, and each of the divided regions has a plurality of scanned cells; (b) in each of the divided regions, a plurality of original inputs and a plurality of original outputs according to each of the divided regions ( The position of the primary out) determines a scanning direction; (c) dividing the scanned cells into a plurality of hierarchical groups according to the positions of the scanned cells and the scanning direction of each of the divided regions, The number of the scanned cells in each of the hierarchical groups is a predetermined multiple of the number of the scanned cells in the previous hierarchical group; (d) in each of the hierarchical groups In the group, searching for a plurality of compatible groups having a minimum path length, wherein the number of scan outs of the compatible groups is less than a threshold; (e) sequentially performing the compatible groups Connect to synthesize multiple sweeps Tree; the plurality of scan cells, and (f) does not belong to the group of the plurality of connection to a compatible scan chain. The method of claim 1, wherein in each of the divided regions, the scanning direction is toward a densest position of the original outputs. The method of claim 1, wherein before finding the compatible groups, a compatible group map is established, and the relationship between the compatible groups is found in the compatible group map. The method of claim 1, wherein when the circuit of the chip is divided, the order of dividing the circuit is determined by the number of original outputs, and the number of original outputs is determined by Go to the small to perform the split in order. The method of claim 1, wherein the segmentation area located in the middle of the circuit is the last execution of the synthesis of the scan trees. The method of claim 1, wherein the step (f) comprises: inserting the scanned cells not belonging to the compatible groups into the scan trees according to a test application time limit; The scanned cells are connected to form the scan strand. The method of claim 1, wherein after the step (a), finding the divided area having the maximum number of outputs and not synthesizing the scan trees. The method of claim 1, wherein after the step (e), checking whether the number of the scan trees in the divided regions is less than a predefined number of scan trees. A wafer testing device for testing a wafer, comprising: a plurality of scan inputs (Scan In) and a plurality of scan outputs; a dividing portion for dividing a circuit of the chip into a plurality of divided regions, wherein each The divided areas have the same area, and each of the divided areas has a plurality of scanning cells; a scanning direction determining unit is configured to, in each of the divided areas, a plurality of original inputs according to each of the divided areas. And a plurality of positions of the original output, determining a scanning direction; a layering group portion for dividing the scanning cells into a plurality of scanning cells according to the positions of the scanning cells and the scanning direction of each of the divided regions a hierarchical group, wherein the number of the scanned cells in each of the hierarchical groups is a predetermined multiple of the number of the scanned cells in the previous hierarchical group; a compatible group generating unit And searching, in each of the hierarchical groups, a plurality of compatible groups having a minimum path length, wherein the number of the scan outputs of the compatible groups is less than a threshold; and scanning cells Portion to the compatibility of these groups are connected in sequence, to synthesize a plurality of scanning the tree, and the plurality of scan cells not belonging to the group of the plurality of connections into a compatible scan chain.