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TWI429181B - Apparatus and method for switching converter - Google Patents

Apparatus and method for switching converter Download PDF

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Publication number
TWI429181B
TWI429181B TW99124160A TW99124160A TWI429181B TW I429181 B TWI429181 B TW I429181B TW 99124160 A TW99124160 A TW 99124160A TW 99124160 A TW99124160 A TW 99124160A TW I429181 B TWI429181 B TW I429181B
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circuit
voltage
transistor
coupled
signal
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TW99124160A
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TW201206038A (en
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Qian Ouyang
Yuancheng Ren
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Monolithic Power Systems Inc
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Description

開關變換器的裝置及方法Switching converter device and method

本發明一般係有關電源,更具體地說,係有關開關變換器。The present invention is generally related to power supplies, and more particularly to switching converters.

大多數電子產品,諸如筆記型電腦、桌上型電腦、PDA等,需要直流(DC)電源向各個功能模組提供經過調節的功率。DC-DC同步降壓式變換器具有效率高、體積小等優點,而獲得到了廣泛的應用。低的電壓波紋和快速的暫態響應是DC-DC同步降壓式變換器最基本的要求。Most electronic products, such as notebook computers, desktop computers, PDAs, etc., require a direct current (DC) power supply to provide regulated power to each functional module. The DC-DC synchronous buck converter has the advantages of high efficiency and small size, and has been widely used. Low voltage ripple and fast transient response are the most basic requirements for DC-DC synchronous buck converters.

滯環控制電路具有暫態響應速度快、結構簡單等優點,可以作為DC-DC同步降壓式變換器的控制電路,如圖1所示,輸入電壓經由電晶體101和102的調變,被耦合到由電感器103和電容器104所組成的輸出濾波器,濾波之後的電壓被輸出到負載電阻105,輸出電壓Vout 經由由電阻器106和107所構成的電壓取樣電路而將電壓取樣信號FB反饋到滯環比較器108的輸入端,與上限閥值電壓VH 和下限閥值電壓VL 相比較,滯環比較器108的輸出信號係耦接到驅動電路109,驅動電路109產生相應的驅動信號,以控制電晶體101和102的導通和關斷,電晶體101和102的閘極驅動信號是互補的。圖1的示例示出,電晶體101和102為金屬氧化物半導體場效電晶體(MOSFET),在其他示例中,可以使用諸如雙極接面電 晶體(BJT)或絕緣閘雙極電晶體(IGBT)之類的其他適當電子設備來加以實現。圖2示出了圖1中之電壓取樣信號FB、電晶體101和102的閘極驅動信號波形。反饋信號FB達到上限閥值VH 時,電晶體101被關斷,電晶體102被導通,當反饋信號FB達到下限閥值VL 時,電晶體102被關斷,電晶體101被導通。但滯環控制電路過分依賴輸出電壓諧波,經由將電壓諧波與上下兩個閥值電壓相比較來產生上下兩個電晶體的控制信號,變換器的輸出電壓諧波無法被控制在理想範圍內,變換器的切換頻率也會因週邊元件和操作條件的改變而發生變化。The hysteresis control circuit has the advantages of fast transient response speed and simple structure, and can be used as a control circuit of a DC-DC synchronous buck converter. As shown in FIG. 1, the input voltage is modulated by the transistors 101 and 102. coupled to an output filter inductor 103 and a capacitor 104 composed of voltage after filtering is output to a load resistor 105, output voltage V out through the voltage sampling circuit by the resistors 106 and 107 constitute a voltage sampling while the signal FB Feedback to the input of the hysteresis comparator 108, compared to the upper threshold voltage V H and the lower threshold voltage V L , the output signal of the hysteresis comparator 108 is coupled to the drive circuit 109, and the drive circuit 109 generates a corresponding The signals are driven to control the turn-on and turn-off of transistors 101 and 102, and the gate drive signals of transistors 101 and 102 are complementary. The example of FIG. 1 shows that the transistors 101 and 102 are metal oxide semiconductor field effect transistors (MOSFETs), and in other examples, such as bipolar junction transistors (BJT) or insulated gate bipolar transistors ( Other suitable electronic devices such as IGBTs are implemented. 2 shows the gate drive signal waveforms of the voltage sampling signal FB, the transistors 101 and 102 of FIG. When the feedback signal FB reaches the upper limit threshold V H , the transistor 101 is turned off, the transistor 102 is turned on, and when the feedback signal FB reaches the lower limit threshold V L , the transistor 102 is turned off, and the transistor 101 is turned on. However, the hysteresis control circuit relies excessively on the output voltage harmonics. By comparing the voltage harmonics with the upper and lower threshold voltages to generate the control signals of the upper and lower transistors, the output voltage harmonics of the converter cannot be controlled within the ideal range. Within this, the switching frequency of the converter also changes due to changes in peripheral components and operating conditions.

圖3示出了採用恒定導通時間(COT)控制電路的DC-DC同步降壓式變換器電路。輸出電壓Vout 經由電壓取樣電路而將電壓取樣信號FB反饋到比較器308的輸入端,與參考電壓信號VREF 相比較,比較器308的輸出信號被耦接到驅動電路109,同時導通計時電路310也被耦接到驅動電路109,經由將電壓取樣信號FB與參考電壓信號VREF 相比較來產生電晶體101的導通信號,電晶體101的導通時間是固定的,由導通計時電路310所控制。這種方法減小了輸出電壓的諧波,但是電晶體101的關斷時間是可變的,變換器的切換頻率也會相應變化。由於採用恒定導通時間控制,省略了上限閥值電壓,如果在電晶體101導通時刻產生負載跳變的情況,電路無法做出迅速的暫態響應,必須等到導通時間結束才能關斷電晶體101,這會導致輸出電壓有較大幅度的變化。圖4示出了 圖3中之電壓取樣信號FB和電晶體101閘極驅動信號的波形。當反饋信號FB達到參考電壓信號VREF 時,電晶體101被導通,導通時間Ton 係由導通計時電路310所控制。採用恒定導通時間(COT)控制電路的DC-DC同步降壓式變換器電路,輸出電壓諧波獲得到了改善,但切換頻率仍然會因週邊元件和操作條件的改變而發生變化,並且惡劣情況下的暫態響應速度會受到限制。Figure 3 shows a DC-DC synchronous buck converter circuit employing a constant on-time (COT) control circuit. Output voltage V out through the voltage sampling circuit and the voltage sampling signal FB back to the input terminal of the comparator 308, compared with the reference voltage signal V REF, the output signal of the comparator 308 is coupled to a driving circuit 109, while the on-time clocking circuit 310 is also coupled to the driving circuit 109, and generates a conduction signal of the transistor 101 by comparing the voltage sampling signal FB with the reference voltage signal V REF . The on-time of the transistor 101 is fixed, and is turned on by the conduction timing circuit 310. control. This method reduces the harmonics of the output voltage, but the turn-off time of the transistor 101 is variable and the switching frequency of the converter changes accordingly. Since the constant on-time control is used, the upper threshold voltage is omitted. If the load jump occurs when the transistor 101 is turned on, the circuit cannot make a rapid transient response, and the transistor 101 must be turned off after the on-time is over. This causes a large change in the output voltage. Fig. 4 shows waveforms of the voltage sampling signal FB and the transistor 101 gate driving signal of Fig. 3. When the feedback signal FB signal reaches the reference voltage V REF, the transistor 101 is turned on, the on-time T on is controlled by a system timing circuit 310 is turned on. The DC-DC synchronous buck converter circuit with constant on-time (COT) control circuit has improved the output voltage harmonics, but the switching frequency will still change due to changes in peripheral components and operating conditions, and under severe conditions The transient response speed is limited.

本發明的目的在於提供一種開關變換器的裝置,使其輸出電壓波紋控制在小的範圍內,具有快速的暫態響應速度,電晶體的切換頻率穩定。It is an object of the present invention to provide a device for a switching converter that has its output voltage ripple controlled within a small range, has a fast transient response speed, and has a stable switching frequency of the transistor.

本發明的目的在於提供一種開關變換器的方法,將該開關變換器的輸出電壓波紋控制在小的範圍內,使其具有快速的暫態響應速度,以確保電晶體的切換頻率穩定。It is an object of the present invention to provide a method of switching a converter that controls the output voltage ripple of the switching converter to a small range to have a fast transient response speed to ensure stable switching frequency of the transistor.

為了實現上述發明目的,開關變換器電路包括:輸入端子,以接收輸入電壓;輸出端子,係耦接到負載電路,而為所述負載電路提供輸出電壓;反饋電路,係與輸出電壓相耦接,以提供反饋信號給驅動電路;驅動電路,係與反饋電路相耦接,以輸出驅動信號;開關電路,基於驅動電路輸出的驅動信號而切換電晶體導通或關斷。In order to achieve the above object, a switching converter circuit includes: an input terminal for receiving an input voltage; an output terminal coupled to the load circuit to provide an output voltage for the load circuit; and a feedback circuit coupled to the output voltage To provide a feedback signal to the driving circuit; the driving circuit is coupled to the feedback circuit to output the driving signal; and the switching circuit switches the transistor to be turned on or off based on the driving signal output by the driving circuit.

在一個實施例中,所述反饋電路包括電壓取樣電路,對所述輸出電壓進行取樣,以產生電壓取樣信號。In one embodiment, the feedback circuit includes a voltage sampling circuit that samples the output voltage to generate a voltage sampling signal.

在一個實施例中,所述反饋電路還包括導通計時電 路,所述導通計時電路輸出導通計時信號。In one embodiment, the feedback circuit further includes a turn-on timing The turn-on timing circuit outputs a turn-on timing signal.

在一個實施例中,所述反饋電路還包括自適應模組,所述自適應模組接收所述驅動信號和導通計時信號,以輸出上限閥值電壓和下限閥值電壓。In one embodiment, the feedback circuit further includes an adaptive module that receives the drive signal and the turn-on timing signal to output an upper threshold voltage and a lower threshold voltage.

在一個實施例中,所述反饋電路還包括比較器電路,所述比較器電路將所述電壓取樣信號與所述上限閥值電壓和所述下限閥值電壓相比較,以產生所述反饋信號。In one embodiment, the feedback circuit further includes a comparator circuit that compares the voltage sampling signal with the upper threshold voltage and the lower threshold voltage to generate the feedback signal .

在一個實施例中,所述導通計時電路係耦合到所述輸入電壓,包括一個由至少一個鏡像電流源和一個第一電容器所耦接而成的充電電路,和一個比較電路;所述第一電容器的一端係耦接到所述比較電路,與一個參考電壓相比較,以產生所述導通計時信號。In one embodiment, the on-time circuit is coupled to the input voltage, including a charging circuit coupled by at least one mirror current source and a first capacitor, and a comparison circuit; One end of the capacitor is coupled to the comparison circuit and compared to a reference voltage to generate the turn-on timing signal.

在一個實施例中,所述自適應模組包括一個由至少一個第一電晶體和一個第一電流源所耦接而成的放電電路,和一個由至少一個第二電晶體和一個第二電流源所耦接而成的充電電路。In one embodiment, the adaptive module includes a discharge circuit coupled by at least one first transistor and a first current source, and a second transistor and a second current A charging circuit coupled to the source.

在一個實施例中,所述第一電晶體的閘極係耦接到所述驅動電路輸出的驅動信號,所述第二電晶體的閘極係耦接到所述導通計時信號。In one embodiment, the gate of the first transistor is coupled to a driving signal output by the driving circuit, and the gate of the second transistor is coupled to the conduction timing signal.

在一個實施例中,所述自適應模組還包括一個與放電電路、充電電路相耦接的第二電容器,所述第一電晶體被導通時,第一電流源給所述第二電容器放電;所述第二電晶體被導通時,所述第二電流源給所述第二電容器充電。In one embodiment, the adaptive module further includes a second capacitor coupled to the discharge circuit and the charging circuit. When the first transistor is turned on, the first current source discharges the second capacitor. The second current source charges the second capacitor when the second transistor is turned on.

在一個實施例中,所述自適應模組還包括參考電壓 源,輸出所述下限閥值電壓;所述參考電壓源與一個滯環電壓源相耦接後,與所述第二電容器相耦接;所述參考電壓源、滯環電壓源和第二電容器三者的電壓相加後,輸出所述上限閥值電壓。In one embodiment, the adaptive module further includes a reference voltage a source, outputting the lower threshold voltage; the reference voltage source coupled to a hysteresis voltage source and coupled to the second capacitor; the reference voltage source, a hysteresis voltage source, and a second capacitor After the voltages of the three are added, the upper threshold voltage is output.

在一個實施例中,所述自適應模組還包括參考電壓源,輸出所述上限閥值電壓;所述參考電壓源與負的一個滯環電壓源相耦接後,與所述第二電容器相耦接;所述參考電壓源電壓減去滯環電壓源電壓、第二電容器電壓後,輸出所述下限閥值電壓。In one embodiment, the adaptive module further includes a reference voltage source that outputs the upper threshold voltage; the reference voltage source is coupled to a negative hysteresis voltage source, and the second capacitor The phase voltage is coupled to the reference voltage source voltage, and after the hysteresis voltage source voltage and the second capacitor voltage are subtracted, the lower threshold voltage is output.

在一個實施例中,所述開關電路包括第一電晶體和第二電晶體,其中,第一電晶體的源極與第二電晶體的汲極相耦接作為輸出端,再經濾波電路而與輸出端子相耦接。In one embodiment, the switching circuit includes a first transistor and a second transistor, wherein a source of the first transistor is coupled to a drain of the second transistor as an output, and then a filter circuit It is coupled to the output terminal.

在一個實施例中,所述驅動信號為兩路互補的脈衝信號,係分別耦接到第一電晶體、第二電晶體的閘極。In one embodiment, the driving signals are two complementary pulse signals coupled to the gates of the first transistor and the second transistor, respectively.

本發明採用上述結構的裝置和/或方法,經由電壓取樣電路取樣開關變換器輸出電壓信號,經由反饋電路而被提供給驅動電路,以控制電晶體的導通與關斷,可以對輸出電壓進行調節;自適應控制電路提供上下限閥值電壓,使開關變換器具有快速的暫態響應速度,即使是最惡劣的情況也能快速響應;另外,自適應控制電路能夠根據開關變換器的實際操作情況,調節上限閥值電壓和/或下限閥值電壓,以使電晶體的切換頻率穩定。The present invention adopts the above-mentioned structure device and/or method, and samples the output voltage signal of the switching converter via the voltage sampling circuit, and is supplied to the driving circuit via the feedback circuit to control the turning on and off of the transistor, and the output voltage can be adjusted. The adaptive control circuit provides upper and lower threshold voltages, so that the switching converter has a fast transient response speed, which can respond quickly even in the worst case. In addition, the adaptive control circuit can be based on the actual operation of the switching converter. The upper threshold voltage and/or the lower threshold voltage are adjusted to stabilize the switching frequency of the transistor.

揭示一種用於開關變換器的方法和裝置。在以下描述中,為了提供對本發明的透徹理解,闡述了許多特定細節。然而,對於本領域普通技術人員顯而易見的是:不必採用這些特定細節來實行本發明。在其他實例中,為了避免混淆本發明,並未具體描述公知的材料或方法。A method and apparatus for a switching converter is disclosed. In the following description, numerous specific details are set forth in order to provide a However, it will be apparent to those skilled in the art that the invention In other instances, well-known materials or methods have not been specifically described in order to avoid obscuring the invention.

在整個說明書中,對“一個實施例”、“實施例”、“一個示例”或“示例”的提及意謂:結合該實施例或示例描述的特定特徵、結構或特性被包含在本發明至少一個實施例中。因此,在整個說明書的各個地方出現的短語“在一個實施例中”、“在實施例中”、“一個示例”或“示例”不一定都指同一個實施例或示例。此外,可以以任何適當的組合和/或子組合而將特定的特徵、結構或特性組合在一個或多個實施例或示例中。此外,本領域普通技術人員應當理解,在此提供的示圖都是為了說明的目的,並且示圖不一定是按比例來予以繪製的。Reference throughout the specification to "one embodiment", "an embodiment", "an" or "an" or "an" In at least one embodiment. The appearances of the phrase "in one embodiment", "in the embodiment", "the" Furthermore, the particular features, structures, or characteristics may be combined in one or more embodiments or examples in any suitable combination and/or sub-combination. In addition, those skilled in the art should understand that the drawings are provided for the purpose of illustration, and the drawings are not necessarily drawn to scale.

圖5為根據本發明的一個實施例,輸入電壓被耦合到輸入電容器和開關電路,開關電路係由電晶體101和102所組成,電晶體101和102的公共點係耦接到由電感器103和電容器104所構成的濾波器,而濾波器的輸出係耦合到負載電路。自適應滯環控制電路511的一個輸入端係耦接到電晶體101的閘極,以接收其驅動控制信號HS,自適應滯環控制電路511的另一個輸入端係耦接到導通計時電路510,以接收其導通計時信號。自適應滯環控制電路511的輸出信號係分別耦接到滯環比較器508的兩個輸 入端,而為其提供上限閥值電壓VH 和下限閥值電壓VL 。由電阻器106和107所構成的電壓取樣電路,對輸出電壓Vout 進行取樣,將電壓取信號FB反饋到滯環比較器508的另一個輸入端。滯環比較器508將電壓取樣信號FB與上下限閥值電壓相比較,將比較結果耦接到驅動電路109,驅動電路109根據比較結果而輸出互補的驅動信號,以控制電晶體101和102的導通和關斷。5 is an input voltage coupled to an input capacitor and a switching circuit, the switching circuit is composed of transistors 101 and 102, and a common point of the transistors 101 and 102 is coupled to the inductor 103, in accordance with an embodiment of the present invention. And a filter formed by capacitor 104, and the output of the filter is coupled to the load circuit. One input of the adaptive hysteresis control circuit 511 is coupled to the gate of the transistor 101 to receive its drive control signal HS, and the other input of the adaptive hysteresis control circuit 511 is coupled to the turn-on timing circuit 510. To receive its turn-on timing signal. The output signals of the adaptive hysteresis control circuit 511 are coupled to the two inputs of the hysteresis comparator 508, respectively, to which an upper threshold voltage V H and a lower threshold voltage V L are provided . , The output voltage V out is sampled by resistors 106 and 107 constitute a voltage sampling circuit, the feedback signal FB takes the voltage to the other input terminal of the hysteresis comparator 508. The hysteresis comparator 508 compares the voltage sampling signal FB with the upper and lower threshold voltages, couples the comparison result to the driving circuit 109, and the driving circuit 109 outputs a complementary driving signal according to the comparison result to control the transistors 101 and 102. Turn on and off.

圖6為本發明中導通計時電路510的一個實施例。導通計時電路510係耦接到輸入電壓Vin ,鏡像電流源601以電流I給電容器602充電,電容器602上的電壓係耦接到比較器603的輸入端,藉由設定鏡像電流源601與電容器602就可以確定導通計時信號。參考電壓信號VREF 係耦接到比較器603的另一個輸入端,與電容器602上電壓相比較,比較器603根據比較結果而輸出導通計時信號,導通計時信號係耦接到自適應滯環控制電路511的一個輸入端。Figure 6 is an embodiment of a turn-on timing circuit 510 of the present invention. The turn-on timing circuit 510 is coupled to the input voltage V in , the mirror current source 601 charges the capacitor 602 with a current I, and the voltage across the capacitor 602 is coupled to the input of the comparator 603 by setting the mirror current source 601 and the capacitor. 602 can determine the turn-on timing signal. The reference voltage signal V REF is coupled to the other input of the comparator 603. Compared with the voltage on the capacitor 602, the comparator 603 outputs a turn-on timing signal according to the comparison result, and the turn-on timing signal is coupled to the adaptive hysteresis control. An input of circuit 511.

圖7為本發明中自適應控制電路511的一個實施例。電晶體701的閘極係耦接到電晶體101的閘極驅動信號HS,電晶體702的閘極係耦接到導通計時信號。當HS信號為高位準時,電晶體701被導通,電流源704經由電晶體701而以電流I1給電容器703放電;當導通計時信號為高位準時,電晶體702被導通,電流源705經由電晶體702而以電流I2給電容器703充電。參考電壓信號VL 為下限閥值電壓,與一個滯環電壓相加,例如圖7中所示的 15mV,但具體應用中可以根據實際情況而調整,將求和後的電壓與電容器703上的電壓VC 相加,獲得到的電壓為上限閥值電壓VH ,VH =VL +15mV+VC (可以經由加法器電路來予以實現)。圖8為圖7中上限閥值電壓和下限閥值電壓之關係的示意圖,下限閥值電壓VL 是固定的,滯環電壓提供穩定操作時上限閥值電壓VH 與下限閥值電壓VL 之間的差值,而這個差值又與電容器703上的電壓VC 相疊加,這樣上限閥值電壓VH 會根據實際操作狀況而進行調整,以實現自適應控制。例如I1=I2的情況,電晶體701的導通時間為Ton-HS ,電晶體702的導通時間為Ton-COT ,如果Ton-HS =Ton-COT ,電容器703上的電壓VC =0,VH =VL +15mV;如果Ton-HS <Ton-COT ,電容器703上的電壓VC >0,VH >VL +15mV,電晶體101的導通時間Ton-HS 會變大,以達到更高的上限閥值VH ;如果Ton-HS >Ton-COT ,電容器703上的電壓VC <0,VH <VL +15mV,電晶體101的導通時間Ton-HS 會變小,因為上限閥值電壓VH 變小了。自適應控制電路會根據開關變換器實際操作情況而對上限閥值電壓進行調節,確保切換頻率在很小的範圍內變化。並且自適應控制電路輸出上限閥值電壓和下限閥值電壓,能夠確保開關變換器在最惡劣情況下的暫態響應速度。Figure 7 is an embodiment of an adaptive control circuit 511 in the present invention. The gate of the transistor 701 is coupled to the gate drive signal HS of the transistor 101, and the gate of the transistor 702 is coupled to the turn-on timing signal. When the HS signal is high, the transistor 701 is turned on, the current source 704 discharges the capacitor 703 via the transistor 701 with the current I1; when the turn-on timing signal is high, the transistor 702 is turned on, and the current source 705 is passed through the transistor 702. The capacitor 703 is charged with a current I2. The reference voltage signal V L is a lower threshold voltage and is added to a hysteresis voltage, such as 15 mV as shown in FIG. 7, but in a specific application, it can be adjusted according to actual conditions, and the summed voltage and the capacitor 703 are The voltage V C is added and the obtained voltage is the upper threshold voltage V H , V H = V L +15 mV + V C (which can be implemented via an adder circuit). 8 is a schematic diagram showing the relationship between the upper limit threshold voltage and the lower limit threshold voltage in FIG. 7. The lower limit threshold voltage V L is fixed, and the hysteresis voltage provides the upper limit threshold voltage V H and the lower limit threshold voltage V L during stable operation. The difference between this difference and the voltage V C on the capacitor 703 is superimposed, so that the upper threshold voltage V H is adjusted according to the actual operating conditions to achieve adaptive control. For example, in the case of I1=I2, the on- time of the transistor 701 is Ton-HS , the on- time of the transistor 702 is Ton-COT , and if Ton-HS =T on-COT , the voltage on the capacitor 703 is V C = 0, V H = V L + 15 mV; if T on - HS < T on - COT , the voltage V C of the capacitor 703 is > 0, V H > V L + 15 mV, and the on- time of the transistor 101 T on-HS It becomes larger to reach a higher upper limit threshold V H ; if Ton-HS >T on-COT , the voltage V C <0, V H <V L +15 mV on the capacitor 703, the on- time T of the transistor 101 The on-HS will become smaller because the upper threshold voltage V H becomes smaller. The adaptive control circuit adjusts the upper threshold voltage according to the actual operation of the switching converter to ensure that the switching frequency varies within a small range. And the adaptive control circuit outputs the upper threshold voltage and the lower threshold voltage to ensure the transient response speed of the switching converter under the worst conditions.

圖9為根據本發明進行模擬而獲得到的波形圖。下限閥值電壓VL 為固定值800mV,輸入電壓Vin 在5V到16V之間變化,上限閥值VH 也相應的在810mV到815mV之間變化,上限閥值會根據實際操作情況而進行自適應調 節。Figure 9 is a waveform diagram obtained by simulation in accordance with the present invention. The lower limit threshold voltage V L is a fixed value of 800 mV, the input voltage V in is varied between 5 V and 16 V, and the upper limit threshold V H is also varied between 810 mV and 815 mV, and the upper limit threshold is self-operating according to actual operation conditions. Adapt to adjustment.

圖10為根據本發明自適應控制電路511的另一個實施例。參考電壓信號VH 為上限閥值電壓,VH 是一個固定的電壓,與一個滯環電壓相減,例如圖10中所示的15mV,但具體應用中可以根據實際情況而調整,將求差後的電壓與電容器703上的電壓VC 相減,獲得到的電壓為下限閥值電壓VL ,VL =VH -15mV-VC (可以經由減法器電路來予以實現)。Figure 10 is another embodiment of an adaptive control circuit 511 in accordance with the present invention. The reference voltage signal V H is the upper limit threshold voltage, and V H is a fixed voltage, which is subtracted from a hysteresis voltage, such as 15 mV as shown in FIG. 10, but can be adjusted according to actual conditions in a specific application, and the difference will be The post voltage is subtracted from the voltage V C across capacitor 703, and the resulting voltage is the lower threshold voltage V L , V L = V H -15 mV - V C (which can be implemented via a subtractor circuit).

以上對本發明的示出示例的描述,包括摘要中所描述的,並不希望是毫無遺漏的或者是對所揭示的精確形式的限制。儘管出於說明性目的而在此描述了本發明的特定實施例和示例,但是在不偏離本發明的更寬的精神和範圍的情況下,各種等同修改是可以的。實際上,應當理解,特定電壓、電流、頻率、功率範圍值、時間等被提供用於說明目的,並且其他值也可以用在根據本發明教導的其他實施例和示例中。The above description of the illustrated examples of the invention, including the description of the present invention, is not intended to be exhaustive or limited to the precise forms disclosed. While the invention has been described with respect to the specific embodiments and examples of the present invention, various equivalent modifications are possible without departing from the spirit and scope of the invention. In fact, it should be understood that particular voltages, currents, frequencies, power range values, times, etc. are provided for illustrative purposes, and other values may be used in other embodiments and examples in accordance with the teachings of the present invention.

根據以上詳細描述,可以對本發明的示例進行這些修改。以下申請專利範圍中所使用的術語不應該被理解為將本發明限制於說明書和申請專利範圍中所揭示的特定實施例。而是,範圍完全由以下申請專利範圍所確定,申請專利範圍要根據已制定的申請專利範圍解釋原則來加以理解。因此,本說明書和圖式被視為說明性的而非限制性的。These modifications can be made to the examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed as limiting the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope is fully determined by the scope of the following patent application, and the scope of the patent application is to be understood in accordance with the principles of interpretation of the scope of the patent application that has been established. Accordingly, the specification and drawings are to be regarded as

101‧‧‧電晶體101‧‧‧Optoelectronics

102‧‧‧電晶體102‧‧‧Optoelectronics

103‧‧‧電感器103‧‧‧Inductors

104‧‧‧電容器104‧‧‧ capacitor

105‧‧‧負載電阻器105‧‧‧Load resistors

106‧‧‧電阻器106‧‧‧Resistors

107‧‧‧電阻器107‧‧‧Resistors

108‧‧‧滯環比較器108‧‧‧ Hysteresis comparator

109‧‧‧驅動電路109‧‧‧Drive circuit

308‧‧‧比較器308‧‧‧ comparator

310‧‧‧導通計時電路310‧‧‧ Turn-on timing circuit

508‧‧‧滯環比較器508‧‧‧ Hysteresis comparator

510‧‧‧導通計時電路510‧‧‧ Turn-on timing circuit

511‧‧‧自適應滯環控制電路511‧‧‧Adaptive hysteresis control circuit

601‧‧‧鏡像電流源601‧‧‧Mirror current source

602‧‧‧電容器602‧‧‧ capacitor

603‧‧‧比較器603‧‧‧ comparator

701‧‧‧電晶體701‧‧‧Optoelectronics

702‧‧‧電晶體702‧‧‧Optoelectronics

703‧‧‧電容器703‧‧‧ capacitor

704‧‧‧電流源704‧‧‧current source

705‧‧‧電流源705‧‧‧current source

FB‧‧‧電壓取樣信號FB‧‧‧ voltage sampling signal

HS‧‧‧驅動控制信號HS‧‧‧ drive control signal

圖1是經由滯環控制電路來控制DC-DC同步降壓式變換器的示意圖。1 is a schematic diagram of controlling a DC-DC synchronous buck converter via a hysteresis control circuit.

圖2是圖1中電晶體閘極驅動信號和電壓取樣信號波形。2 is a waveform diagram of a transistor gate drive signal and a voltage sample signal of FIG. 1.

圖3是經由恒定導通時間控制電路來控制DC-DC同步降壓式變換器的示意圖。3 is a schematic diagram of controlling a DC-DC synchronous buck converter via a constant on-time control circuit.

圖4是圖3中電晶體閘極驅動信號和電壓取樣信號波形。4 is a waveform diagram of a transistor gate drive signal and a voltage sample signal of FIG.

圖5是本發明經由自適應控制電路控制DC-DC同步降壓式變換器的一個實施例的示意圖。5 is a schematic diagram of one embodiment of the present invention for controlling a DC-DC synchronous buck converter via an adaptive control circuit.

圖6是圖5中導通計時電路一個實施例的示意圖。Figure 6 is a schematic illustration of one embodiment of the turn-on timing circuit of Figure 5.

圖7是圖5中自適應控制電路一個實施例的示意圖。Figure 7 is a schematic illustration of one embodiment of the adaptive control circuit of Figure 5.

圖8是圖7中上限電壓閥值和下限電壓閥值的示意圖。Figure 8 is a schematic illustration of the upper and lower voltage thresholds of Figure 7.

圖9是圖5中電路模擬結果的示意圖。Figure 9 is a schematic illustration of the circuit simulation results of Figure 5.

圖10是圖5中自適應控制電路另一個實施例的示意圖。Figure 10 is a schematic illustration of another embodiment of the adaptive control circuit of Figure 5.

101‧‧‧電晶體101‧‧‧Optoelectronics

102‧‧‧電晶體102‧‧‧Optoelectronics

103‧‧‧電感器103‧‧‧Inductors

104‧‧‧電容器104‧‧‧ capacitor

105‧‧‧負載電阻器105‧‧‧Load resistors

106‧‧‧電阻器106‧‧‧Resistors

107‧‧‧電阻器107‧‧‧Resistors

109‧‧‧驅動電路109‧‧‧Drive circuit

508‧‧‧滯環比較器508‧‧‧ Hysteresis comparator

510‧‧‧導通計時電路510‧‧‧ Turn-on timing circuit

511‧‧‧自適應滯環控制電路511‧‧‧Adaptive hysteresis control circuit

Claims (23)

一種開關變換器電路,包括:輸入端子,以接收輸入電壓;輸出端子,係耦接到負載電路,而為該負載電路提供輸出電壓;反饋電路,係與該輸出電壓相耦接,以提供反饋信號給驅動電路;驅動電路,係與該反饋電路相耦接,以輸出驅動信號;以及開關電路,係基於該驅動電路輸出的該驅動信號而切換電晶體導通或關斷,其中,該反請電路包括電壓取樣電路、導通計時電路和自適應模組,該電壓取樣電路對該輸出電壓進行取樣,以產生電壓取樣信號,該導通計時電路輸出導通計時信號,該自適應模組接收該驅動信號和該導通計時信號,以輸出上限閥值電壓和下限閥值電壓。 A switching converter circuit includes: an input terminal for receiving an input voltage; an output terminal coupled to the load circuit to provide an output voltage for the load circuit; and a feedback circuit coupled to the output voltage to provide feedback a signal is applied to the driving circuit; the driving circuit is coupled to the feedback circuit to output a driving signal; and the switching circuit switches the transistor to be turned on or off based on the driving signal output by the driving circuit, wherein the reverse The circuit includes a voltage sampling circuit, a turn-on timing circuit and an adaptive module. The voltage sampling circuit samples the output voltage to generate a voltage sampling signal, and the conduction timing circuit outputs a conduction timing signal, and the adaptive module receives the driving signal. And the turn-on timing signal to output an upper threshold voltage and a lower threshold voltage. 如申請專利範圍第1項所述之開關變換器電路,其中,該反饋電路還包括比較器電路,該比較器電路將該電壓取樣信號與該上限閥值電壓和該下限閥值電壓相比較,以產生該反饋信號。 The switching converter circuit of claim 1, wherein the feedback circuit further comprises a comparator circuit, the comparator circuit comparing the voltage sampling signal with the upper threshold voltage and the lower threshold voltage, To generate the feedback signal. 如申請專利範圍第1項所述之開關變換器電路,其中,該導通計時電路係耦合到該輸入電壓,包括一個由至少一個鏡像電流源和一個第一電容器所耦接而成的充電電路,和一個比較電路;該第一電容器的一端係耦接到該比 較電路,與一個參考電壓相比較,以產生該導通計時信號。 The switching converter circuit of claim 1, wherein the on-time circuit is coupled to the input voltage, and includes a charging circuit coupled by at least one mirror current source and a first capacitor. And a comparison circuit; one end of the first capacitor is coupled to the ratio The comparator circuit is compared to a reference voltage to generate the turn-on timing signal. 如申請專利範圍第3項所述之開關變換器電路,其中,該自適應模組包括一個由至少一個第一電晶體和一個第一電流源所耦接而成的放電電路,和一個由至少一個第二電晶體和一個第二電流源所耦接而成的充電電路。 The switching converter circuit of claim 3, wherein the adaptive module comprises a discharge circuit coupled by at least one first transistor and a first current source, and a A charging circuit coupled by a second transistor and a second current source. 如申請專利範圍第4項所述之開關變換器電路,其中,該第一電晶體的閘極係耦接到該驅動電路輸出的驅動信號,該第二電晶體的閘極係耦接到該導通計時信號。 The switching converter circuit of claim 4, wherein a gate of the first transistor is coupled to a driving signal output by the driving circuit, and a gate of the second transistor is coupled to the gate Turn on the timing signal. 如申請專利範圍第5項所述之開關變換器電路,其中,該自適應模組還包括一個與放電電路、充電電路相耦接的第二電容器,當該第一電晶體被導通時,該第一電流源給該第二電容器放電;當該第二電晶體被導通時,該第二電流源給該第二電容器充電。 The switching converter circuit of claim 5, wherein the adaptive module further includes a second capacitor coupled to the discharge circuit and the charging circuit, when the first transistor is turned on, A first current source discharges the second capacitor; and when the second transistor is turned on, the second current source charges the second capacitor. 如申請專利範圍第6項所述之開關變換器電路,其中,該自適應模組還包括參考電壓源,以輸出該下限閥值電壓;該參考電壓源與一個滯環電壓源相耦接後,與該第二電容器相耦接;該參考電壓源、該滯環電壓源和該第二電容器三者的電壓相加後,輸出該上限閥值電壓。 The switching converter circuit of claim 6, wherein the adaptive module further includes a reference voltage source to output the lower threshold voltage; the reference voltage source is coupled to a hysteresis voltage source And coupling with the second capacitor; after the voltages of the reference voltage source, the hysteresis voltage source and the second capacitor are added, the upper threshold voltage is output. 如申請專利範圍第6項所述之開關變換器電路,其中,該自適應模組還包括參考電壓源,以輸出該上限閥值電壓;該參考電壓源與一個負的滯環電壓源相耦接後,與該第二電容器相耦接;該參考電壓源電壓減去滯環電壓源電壓、該第二電容器電壓後,輸出該下限閥值電壓。 The switching converter circuit of claim 6, wherein the adaptive module further includes a reference voltage source to output the upper threshold voltage; the reference voltage source is coupled to a negative hysteresis voltage source After being connected, coupled to the second capacitor; after the reference voltage source voltage subtracts the hysteresis voltage source voltage and the second capacitor voltage, the lower threshold voltage is output. 如申請專利範圍第1項所述之開關變換器電路,其中,該開關電路包括第一電晶體和第二電晶體,其中,該第一電晶體的源極與該第二電晶體的汲極相耦接以作為輸出端,再經濾波電路而與輸出端子相耦接。 The switching converter circuit of claim 1, wherein the switching circuit comprises a first transistor and a second transistor, wherein a source of the first transistor and a drain of the second transistor The phase is coupled to serve as an output terminal, and is coupled to the output terminal via a filter circuit. 如申請專利範圍第9項所述之開關變換器電路,其中,該驅動信號為兩路互補的脈衝信號,係分別耦接到該第一電晶體、該第二電晶體的閘極。 The switching converter circuit of claim 9, wherein the driving signal is two complementary pulse signals coupled to the first transistor and the gate of the second transistor, respectively. 一種電壓變換的方法,其特徵在於,包括利用驅動信號來控制電晶體導通或關斷,以控制輸出電壓;基於導通計時信號和控制該電晶體的驅動信號,自適應地輸出上限閥值電壓或下限閥值電壓;基於該輸出電壓的取樣信號與該上限閥值電壓、該下限閥值電壓的比較,以輸出比較信號;以及基於該比較信號以輸出驅動信號。 A voltage conversion method, comprising: controlling a transistor to be turned on or off by using a driving signal to control an output voltage; adaptively outputting an upper threshold voltage or based on a turn-on timing signal and a driving signal for controlling the transistor a lower threshold voltage; a comparison of the sampling signal based on the output voltage with the upper threshold voltage and the lower threshold voltage to output a comparison signal; and based on the comparison signal to output a driving signal. 如申請專利範圍第11項所述的方法,其中,該輸出電壓的取樣信號係經由耦接在該輸出電壓的電壓取樣電路來予以實現。 The method of claim 11, wherein the sampling signal of the output voltage is implemented via a voltage sampling circuit coupled to the output voltage. 如申請專利範圍第11項所述的方法,其中,該導通計時信號係經由下述導通計時電路來予以實現:包括一個由至少一個鏡像電流源和一個第一電容器所耦接而成的充電電路,和一個比較電路;該第一電容器的一端係耦接到該比較電路,與一個參考電壓相比較,以產生該導通計時信號。 The method of claim 11, wherein the turn-on timing signal is implemented by a turn-on timing circuit comprising: a charging circuit coupled by at least one mirror current source and a first capacitor And a comparison circuit; one end of the first capacitor is coupled to the comparison circuit and compared with a reference voltage to generate the on-time signal. 如申請專利範圍第11項所述的方法,其中,該自適應地輸出上限閥值電壓係經由下述電路來予以實現:第二電容器與放電電路、充電電路相耦接,該放電電路係藉由驅動信號來控制通斷,該充電電路係藉由導通計時信號來控制通斷,該第二電容器的電壓端疊加參考電壓源、滯環電壓源後輸出該上限閥值電壓,其中,該參考電壓源的電壓作為該下限閥值電壓。 The method of claim 11, wherein the adaptively outputting the upper threshold voltage is implemented by: a second capacitor coupled to the discharge circuit and the charging circuit, the discharge circuit borrowing The on/off is controlled by a driving signal, and the charging circuit controls on-off by turning on a timing signal, and the voltage terminal of the second capacitor superimposes the reference voltage source and the hysteresis voltage source, and outputs the upper threshold voltage, wherein the reference The voltage of the voltage source is used as the lower threshold voltage. 如申請專利範圍第14項所述的方法,其中,該放電電路係由第一電流源和第一電晶體所耦接而成,該第一電晶體的閘極接收驅動信號。 The method of claim 14, wherein the discharge circuit is coupled by the first current source and the first transistor, and the gate of the first transistor receives the drive signal. 如申請專利範圍第14或15項所述的方法,其中,該充電電路係由第二電流源和第二電晶體所耦接而成,該第二電晶體的閘極接收導通計時信號。 The method of claim 14 or 15, wherein the charging circuit is coupled by the second current source and the second transistor, and the gate of the second transistor receives the conduction timing signal. 如申請專利範圍第16項所述的方法,其中,當該驅動信號為高位準時,該第一電晶體被導通,該第一電流源經由該第一電晶體而給該第二電容器放電。 The method of claim 16, wherein the first transistor is turned on when the driving signal is at a high level, and the first current source discharges the second capacitor via the first transistor. 如申請專利範圍第16項所述的方法,其中,當該導通計時信號為高位準時,該第二電晶體被導通,該第二電流源經由該第二電晶體而給第二該電容器充電。 The method of claim 16, wherein the second transistor is turned on when the turn-on timing signal is at a high level, and the second current source charges the second capacitor via the second transistor. 如申請專利範圍第11項所述的方法,其中,該自適應地輸出下限閥值電壓係經由下述電路來予以實現:第二電容器與放電電路、充電電路相耦接,該放電電路係藉由驅動信號來控制通斷,該充電電路係藉由導通計時信號來控制通斷,參考電壓源減去第二電容器的電壓、 滯環電壓源的電壓後輸出該下限閥值電壓,其中,該參考電壓源的電壓作為該上限閥值電壓。 The method of claim 11, wherein the adaptively outputting the lower threshold voltage is implemented by: a second capacitor coupled to the discharge circuit and the charging circuit, the discharge circuit borrowing The on/off is controlled by a driving signal that is controlled to be turned on and off by turning on the timing signal, and the reference voltage source is subtracted from the voltage of the second capacitor, The lower threshold voltage is output after the voltage of the hysteresis voltage source, and the voltage of the reference voltage source is used as the upper threshold voltage. 如申請專利範圍第19項所述的方法,其中,該放電電路係由第一電流源和第一電晶體所耦接而成,該第一電晶體的閘極接收驅動信號。 The method of claim 19, wherein the discharge circuit is coupled by the first current source and the first transistor, and the gate of the first transistor receives the driving signal. 如申請專利範圍第19或20項所述的方法,其中,該充電電路係由第二電流源和第二電晶體所耦接而成,該第二電晶體的閘極接收導通計時信號。 The method of claim 19 or 20, wherein the charging circuit is coupled by the second current source and the second transistor, and the gate of the second transistor receives the conduction timing signal. 如申請專利範圍第21項所述的方法,其中,當驅動信號為高位準時,該第一電晶體被導通,該第一電流源經由該第一電晶體而給該第二電容器放電。 The method of claim 21, wherein the first transistor is turned on when the driving signal is at a high level, and the first current source discharges the second capacitor via the first transistor. 如申請專利範圍第21項所述的方法,其中,當該導通計時信號為高位準時,該第二電晶體被導通,該第二電流源經由該第二電晶體而給該第二電容器充電。 The method of claim 21, wherein the second transistor is turned on when the turn-on timing signal is at a high level, and the second current source charges the second capacitor via the second transistor.
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