TWI427594B - Power supply, control method and electronic system utilizing the same - Google Patents

Description

Power supply device, control method and electronic system

The present invention relates to a power supply device, particularly to a power supply device in a display panel.

In general, flat panel displays can be classified into non-self-illuminating displays as well as self-illuminating displays. A liquid crystal display (LCD) is a type of non-self-luminous display. The self-luminous display includes a plasma display panel (PDP), a field emission display (FED), an electroluminescent (EL) display, and an organic light emitting diode display (organic light emitting diode display; OLED).

Self-illuminating displays are often used because of their advantages of thin size, light weight, high luminous efficiency, and low driving voltage. However, as the display panel of the self-luminous display is larger, the length of the internal power supply line is longer. Since the power line has an equivalent impedance, the voltage across the power line is different.

The invention provides a power supply device coupled to a power line and a reference line. The power cord has a first and second node. The reference line has a third and fourth node. The first node is coupled to one of the first pixel units of the first pixel unit. The second node is coupled to one of the second pixel units of the second pixel unit. The first capacitor of the first pixel unit is coupled between the gate of the first driving transistor and the third node. The second capacitor of the second pixel unit is coupled between the gate of the second driving transistor and the fourth node. The power supply device includes a processing unit and a first voltage generating unit. The processing unit captures the voltage of one of the first and second nodes, and generates a control signal according to the captured result. The first voltage generating unit provides a first reference voltage or a second reference voltage to the reference line according to the control signal.

The invention further provides an electronic system comprising a voltage conversion device and a display panel. The voltage conversion device converts an input voltage into an output voltage. The display panel receives the output voltage and includes a power line, a reference line, a first pixel unit, a second pixel unit, a processing unit, and a first voltage generating unit. The power line has a first node and a second node. The reference line has a third node and a fourth node. The first pixel unit includes a first driving transistor and a first capacitor. The first driving transistor is coupled to the first node. The first capacitor is coupled between the gate of the first driving transistor and the third node. The second pixel unit includes a second driving transistor and a second capacitor. The second driving transistor is coupled to the second node. The second capacitor is coupled between the gate of the second driving transistor and the fourth node. The processing unit captures the voltage of one of the first and second nodes, and generates a control signal according to the captured result. The first voltage generating unit provides a first or second reference voltage to the reference line according to the control signal.

The invention further provides a control method suitable for a first and second pixel unit. The first pixel unit has a first driving transistor and a first capacitor. The second pixel unit has a second driving transistor and a second capacitor. The first driving transistor is coupled to a first node of a power line. The second driving transistor is coupled to one of the second nodes of the power line. The first capacitor is coupled between the third node of one of the reference lines and the gate of the first driving transistor. The second capacitor is coupled between the fourth node of one of the reference lines and the gate of the second driving transistor. The control method of the present invention includes providing an operating voltage to the power line during a first period, and extracting a voltage of one of the first and second nodes for generating a first reference voltage; Providing a scan signal and a data signal to the first or second pixel unit and providing a first reference voltage to the reference line; during a second period, stopping providing the scan signal, continuing to provide the first reference voltage; During a third period, a second reference voltage is supplied to the reference line.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

Figure 1A is a schematic view of an electronic system of the present invention. As shown, the electronic system 100 includes a voltage conversion device 110 and a display panel 120. The voltage conversion device 110 converts the input voltage V _IN into an output voltage V _OUT . The display panel 120 receives the output voltage V _OUT and presents an image. In the present embodiment, the output voltage V _OUT is a direct current (DC) voltage.

The invention does not limit the type of input voltage V _IN . In other possible embodiments, the input voltage V _IN is an alternating current (AC) voltage or a direct current voltage. In addition, the electronic system 100 can be a personal digital assistant (PDA), a cellular phone, a digital camera, a television, a global positioning system (GPS), a car display, an aeronautical display, a digital photo frame, and a note. A computer or a desktop computer.

The display panel 120 includes a power supply line (power line) 121, the reference line 122, the pixel unit P _1, P ₂ and power supply means 123. The power line 121 has nodes N ₁ and N ₂ . In the present embodiment, the power line 121 has a start terminal NPs that receives the operating voltage PVDD provided by the power supply device 123. As shown, the distance between the node N ₂ and the starting end NPs is greater than the distance between the node N ₁ and the starting end NPs.

Reference line 122 has nodes N ₃ and N ₄ . In the present embodiment, the reference line 122 has a start terminal NRs that receives the reference voltage Vref or GND provided by the power supply device 123. As shown, the distance between the node N ₄ and the starting end NRs is smaller than the distance between the node N ₃ and the starting end NR _s . Additionally, reference line 122 has an end that can receive a ground voltage. In this embodiment, the ground voltage is equal to the reference voltage GND.

The pixel unit P ₁ includes a driving transistor MD ₁ and a capacitor C ₁ . The driving transistor MD _{1 is} coupled to the node N ₁ . The capacitor C _{1 is} coupled between the gate of the driving transistor MD ₁ and the node N ₃ . The pixel unit P ₂ includes a driving transistor MD ₂ and a capacitor C ₂ . The driving transistor MD _{2 is} coupled to the node N ₂ . The capacitor C _{2 is} coupled between the gate of the driving transistor MD ₂ and the node N ₄ . In the present embodiment, the driving transistors MD ₁ and MD ₂ are all P-type transistors, but are not intended to limit the present invention.

The power supply device 123 takes the voltage of one of the nodes N ₁ and N ₂ and supplies the reference voltage Vref or GND to the reference line 122 according to the result of the extraction. In the present embodiment, the power supply device 123 draws the voltage of the node N ₂ , but is not intended to limit the present invention. In other embodiments, the power supply voltage of the node N ₁ 123 may capturing.

Fig. 1B shows the arrangement of the complex pixel units P ₁₁ to P _mn and the connection relationship between the pixel units P ₁₁ to P _mn and the power supply line 121 and the reference lines RL ₁ to RL _n . In the present embodiment, the pixel units P ₁₁ to P _mn are arranged in an array manner, but are not intended to limit the present invention.

In FIG. 1B, the display panel 120 further includes a driving device 124. The drive device 124 includes a gate driver 125 and a source driver 126. The gate driver 125 supplies a scan signal to the gate lines GL ₁ to GL _n . The source driver 126 provides a data signal to the data lines DL ₁ ~ DL _m . In a possible embodiment, all or part of the power supply device 123 can be integrated with the driving device 124 into an integrated circuit (IC).

Further, in the present embodiment, the power supply device 123 generates the control signal S _C and the reference signal Vref to the gate driver 125 only in accordance with the voltage of the node NP ₁₁ of the power source line 121. The gate driver 125 selectively outputs the reference signal Vref or GND to the reference lines RL ₁ to RL _n according to the control signal S _C . In other embodiments, the power supply device 123 can generate different reference signals to the gate driver 125 according to the voltages of different nodes on the power line 121. The gate driver 125 then selectively outputs the corresponding reference signal to the reference lines RL ₁ -RL _n .

For example, assume that the pixel unit P ₁₁ ~P _{m1 of the} first column (row, horizontal direction) is coupled to the reference line RL ₁ , and the pixel units P ₁₂ -P _{m2 of the} second column are coupled to the reference line RL ₂ . In this example, the power supply unit 123 can generate different reference voltages to the gate driver 125 according to the voltages of different nodes (such as NP ₁₁ and NP ₁₂ ). The gate driver 125 then selectively pairs the corresponding reference lines RL ₁ and RL ₂ .

Figure 2A is a possible embodiment of a pixel unit of the present invention. Because the pixel units P ₁₁ ~ P _mn are the same structure, so only the pixel unit P ₁₁ as an example, circuit configuration of the pixel unit P _11. As shown, the pixel unit P ₁₁ includes a switching transistor MS ₁₁ , a capacitor C ₁₁ , a driving transistor MD _{11 ,} and a light-emitting element 200.

In this embodiment, the switching transistor MS ₁₁ is an N-type transistor, and the gate is coupled to the gate line GL ₁ for receiving the scan signal, and the drain is coupled to the data line DL ₁ for receiving data. The signal is coupled to the gate of the driving transistor MD ₁₁ . The capacitor C _{11 is} coupled between the node NR ₁₁ and the gate of the driving transistor MD ₁₁ .

The driving transistor MD ₁₁ can be a P-type transistor, the source of which is coupled to the node NP ₁₁ and the drain of which is coupled to the light-emitting element 200. The other end of the light emitting element 200 receives the voltage PVEE. The light emitting device 200 can be a light emitting diode (LED) or an organic light emitting diode (OLED), but is not intended to limit the present invention. The invention does not limit the kind of the light-emitting element 200.

Please with FIG. 1B, in a first period, a gate driver 125 supplies a scan signal to the gate line GL ₁ ~ GL _n, the source driver 126 and also provide the data signals to the data lines DL ₁ ~ DL _m. At this time, the power supply device 123 supplies the operating voltage PVDD to the power supply line 121.

During a second period, the power supply device 123 draws the voltage of the node NP ₁₁ and generates a reference voltage Vref and a control signal S _C according to the result of the extraction. The gate driver 125 transmits the reference voltage Vref to the pixel units P ₁₁ to P _m1 through the reference line RL ₁ according to the control signal S _C . Therefore, the voltage of the node NR ₁₁ is the reference voltage Vref. During this period, since the scanning signal on the gate line GL ₁ turns on the switching transistor MS ₁₁ , the voltage of the node Nb is equal to the data signal V _DATA on the data line DL ₁ .

During a third period, the scan signal on the gate line GL ₁ does not conduct the switching transistor MS ₁₁ . Therefore, the voltage of the node Nb is still equal to the data signal V _DATA (assumed to be 3V). At this time, the voltage of the node NR ₁₁ is still equal to the reference voltage Vref (assumed to be 1 V).

During a fourth period, the gate driver 125 causes the reference line RL _{1 to} transfer the reference voltage GND to the pixel units P ₁₁ to P _{m1 in} accordance with the control signal S _C . Therefore, the voltage of the node NR ₁₁ will be changed from the reference voltage Vref to the reference voltage GND. Due to the coupling effect of the capacitor C _11, so the voltage of the node Nb will fall Vref. Therefore, the voltage of the node Nb is V _Nb = V _{DATA -} Vref.

Since the voltage drop caused by the equivalent impedance of the power line 121 may affect the voltage across the source and the gate of the driving transistor MD ₁₁ , the voltage levels of the reference lines RL ₁ to RL _n may be controlled. drop compensator 121 because the equivalent impedance of the power line caused by, so to restore the voltage across the source and between the gate ₁₁ of the driving transistor MD.

For example, during the first period, the operating voltage PVDD is equal to 5V, and the data signal V _DATA on the data line DL ₁ is equal to 3V. Therefore, the voltage across the source and the gate of the driving transistor MD ₁₁ (V _G - V _S ) is equal to 2V (5V - 3V).

Assume that the equivalent resistance of the power line 121 causes a voltage drop of 1V. Therefore, in the second period, the voltage of the node NP ₁₁ (i.e., the source voltage of the driving transistor MD ₁₁ ) is 4V (5V - 1V). The power supply device 123 knows that the equivalent resistance of the power supply line 121 causes a voltage drop of 1 V in accordance with the voltage of the node NP ₁₁ , so the reference voltage Vref is set to 1V. Therefore, in the second period, the voltage of the node NR ₁₁ is 1V. Since the voltage of the node Nb is still 3V, the voltage across the source and the gate of the driving transistor MD ₁₁ will be changed from the original 2V to 1V (4V - 3V).

In the third period, since the voltage of the node NR ₁₁ is still 1 V, and the voltage of the node Nb is still 3 V, the voltage across the source and the gate of the driving transistor MD ₁₁ is maintained at 1 V.

In the fourth period, the voltage of the node Nb is V _Nb = V _{DATA -} Vref (i.e., 3V - 1V). Since the voltage of the node NP ₁₁ is 4V and the voltage of the node Nb is V _Nb = 2V, the voltage across the source and the gate of the driving transistor MD ₁₁ is restored from 1V to 2V.

Figure 2B is another possible embodiment of the pixel unit of the present invention. Fig. 2B is similar to Fig. 2A except that the control transistor MC _{11 is added to} Fig. 2B. In the present embodiment, the control transistor MC ₁₁ is an N-type transistor, the gate of which receives the illuminating signal S _EM , the drain of which is coupled to the drain of the driving transistor MD ₁₁ , and the source of which is coupled to the illuminating element 200 . .

The invention does not limit the internal structure of the pixel unit. As long as the pixel unit has a driving transistor and a capacitor, it can be used as the pixel unit of the present invention, wherein the driving electro-crystal system in the pixel unit is coupled to a power line, and the pixel unit is The capacitor is coupled between a reference line and a gate of the driving transistor.

Figure 3 is a diagram showing one possible embodiment of the power supply unit 123 of the present invention. As shown, the power supply device 123 includes a processing unit 310 and a voltage generating unit 330. The processing unit 310 captures the voltage of any node on the power line 121, and generates a control signal S _C according to the captured result. In the present embodiment, the processing unit 310 _draws the voltage V _{NP11 of the} node NP ₁₁ . In addition, the distance between the node NP ₁₁ to the start end NP _S of the power line 121 is greater than the distance between the node NP ₁₂ and the start end NP _{S of the} power line 121.

In the present embodiment, the processing unit 310 includes a subtractor 311 and a comparator 312. The subtracter 311 calculates the difference between the operating voltage PVDD and the drawn voltage (i.e., the voltage V _{NP11 of the} node NP ₁₁ ). In the present embodiment, the difference calculated by the subtracter 311 is used as the reference voltage Vref.

The comparator 312 generates a control signal S _C based on the difference (Vref) calculated by the subtracter 311 and the reference signal Sref. In this embodiment, when the difference calculated by the subtracter 311 is smaller than the reference signal Sref, the control signal S _C is in a disabled state; when the difference calculated by the subtracter 311 is greater than the reference signal Sref, the control signal S _C is the consistent state.

The voltage generating unit 330 outputs the control signal S _C and the reference voltage Vref to the gate driver 125, wherein the reference voltage Vref is the difference value calculated by the subtracter 311. In a possible embodiment, the reference voltage GND is less than the reference voltage Vref.

In the present embodiment, when the control signal S _C is in an enabled state, the gate driver 125 supplies the reference voltage Vref to the reference lines RL ₁ to RL _n ; when the control signal S _C is in the disabled state, the gate driver 125 provides The reference voltage GND is supplied to the reference lines RL ₁ to RL _n . In a possible embodiment, the voltage generating unit 330 can be integrated into the gate driver 125 shown in FIG. 1B. In this example, the gate driver 125 has a complex voltage generating unit 330 for controlling the levels of the reference lines RL ₁ to RL _n , respectively.

In the present embodiment, the voltage generating unit 330 includes transistors 331 and 332. The transistor 331 can be a P-type transistor. The transistor 332 can be an N-type transistor. When the control signal S _C is in an enabled state, the transistor 331 transmits the reference voltage Vref to the reference lines RL ₁ to RL _n . When the control signal S _C is in the disabled state, the transistor 332 transmits the reference voltage GND to the reference lines RL ₁ to RL _n .

In addition, in the present embodiment, the power supply device 123 further includes a voltage generating unit 350. The voltage generating unit 350 supplies the operating voltage PVDD to the start terminal NP _{S of the} power line 121. In a possible embodiment, the processing unit 310 generates a control signal S _C according to the operating voltage PVDD and the captured voltage (ie, V _NP11 ).

Figure 4 is a possible flow chart of one of the control methods of the present invention. The control method of the present invention is applied to the pixel units P ₁ and P ₂ shown in Fig. 1A. Therefore, a possible flow of one of the control methods of the present invention will be described below with reference to the symbol of Fig. 1A.

First, the operating voltage is supplied to the power supply line PVDD 121, and retrieve one of the voltage of the node N _1, and those ₂ N, to generate the reference voltage Vref (step S410). In a possible embodiment, the reference voltage Vref may be the difference between the operating voltage PVDD and the drawn voltage.

In this embodiment, the voltage of node N ₂ is taken. The distance between the node N ₂ to a power supply device (such as the symbol 123 shown in FIG. 1A) is greater than the distance between the node N ₁ and the power supply device 123. In addition, the operating voltage PVDD may be provided by the power supply device 123.

Next, a scan signal and a data signal are supplied to the first or second pixel unit, and a reference voltage Vref is supplied to the reference line 122 (step S430). Taking the pixel unit P _{1 of} FIG. 1A as an example, at this time, the gate voltage of the driving transistor MD ₁ is approximately equal to the data signal, and the voltage of the node N ₄ is approximately equal to the reference voltage Vref.

Then, the supply of the scan signal is stopped, and the reference voltage Vref is continuously supplied (step S450). At this time, the gate voltage of the driving transistor MD ₁ is still approximately equal to the data signal, and the voltage of the node N ₄ is also approximately equal to the reference voltage Vref.

Finally, the reference voltage GND is supplied to the reference line 122 (step S470). At this time, the voltage of the node N ₄ is approximately equal to the reference voltage GND. In the present embodiment, the reference voltage GND is smaller than the reference voltage Vref. According to the characteristics of the capacitor C ₂ , when the voltage of the node N ₄ drops from the original Vref to GND, the gate voltage of the driving transistor MD ₂ will drop by Vref. Therefore, the voltage drop due to the impedance of the power line 121 can be compensated.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Electronic system

110‧‧‧Voltage conversion device

120‧‧‧ display panel

121‧‧‧Power cord

122‧‧‧ reference line

P ₁ , P ₂ , P ₁₁ ~P _mn ‧‧‧ pixel elements

123‧‧‧Power supply unit

124‧‧‧ drive

125‧‧‧gate driver

126‧‧‧Source Driver

MS ₁₁ ‧‧‧Switching transistor

C ₁₁ ‧‧‧ capacitor

MD ₁₁ ‧‧‧ drive transistor

200‧‧‧Lighting elements

MC ₁₁ ‧‧‧Control transistor

310‧‧‧Processing unit

311‧‧‧Subtractor

312‧‧‧ Comparator

331, 332‧‧‧Optoelectronics

330, 350‧‧‧ voltage generating unit

Figure 1A is a schematic view of an electronic system of the present invention.

Figure 1B is another possible embodiment of the electronic system of the present invention.

Figure 2A is a possible embodiment of a pixel unit of the present invention.

Figure 2B is another possible embodiment of the pixel unit of the present invention.

Fig. 3 is a view showing a possible embodiment of the power supply device of the present invention.

Figure 4 is a possible flow chart of one of the control methods of the present invention.

100. . . electronic system

110. . . Voltage conversion device

120. . . Display panel

121. . . power cable

122. . . reference line

P ₁ , P ₂ . . . Pixel unit

123. . . Power supply unit

Claims (38)

A power supply device is coupled to a power line and a reference line, the power line has a first node and a second node, the reference line has a third node and a fourth node, and the first node is coupled to a first pixel One of the first driving transistor, the second node is coupled to a second driving transistor of the second pixel unit, and the first capacitor of the first pixel unit is coupled to the first driving transistor Between the gate and the third node, a second capacitor of the second pixel unit is coupled between the gate of the second driving transistor and the fourth node, the power supply device includes: a processing unit Obtaining a voltage of one of the first and second nodes, and generating a control signal according to the captured result; and a first voltage generating unit, according to the control signal, providing a first reference voltage or a second The reference voltage is applied to the reference line. The power supply device of claim 1, further comprising a second voltage generating unit for providing an operating voltage to a first starting end of the power line. The power supply device of claim 2, wherein the processing unit captures a voltage of the second node, and a distance between the second node and the first start end is greater than the first node to the first start end the distance between. The power supply device of claim 3, wherein the processing unit generates the control signal according to the operating voltage and the captured voltage. The power supply device of claim 4, wherein the processing unit comprises: a subtractor for calculating a difference between the operating voltage and the captured voltage; and a comparator for generating the control signal based on the difference calculated by the subtractor and a reference signal. The power supply device of claim 5, wherein when the difference calculated by the subtractor is less than the reference signal, the control signal is in a disabled state, and when the difference calculated by the subtractor is greater than the When the signal is referenced, the control signal is in a consistent energy state. The power supply device of claim 6, wherein the first voltage generating unit provides the first reference voltage to the reference line when the control signal is in the enabled state, when the control signal is the forbidden In the energy state, the first voltage generating unit provides the second reference voltage to the reference line. The power supply device of claim 7, wherein the second reference voltage is less than the first reference voltage. The power supply device of claim 8, wherein the first reference voltage is a difference calculated by the subtractor. The power supply device of claim 9, wherein the first voltage generating unit comprises: a first transistor, and when the control signal is in the enabled state, transmitting the first reference voltage to the reference line And a second transistor, when the control signal is in the disabled state, transmitting the second reference voltage to the reference line. The power supply device of claim 10, wherein the first transistor is a P-type transistor, and the second transistor is an N-type transistor. The power supply device of claim 10, wherein the reference line has a second start end and an end end, the second start end is coupled to the first and second transistors, and the end end receives the Second reference voltage. The power supply device of claim 12, wherein the third and fourth nodes are located between the second start end and the end end. The power supply device of claim 1, wherein the first driving transistor is a P-type transistor, the source is coupled to the first node, and the drain is coupled to a light-emitting element. The power supply device of claim 14, wherein the first pixel unit further comprises a switching transistor, the switching transistor is an N-type transistor, and the gate receives a scan signal and has a drain Receiving a data signal, the source of which is coupled to the gate of the first driving transistor. An electronic system comprising: a voltage conversion device for converting an input voltage into an output voltage; and a display panel receiving the output voltage, and comprising: a power line having a first node and a second node a reference line having a third node and a fourth node; a first pixel unit comprising: a first driving transistor coupled to the first node; and a first capacitor coupled to the first a gate of the driving transistor and the third node; a second pixel unit comprising: a second driving transistor coupled to the second node; And a second capacitor coupled between the gate of the second driving transistor and the fourth node; and a processing unit that captures a voltage of one of the first and second nodes and selects As a result, a control signal is generated; and a first voltage generating unit that supplies a first or second reference voltage to the reference line based on the control signal. The electronic system of claim 16, further comprising a second voltage generating unit for providing an operating voltage to a first starting end of the power line. The electronic system of claim 17, wherein the processing unit captures a voltage of the second node, and a distance between the second node and the first start end is greater than a distance from the first node to the first start end. The distance between them. The electronic system of claim 18, wherein the processing unit generates the control signal based on the operating voltage and the drawn voltage. The electronic system of claim 19, wherein the processing unit comprises: a subtractor for calculating a difference between the operating voltage and the captured voltage; and a comparator according to the subtracting The difference calculated by the device and a reference signal are generated to generate the control signal. The electronic system of claim 20, wherein when the difference calculated by the subtractor is less than the reference signal, the control signal is In a disabled state, when the difference calculated by the subtractor is greater than the reference signal, the control signal is in a consistent energy state. The electronic system of claim 21, wherein when the control signal is in the enabled state, the first voltage generating unit provides the first reference voltage to the reference line, and when the control signal is the disabled In the state, the first voltage generating unit provides the second reference voltage to the reference line. The electronic system of claim 22, wherein the second reference voltage is less than the first reference voltage. The electronic system of claim 23, wherein the first reference voltage is a difference calculated by the subtractor. The electronic system of claim 24, wherein the first voltage generating unit comprises: a first transistor, and when the control signal is in the enabled state, transmitting the first reference voltage to the reference line; And a second transistor, when the control signal is in the disabled state, transmitting the second reference voltage to the reference line. The electronic system of claim 25, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor. The electronic system of claim 26, wherein the reference line has a second start end and an end end, the second start end is coupled to the first and second transistors, and the end end receives the first Two reference voltages. The electronic system of claim 27, wherein the third and fourth nodes are located between the second start end and the end end. An electronic system as described in claim 16 wherein the The first driving transistor system is a P-type transistor, the source is coupled to the first node, and the drain is coupled to a light-emitting element. The electronic system of claim 29, wherein the display panel further comprises a driving device for providing a scan signal and a data signal. The electronic system of claim 30, wherein the first voltage generating unit is integrated with the driving device. The electronic system of claim 30, wherein the first pixel unit further comprises a switching transistor, the switching transistor system is an N-type transistor, and the gate receives the scanning signal and has a drain Receiving the data signal, the source thereof is coupled to the gate of the first driving transistor. The electronic system of claim 16, wherein the electronic system is a PDA, a cellular phone, a digital camera, a television, a global positioning system (GPS), and a A car display, an aerial display, a digital photo frame, a laptop or a desktop computer. A control method is applicable to a first and second pixel unit, the first pixel unit having a first driving transistor and a first capacitor, the second pixel unit having a second driving transistor and a a second capacitor, the first driving transistor is coupled to a first node of a power line, the second driving transistor is coupled to a second node of the power line, and the first capacitor is coupled to one of the reference lines Between the third node and the gate of the first driving transistor, the second capacitor is coupled between the fourth node of the reference line and the gate of the second driving transistor. The control method includes: During a first period, an operating voltage is supplied to the power line and captured a voltage of one of the first and second nodes for generating a first reference voltage; and providing a scan signal and a data signal to the first or second pixel unit during a second period, and providing the The first reference voltage is supplied to the reference line; in a second period, the supply of the scan signal is stopped, and the first reference voltage is continuously supplied; and in a third period, a second reference voltage is supplied to the reference line. The control method of claim 34, wherein the operating voltage is provided by a power supply device. The control method of claim 35, wherein in the first period, the voltage of the second node is captured, and the distance between the second node and the power supply device is greater than the first node to the The distance between power supply units. The control method of claim 34, wherein the first reference voltage is a difference between the operating voltage and the drawn voltage. The control method of claim 37, wherein the first reference voltage is greater than the second reference voltage.