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TWI427385B - Liquid crystal display panel - Google Patents

Liquid crystal display panel Download PDF

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Publication number
TWI427385B
TWI427385B TW99143272A TW99143272A TWI427385B TW I427385 B TWI427385 B TW I427385B TW 99143272 A TW99143272 A TW 99143272A TW 99143272 A TW99143272 A TW 99143272A TW I427385 B TWI427385 B TW I427385B
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Taiwan
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groove
liquid crystal
pixel electrodes
crystal display
display panel
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TW99143272A
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Chinese (zh)
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TW201224617A (en
Inventor
Yu Kuan Chang
Chien Cheng Yu
Chun Kai Lai
Yen Hua Hsu
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Au Optronics Corp
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Priority to TW99143272A priority Critical patent/TWI427385B/en
Priority to CN 201110009655 priority patent/CN102162960B/en
Publication of TW201224617A publication Critical patent/TW201224617A/en
Application granted granted Critical
Publication of TWI427385B publication Critical patent/TWI427385B/en

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Description

液晶顯示面板LCD panel

本發明係關於一種液晶顯示面板,尤指一種在平坦層上設置有凹槽以及凹槽四周設置有四個畫素電極之液晶顯示面板,其中在水平方向或垂直方向相鄰之畫素電極之間具有不等的間距。The present invention relates to a liquid crystal display panel, and more particularly to a liquid crystal display panel in which a groove is disposed on a flat layer and four pixel electrodes are disposed around the groove, wherein the pixel electrodes adjacent in the horizontal direction or the vertical direction are There are unequal spacings between them.

近年來,隨著液晶顯示面板生產技術的成熟,應用各類型之液晶顯示面板之產品亦隨著日趨增加。因此,液晶顯示面板的各項特性亦被大眾廣泛討論。在各類型的液晶顯示面板與各項液晶顯示面板之特性中,穿透式液晶顯示面板之耐壓性經常被提出討論。在歷經多次設計改革,穿透式液晶顯示面板的耐壓性能已大幅提昇,其中一種設計即為混合間隙物(hybrid PS)設計,此設計之重點在於使部分之設置於彩色濾光片基板表面之間隙物在組立之後可與薄膜電晶體基板接觸而使得液晶顯示面板可於常時維持一固定的液晶間隙,此部分的間隙物稱為主間隙物(main spacer);而另一部分的間隙物於常時並未與薄膜電晶體基板接觸,而係在液晶顯示面板承受外在施加的壓力時方與薄膜電晶體基板接觸,藉此增加液晶顯示面板的耐壓效果,此部分的間隙物稱為次間隙物(sub spacer)。一般說來,主間隙物與次間隙物具有相同的高度,而薄膜電晶體基板上之平坦層表面上具有複數個對應次間隙物的凹槽,藉此使次間隙物可於常時不與薄膜電晶體基板接觸。然而,設置於平坦層上之畫素電極圖案常容易因為下方之凹槽的高低起伏,使得在進行曝光製程產生光阻因曝光量不足,進而導致顯影不良,造成畫素電極的蝕刻不均問題。此外,在高解析度產品設計上,畫素電極之間的間距需儘量縮小,因此在凹槽處就更容易發現因曝光顯影不良造成畫素電極的透明導電材料的殘留,進而使液晶顯示面板產生亮點或顯示異常等狀況發生。In recent years, with the maturity of the production technology of liquid crystal display panels, products using various types of liquid crystal display panels have also been increasing. Therefore, various characteristics of the liquid crystal display panel have also been widely discussed by the public. Among the characteristics of various types of liquid crystal display panels and various liquid crystal display panels, the withstand voltage of the transmissive liquid crystal display panel is often discussed. After many design changes, the pressure resistance of the transmissive liquid crystal display panel has been greatly improved. One of the designs is a hybrid PS design. The focus of this design is to make part of the color filter substrate. The spacer of the surface can be in contact with the thin film transistor substrate after assembly, so that the liquid crystal display panel can maintain a fixed liquid crystal gap at all times, the spacer of this part is called main spacer; and the spacer of another part It is not in contact with the thin film transistor substrate at all times, but is in contact with the thin film transistor substrate when the liquid crystal display panel is subjected to externally applied pressure, thereby increasing the withstand voltage effect of the liquid crystal display panel, and the spacer of this portion is called Sub spacer. Generally, the main spacer has the same height as the secondary spacer, and the surface of the flat layer on the thin film transistor substrate has a plurality of recesses corresponding to the secondary spacers, thereby making the secondary spacers not always compatible with the thin film. The transistor substrate is in contact. However, the pixel electrode pattern disposed on the flat layer is often easily undulated due to the height of the lower groove, so that the photoresist is exposed during the exposure process due to insufficient exposure, which leads to poor development, causing uneven etching of the pixel electrode. . In addition, in the design of high-resolution products, the spacing between the pixel electrodes should be minimized. Therefore, it is easier to find the residual of the transparent conductive material of the pixel electrode due to poor exposure and development in the groove, thereby making the liquid crystal display panel A condition such as a bright spot or an abnormal display occurs.

本發明之目的之一在於提供一種液晶顯示面板,以解決習知技術面臨之畫素電極的透明導電材料的殘留問題。One of the objects of the present invention is to provide a liquid crystal display panel to solve the problem of residual transparent conductive material of a pixel electrode faced by the prior art.

本發明之一較佳實施例提供一種液晶顯示面板,包括一第一基板、複數條閘極線、複數條資料線、一平坦層以及複數個畫素電極。其中閘極線沿一第一方向設置於第一基板上,且資料線沿一第二方向設置於該第一基板上。平坦層係設置於第一基板上並覆蓋閘極線與資料線。其中,平坦層具有至少一凹槽,且該凹槽係對應於一閘極線與一資料線之一交叉點。畫素電極係設置於平坦層上。與平坦層上之凹槽相鄰並沿第一方向排列之兩畫素電極分別包括一靠近平坦層上之凹槽之第一部分以及一遠離平坦層上之凹槽之第二部分。此兩畫素電極之兩第一部分間具有一第一間距,此兩畫素電極之兩第二部分間具有一第二間距,且第一間距大於第二間距。與平坦層上之凹槽相鄰並沿第二方向排列之兩畫素電極分別包括一靠近平坦層上之凹槽之第一部分以及一遠離平坦層上之凹槽之第二部分。此兩畫素電極之兩第一部分間具有一第三間距,兩畫素電極之兩第二部分間具有一第四間距,且第三間距大於第四間距。A preferred embodiment of the present invention provides a liquid crystal display panel including a first substrate, a plurality of gate lines, a plurality of data lines, a flat layer, and a plurality of pixel electrodes. The gate line is disposed on the first substrate along a first direction, and the data line is disposed on the first substrate along a second direction. The flat layer is disposed on the first substrate and covers the gate line and the data line. Wherein, the flat layer has at least one groove, and the groove corresponds to an intersection of a gate line and a data line. The pixel electrode is disposed on the flat layer. The two pixel electrodes adjacent to the grooves on the flat layer and aligned in the first direction each include a first portion adjacent the groove on the flat layer and a second portion away from the groove on the flat layer. A first pitch is formed between the two first portions of the two pixel electrodes, and a second pitch is formed between the two second portions of the two pixel electrodes, and the first pitch is greater than the second pitch. The two pixel electrodes adjacent to the grooves on the flat layer and arranged in the second direction respectively include a first portion adjacent the groove on the flat layer and a second portion away from the groove on the flat layer. The first portion of the two pixel electrodes has a third pitch therebetween, and the second portions of the two pixel electrodes have a fourth pitch, and the third pitch is greater than the fourth pitch.

本發明之另一較佳實施例提供一種液晶顯示面板,包括一第一基板、複數條閘極線、複數條資料線、一平坦層以及至少四個畫素電極。閘極線係沿一第一方向設置於第一基板上,資料線係沿一第二方向設置於第一基板上,以及平坦層係設置於第一基板上且覆蓋閘極線與資料線。平坦層具有至少一凹槽,且凹槽係對應於一閘極線與一資料線之一交叉點。畫素電極係設置於平坦層上並分別對應於凹槽之四周,且各畫素電極分別具有一缺口面對凹槽。Another preferred embodiment of the present invention provides a liquid crystal display panel including a first substrate, a plurality of gate lines, a plurality of data lines, a flat layer, and at least four pixel electrodes. The gate line is disposed on the first substrate along a first direction, the data line is disposed on the first substrate along a second direction, and the flat layer is disposed on the first substrate and covers the gate line and the data line. The flat layer has at least one groove, and the groove corresponds to an intersection of a gate line and a data line. The pixel electrodes are disposed on the flat layer and respectively correspond to the circumference of the groove, and each of the pixel electrodes has a notch facing groove.

本發明之液晶顯示面板係利用在平坦層上設置凹槽以及凹槽四周之具有兩部份之畫素電極之間具有不等間距設計之液晶顯示面板,藉此使各畫素電極間可保持最小間距,同時避免因凹槽內構成畫素電極之透明導電材料因蝕刻不完全而殘留,進而使液晶顯示面板產生亮點或是顯示異常的問題。The liquid crystal display panel of the present invention utilizes a liquid crystal display panel having unequal pitch designs between two pixel electrodes disposed on the flat layer and around the groove, thereby maintaining the pixels between the pixels. The minimum spacing while avoiding the problem that the transparent conductive material constituting the pixel electrode in the groove remains incomplete due to incomplete etching, thereby causing a bright spot or abnormal display of the liquid crystal display panel.

為了使 貴審查委員能更進一步了解本發明之特徵及技術內容,請參閱以下有關本發明之詳細說明與附圖。然而所附圖示僅供參考與輔助說明用,並非用來對本發明加以限制者。In order to provide a more detailed understanding of the features and technical aspects of the present invention, the following detailed description of the invention and the accompanying drawings. However, the attached drawings are for illustrative purposes only and are not intended to limit the invention.

為使熟習本發明所屬技術領域之一般技藝者能更近一步了解本發明,下文特列舉本發明之較佳實施例,並配合所附圖示,詳細說明本發明的構成內容及所欲達成之功效。The present invention will be described in detail with reference to the preferred embodiments of the present invention, efficacy.

請參考第1A圖、第1B圖與第1C圖。第1A圖與第1B圖繪示了本發明之第一較佳實施例之液晶顯示面板之上視示意圖,第1C圖繪示了本較佳實施例之液晶顯示面板之剖面示意圖,其中為突顯表示本發明之特徵,第1A圖與第1B圖省略了出第二基板、平坦層、閘極線與資料線等元件,而第1B圖更進一步省略了主間隙物以及次間隙物。如第1A圖至第1C圖所示,本發明之較佳實施例之液晶顯示面板10包括第一基板11、複數條閘極線GL、複數條資料線DL、平坦層12以及複數個畫素電極13。閘極線GL沿第一方向S1,例如第1A圖中之水平方向,彼此平行地設置於第一基板11上,且資料線DL沿第二方向S2,例如第1A圖中之垂直方向,彼此平行地設置於第一基板11上。此外,平坦層12係設置於第一基板11上並覆蓋閘極線GL與資料線DL。在本實施例中,平坦層12上具有至少一凹槽C,且凹槽C係大體上對應於閘極線GL與資料線DL之交叉點,且此凹槽C並未貫穿平坦層12。此外,畫素電極13係設置於平坦層12上,且凹槽C的四周設置了四個畫素電極13。值得說明的是,在本實施例中,凹槽C在平坦層12上之配置密度大體上為1.5%至2.2%,但並不以此為限。此外,在本實施例中,凹槽C大體上係為圓形凹槽,具有大體上為0.44埃(,angstrom)至0.84埃之深度,但並不以此為限,凹槽也可以依設計是其他的形狀,例如方形凹槽、多邊形凹槽或不規則形狀凹槽。Please refer to FIG. 1A, FIG. 1B and FIG. 1C. 1A and 1B are schematic top views of a liquid crystal display panel according to a first preferred embodiment of the present invention, and FIG. 1C is a cross-sectional view of the liquid crystal display panel of the preferred embodiment, wherein the liquid crystal display panel is highlighted. The features of the present invention are shown in Figs. 1A and 1B, and elements such as a second substrate, a flat layer, a gate line, and a data line are omitted, and the main spacer and the secondary spacer are further omitted in Fig. 1B. As shown in FIGS. 1A to 1C, the liquid crystal display panel 10 of the preferred embodiment of the present invention includes a first substrate 11, a plurality of gate lines GL, a plurality of data lines DL, a flat layer 12, and a plurality of pixels. Electrode 13. The gate lines GL are disposed on the first substrate 11 in parallel with each other in the first direction S1, for example, the horizontal direction in FIG. 1A, and the data lines DL are in the second direction S2, for example, the vertical direction in FIG. The first substrate 11 is disposed in parallel. Further, the flat layer 12 is disposed on the first substrate 11 and covers the gate line GL and the data line DL. In the present embodiment, the flat layer 12 has at least one groove C thereon, and the groove C substantially corresponds to the intersection of the gate line GL and the data line DL, and the groove C does not penetrate the flat layer 12. Further, the pixel electrode 13 is disposed on the flat layer 12, and four pixel electrodes 13 are disposed around the groove C. It should be noted that, in this embodiment, the arrangement density of the groove C on the flat layer 12 is substantially 1.5% to 2.2%, but is not limited thereto. Further, in the present embodiment, the groove C is substantially a circular groove having a height of substantially 0.44 angstroms ( , angstrom) to a depth of 0.84 angstroms, but not limited to this, the groove can also be other shapes according to the design, such as a square groove, a polygonal groove or an irregular shape groove.

在本實施例中,與平坦層12上之凹槽C相鄰並沿第一方向S1排列之兩畫素電極13分別包括靠近平坦層12上之凹槽C之第一部分131以及遠離平坦層12上之凹槽C之第二部分132。此兩畫素電極13之兩第一部分131間具有第一間距D1,此兩畫素電極13之兩第二部分132間具有第二間距D2,且第一間距D1大於第二間距D2。另一方面,與平坦層12上之凹槽C相鄰並沿第二方向S2排列之兩畫素電極13分別包括靠近平坦層12上之凹槽C之第一部分131以及一遠離平坦層上之凹槽之第二部分132。此兩畫素電極13之兩第一部分131間具有第三間距D3,兩畫素電極13之兩第二部分132間具有一第四間距D4,且第三間距D3大於第四間距D4。在本實施例中,第一間距D1大體上係介於6微米與7.5微米之間,第二間距D2大體上係介於4微米與5.5微米之間,第三間距D3大體上係介於6微米與7.5微米之間,且第四間距D4大體上係介於4微米與5.5微米之間,但不以此為限。In the present embodiment, the two pixel electrodes 13 adjacent to the groove C on the flat layer 12 and arranged in the first direction S1 respectively include the first portion 131 of the groove C near the flat layer 12 and away from the flat layer 12 The second portion 132 of the groove C is formed. The first portion 131 of the two pixel electrodes 13 has a first pitch D1, and the second portions 132 of the two pixel electrodes 13 have a second pitch D2, and the first pitch D1 is greater than the second pitch D2. On the other hand, the two pixel electrodes 13 adjacent to the groove C on the flat layer 12 and arranged in the second direction S2 respectively include a first portion 131 adjacent to the groove C on the flat layer 12 and a distance from the flat layer. The second portion 132 of the recess. The first portion 131 of the two pixel electrodes 13 has a third pitch D3, and the second portions 132 of the two pixel electrodes 13 have a fourth pitch D4, and the third pitch D3 is greater than the fourth pitch D4. In this embodiment, the first pitch D1 is substantially between 6 micrometers and 7.5 micrometers, the second pitch D2 is substantially between 4 micrometers and 5.5 micrometers, and the third pitch D3 is substantially between 6 micrometers and 5.5 micrometers. The micrometer is between 7.5 micrometers and the fourth pitch D4 is substantially between 4 micrometers and 5.5 micrometers, but is not limited thereto.

由上述可知,在本實施例中,凹槽C與其四周的畫素電極13之間的重疊面積減少了,因此可減少因平坦層12之高低落差產生之蝕刻不良的問題。此外,在各畫素電極13之遠離凹槽C之第二部份132之間仍可擁有較小之間距,而可得到高解析度的表現。換句話說,在本實施例中,相較於一般畫素電極13的矩形(如第1B圖中虛線所示),設置於凹槽C四周之四個畫素電極13之靠近凹槽之第一部份131,分別具有一向各畫素電極13內部內縮之缺口G,用以減少畫素電極13與凹槽C的重疊面積,進而減少因凹槽C與四周平坦層12之高低落差而導致後續定義畫素電極13的圖案時產生蝕刻不均而造成透明導電材質例如氧化銦錫殘留的問題。As apparent from the above, in the present embodiment, the overlapping area between the groove C and the pixel electrodes 13 around it is reduced, so that the problem of poor etching due to the difference in height of the flat layer 12 can be reduced. In addition, a small distance between the respective pixel electrodes 13 away from the second portion 132 of the groove C can be obtained, and a high resolution performance can be obtained. In other words, in the present embodiment, compared to the rectangular shape of the general pixel electrode 13 (as indicated by the broken line in FIG. 1B), the four pixel electrodes 13 disposed around the groove C are close to the groove. A portion 131 has a notch G which is internally contracted inside the respective pixel electrodes 13 to reduce the overlapping area of the pixel electrode 13 and the groove C, thereby reducing the height difference between the groove C and the surrounding flat layer 12. This causes a problem that uneven etching occurs when the pattern of the pixel electrode 13 is subsequently defined, resulting in a residual transparent conductive material such as indium tin oxide.

此外,在本實施例中,例如第1C圖,與凹槽C相鄰並沿第一方向S1排列之兩畫素電極13之兩第一部分131係與凹槽C部分重疊,且與凹槽C相鄰並沿第二方向S2排列之兩畫素電極13之兩第一部分131亦與凹槽部分重疊,但並不以此為限。Further, in the present embodiment, for example, in FIG. 1C, the two first portions 131 of the two pixel electrodes 13 adjacent to the groove C and arranged in the first direction S1 partially overlap the groove C, and the groove C The two first portions 131 of the two pixel electrodes 13 adjacent to each other and arranged in the second direction S2 also overlap with the groove portion, but are not limited thereto.

此外,如第1C圖所示,本發明之液晶顯示面板10另包括一第二基板14、至少一主間隙物PS1、以及至少一次間隙物PS2。第二基板14與第一基板11相對設置。此外,主間隙物PS1與次間隙物PS2係分別設置於第二基板14面對第一基板11之表面141上,且主間隙物PS1與次間隙物PS2具有相同之高度H2。主間隙物PS1係大體上對應於閘極線GL與資料線DL之一交叉點,且在此位置之平坦層12並無凹槽設計,因此主間隙物PS1係與平坦層12之一平坦表面接觸。此外,次間隙物PS2係大體上對應於平坦層12上之凹槽C,且凹槽C之深度將次間隙物PS2與平坦層12隔開,使次間隙物PS2與平坦層12之間形成距離H1而不互相接觸,其中距離H1約等於凹槽C的深度。值得說明的是,在本實施例中,係以一複合間隙物型(Hybrid PS)液晶顯示面板為例說明,也就是說,在設計上係在平坦層上設置凹槽,使液晶顯示面板於組立後具有與平坦層接觸之主間隙物以及並未與平坦層接觸之次間隙物,用以提升液晶顯示面板之耐壓程度。In addition, as shown in FIG. 1C, the liquid crystal display panel 10 of the present invention further includes a second substrate 14, at least one main spacer PS1, and at least one spacer PS2. The second substrate 14 is disposed opposite to the first substrate 11. In addition, the main spacer PS1 and the secondary spacer PS2 are respectively disposed on the surface 141 of the second substrate 14 facing the first substrate 11, and the main spacer PS1 and the secondary spacer PS2 have the same height H2. The main spacer PS1 substantially corresponds to one of the intersections of the gate line GL and the data line DL, and the flat layer 12 at this position has no groove design, so the main spacer PS1 is flat with one of the flat layers 12. contact. In addition, the secondary spacer PS2 substantially corresponds to the recess C on the flat layer 12, and the depth of the recess C separates the secondary spacer PS2 from the flat layer 12 to form a gap between the secondary spacer PS2 and the flat layer 12. The distance H1 is not in contact with each other, wherein the distance H1 is approximately equal to the depth of the groove C. It should be noted that, in this embodiment, a composite spacer type (Hybrid PS) liquid crystal display panel is taken as an example, that is, a groove is arranged on the flat layer to make the liquid crystal display panel After assembly, the main spacers in contact with the flat layer and the secondary spacers not in contact with the flat layer are used to improve the withstand voltage of the liquid crystal display panel.

本發明之液晶顯示面板並不以上述實施例為限,而可具有其他不同之實施型態。為了簡化說明並易於比較,在下文之本發明之其他較佳實施例中,對於相同元件沿用相同之符號表示,並僅對兩實施例之相異處進行詳述。請參考第2A圖至第2C圖,第2A圖與第2B圖繪示了本發明之第二較佳實施例之液晶顯示面板之上視示意圖,第2C圖繪示了本較佳實施例之液晶顯示面板之剖面示意圖,其中第2B圖省略了主間隙物以及次間隙物。如第2A圖至第2C圖所示,在本較佳實施例之液晶顯示面板30中,與凹槽C相鄰並沿第一方向S1排列之兩畫素電極13之兩第一部分131可與凹槽C之邊緣大體上切齊,且與凹槽C相鄰且沿第二方向S2排列之兩畫素電極13之兩第一部分131亦可與凹槽C之邊緣大體上切齊。換句話說,各畫素電極13的缺口G與凹槽C之邊緣大體上切齊。由於畫素電極13未與凹槽C重疊,因此可避免畫素電極13產生蝕刻不均。The liquid crystal display panel of the present invention is not limited to the above embodiments, but may have other different implementation forms. In the following, in the other preferred embodiments of the present invention, the same elements are denoted by the same reference numerals, and only the differences between the two embodiments will be described in detail. Please refer to FIG. 2A to FIG. 2C. FIG. 2A and FIG. 2B are schematic top views of a liquid crystal display panel according to a second preferred embodiment of the present invention, and FIG. 2C is a view of the preferred embodiment. A schematic cross-sectional view of a liquid crystal display panel in which the main spacer and the secondary spacer are omitted in FIG. 2B. As shown in FIGS. 2A to 2C, in the liquid crystal display panel 30 of the preferred embodiment, the two first portions 131 of the two pixel electrodes 13 adjacent to the groove C and arranged in the first direction S1 can be The edges of the grooves C are substantially aligned, and the two first portions 131 of the two pixel electrodes 13 adjacent to the grooves C and arranged in the second direction S2 may also be substantially aligned with the edges of the grooves C. In other words, the notch G of each of the pixel electrodes 13 is substantially aligned with the edge of the groove C. Since the pixel electrode 13 does not overlap with the groove C, unevenness in etching of the pixel electrode 13 can be avoided.

請另參考第3A圖至第3C圖,第3A圖與第3B圖繪示了本發明之第三較佳實施例之液晶顯示面板之上視示意圖,第3C圖繪示了本較佳實施例之液晶顯示面板之剖面示意圖,其中第3B圖省略了主間隙物以及次間隙物。如第3A圖至第3C圖所示,在本較佳實施例之液晶顯示面板40中,與凹槽C相鄰且沿第一方向S1排列之兩畫素電極13之兩第一部分131分別與凹槽C具有一間隙F,且與凹槽C相鄰且沿第二方向S2排列之兩畫素電極13之兩第一部分131分別與凹槽C具有一間隙F。由於畫素電極13未與凹槽C重疊,因此可避免畫素電極13產生蝕刻不均。Please refer to FIG. 3A to FIG. 3C. FIG. 3A and FIG. 3B are schematic top views of a liquid crystal display panel according to a third preferred embodiment of the present invention, and FIG. 3C illustrates the preferred embodiment. A schematic cross-sectional view of the liquid crystal display panel, wherein the main spacer and the secondary spacer are omitted in FIG. 3B. As shown in FIGS. 3A to 3C, in the liquid crystal display panel 40 of the preferred embodiment, the two first portions 131 of the two pixel electrodes 13 adjacent to the groove C and arranged in the first direction S1 are respectively The groove C has a gap F, and the two first portions 131 of the two pixel electrodes 13 adjacent to the groove C and arranged in the second direction S2 have a gap F with the groove C, respectively. Since the pixel electrode 13 does not overlap with the groove C, unevenness in etching of the pixel electrode 13 can be avoided.

綜上所述,本發明之液晶顯示面板係利用在平坦層上設置凹槽以及位於凹槽四周之具有兩部份之畫素電極之間具有不等間距之設計,使各畫素電極間保持最小間距,且同時避免因凹槽內構成畫素電極之透明導電材料因蝕刻不完全而殘留,進而使液晶顯示面板產生亮點或是顯示異常的問題。In summary, the liquid crystal display panel of the present invention has a design in which a groove is provided on a flat layer and a two-part pixel electrode located around the groove has an unequal spacing to maintain the pixel electrodes. The minimum pitch is at the same time, and at the same time, the problem that the transparent conductive material constituting the pixel electrode in the groove remains due to incomplete etching, thereby causing a bright spot or abnormal display of the liquid crystal display panel.

以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10,30,40...液晶顯示面板10,30,40. . . LCD panel

11、14...基板11, 14. . . Substrate

12...平坦層12. . . Flat layer

13...畫素電極13. . . Pixel electrode

131...第一部份131. . . first part

132...第二部份132. . . Second part

141...表面141. . . surface

C...凹槽C. . . Groove

D1...第一間距D1. . . First spacing

D2...第二間距D2. . . Second spacing

D3...第三間距D3. . . Third spacing

D4...第四間距D4. . . Fourth pitch

DL...資料線DL. . . Data line

GL...閘極線GL. . . Gate line

G...缺口G. . . gap

F...間隙F. . . gap

PS1...主間隙物PS1. . . Main spacer

PS2...次間隙物PS2. . . Secondary spacer

S1...第一方向S1. . . First direction

S2...第二方向S2. . . Second direction

H1...距離H1. . . distance

H2...高度H2. . . height

第1A圖與第1B圖繪示了本發明之第一較佳實施例之液晶顯示面板之上視示意圖。1A and 1B are top plan views of a liquid crystal display panel according to a first preferred embodiment of the present invention.

第1C圖繪示了本較佳實施例之液晶顯示面板之剖面示意圖。FIG. 1C is a cross-sectional view showing the liquid crystal display panel of the preferred embodiment.

第2A圖與第2B圖繪示了本發明之第二較佳實施例之液晶顯示面板之上視示意圖。2A and 2B are top views of a liquid crystal display panel according to a second preferred embodiment of the present invention.

第2C圖繪示了本較佳實施例之液晶顯示面板之剖面示意圖。2C is a cross-sectional view showing the liquid crystal display panel of the preferred embodiment.

第3A圖與第3B圖繪示了本發明之第三較佳實施例之液晶顯示面板之上視示意圖。3A and 3B are top views of a liquid crystal display panel according to a third preferred embodiment of the present invention.

第3C圖繪示了本較佳實施例之液晶顯示面板之剖面示意圖。FIG. 3C is a cross-sectional view showing the liquid crystal display panel of the preferred embodiment.

10...液晶顯示面板10. . . LCD panel

11...基板11. . . Substrate

13...畫素電極13. . . Pixel electrode

131...第一部份131. . . first part

132...第二部份132. . . Second part

C...凹槽C. . . Groove

D1...第一間距D1. . . First spacing

D2...第二間距D2. . . Second spacing

D3...第三間距D3. . . Third spacing

D4...第四間距D4. . . Fourth pitch

G...缺口G. . . gap

PS2...次間隙物PS2. . . Secondary spacer

PS1...主間隙物PS1. . . Main spacer

S1...第一方向S1. . . First direction

S2...第二方向S2. . . Second direction

Claims (19)

一種液晶顯示面板,包含:一第一基板;複數條閘極線,沿一第一方向設置於該第一基板上;複數條資料線,沿一第二方向設置於該第一基板上;一平坦層,設置於該第一基板上並覆蓋該等閘極線與該等資料線,其中該平坦層具有至少一凹槽,該凹槽未貫穿該平坦層,且該凹槽係對應於一該閘極線與一該資料線之一交叉點;以及複數個畫素電極,設置於該平坦層上,其中與該凹槽相鄰且沿該第一方向排列之該兩畫素電極分別包括一第一部分以及一第二部分,沿該第一方向排列之該兩畫素電極之各該第一部分與該凹槽之間的距離係小於沿該第一方向排列之該兩畫素電極之各該第二部分與該凹槽之間的距離,沿該第一方向排列之該兩畫素電極之該兩第一部分之間具有一第一間距,沿該第一方向排列之該兩畫素電極之該兩第二部分之間具有一第二間距,且該第一間距大於該第二間距,以及與該凹槽相鄰且沿該第二方向排列之該兩畫素電極分別包括一第一部分以及一第二部分,沿該第二方向排列之該兩畫素電極之各該第一部分與該凹槽之間的距離係小於沿該第二方向排列之該兩畫素電極之各該第二部分與該凹槽之間的距離,沿該第二方向排列之該兩畫素電極之該兩第一部分之間具有一第三間 距,沿該第二方向排列之該兩畫素電極之該兩第二部分之間具有一第四間距,且該第三間距大於該第四間距。 A liquid crystal display panel comprising: a first substrate; a plurality of gate lines disposed on the first substrate along a first direction; a plurality of data lines disposed on the first substrate along a second direction; a flat layer disposed on the first substrate and covering the gate lines and the data lines, wherein the flat layer has at least one groove, the groove does not penetrate the flat layer, and the groove corresponds to a And a plurality of pixel electrodes disposed on the flat layer, wherein the two pixel electrodes adjacent to the groove and arranged along the first direction respectively comprise a first portion and a second portion, wherein a distance between each of the first portions of the two pixel electrodes arranged in the first direction and the groove is smaller than each of the two pixel electrodes arranged along the first direction a distance between the second portion and the recess, a first pitch between the two first portions of the two pixel electrodes arranged along the first direction, and the two pixel electrodes arranged along the first direction There is a second spacing between the two second portions, The first pitch is greater than the second pitch, and the two pixel electrodes adjacent to the groove and arranged along the second direction respectively comprise a first portion and a second portion, the two arranged along the second direction The distance between each of the first portions of the pixel electrodes and the recess is smaller than the distance between the second portions of the two pixel electrodes arranged in the second direction and the recess, along the second direction Having a third room between the two first portions of the two pixel electrodes And a second spacing between the two second portions of the two pixel electrodes arranged along the second direction, and the third spacing is greater than the fourth spacing. 如申請專利範圍第1項所述之液晶顯示面板,其中與該凹槽相鄰且沿該第一方向排列之該兩畫素電極之該兩第一部分係與該凹槽部分重疊,且與該凹槽相鄰且沿該第二方向排列之該兩畫素電極之該兩第一部分係與該凹槽部分重疊。 The liquid crystal display panel of claim 1, wherein the two first portions of the two pixel electrodes adjacent to the groove and arranged along the first direction partially overlap the groove, and The two first portions of the two pixel electrodes adjacent to each other and arranged in the second direction partially overlap the groove. 如申請專利範圍第2項所述之液晶顯示面板,其中該第一間距係介於6微米與7.5微米之間,該第二間距係介於4微米與5.5微米之間,該第三間距係介於6微米與7.5微米之間,且該第四間距係介於4微米與5.5微米之間。 The liquid crystal display panel of claim 2, wherein the first pitch is between 6 micrometers and 7.5 micrometers, and the second pitch is between 4 micrometers and 5.5 micrometers. Between 6 microns and 7.5 microns, and the fourth pitch is between 4 microns and 5.5 microns. 如申請專利範圍第1項所述之液晶顯示面板,其中與該凹槽相鄰且沿該第一方向排列之該兩畫素電極之該兩第一部分係與該凹槽之邊緣切齊,且與該凹槽相鄰且沿該第二方向排列之該兩畫素電極之該兩第一部分係與該凹槽之一邊緣切齊。 The liquid crystal display panel of claim 1, wherein the two first portions of the two pixel electrodes adjacent to the groove and arranged along the first direction are aligned with edges of the groove, and The two first portions of the two pixel electrodes adjacent to the groove and arranged in the second direction are aligned with an edge of the groove. 如申請專利範圍第1項所述之液晶顯示面板,其中與該凹槽相鄰且沿該第一方向排列之該兩畫素電極之該兩第一部分分別與該凹槽具有一間隙,且與該凹槽相鄰且沿該第二方向排列之該兩畫素電極之該兩第一部分分別與該凹槽具有一間隙。 The liquid crystal display panel of claim 1, wherein the two first portions of the two pixel electrodes adjacent to the groove and arranged along the first direction respectively have a gap with the groove, and The two first portions of the two pixel electrodes adjacent to the groove and arranged along the second direction respectively have a gap with the groove. 如申請專利範圍第1項所述之液晶顯示面板,另包括;一第二基板,與該第一基板相對設置;以及至少一次間隙物,設置於該第二基板面對該第一基板之一表面,並大體上對應於該平坦層之該至少一凹槽,其中該次間隙物與該平坦層之間具有一距離。 The liquid crystal display panel of claim 1, further comprising: a second substrate disposed opposite to the first substrate; and at least one spacer disposed on the second substrate facing the first substrate a surface, and generally corresponding to the at least one groove of the planar layer, wherein the secondary spacer has a distance from the planar layer. 如申請專利範圍第6項所述之液晶顯示面板,另包括至少一主間隙物,設置於該第二基板面對該第一基板之該表面,該至少一主間隙物對應於一該閘極線與一該資料線之一交叉點,且該至少一主間隙物與該平坦層接觸。 The liquid crystal display panel of claim 6, further comprising at least one main spacer disposed on the surface of the second substrate facing the first substrate, the at least one main spacer corresponding to the gate The line intersects with one of the data lines, and the at least one main spacer is in contact with the flat layer. 如申請專利範圍第7項所述之液晶顯示面板,其中該至少一次間隙物與該至少一主間隙物具有相同之高度。 The liquid crystal display panel of claim 7, wherein the at least one spacer has the same height as the at least one main spacer. 如申請專利範圍第6項所述之液晶顯示面板,其中該次間隙物與該平坦層間之該距離與該凹槽之深度相等。 The liquid crystal display panel of claim 6, wherein the distance between the spacer and the flat layer is equal to the depth of the recess. 如申請專利範圍第1項所述之液晶顯示面板,其中該凹槽之深度範圍在0.44埃至0.84埃之間。 The liquid crystal display panel of claim 1, wherein the groove has a depth ranging from 0.44 angstroms to 0.84 angstroms. 一種液晶顯示面板,包含:一第一基板;複數條閘極線,沿一第一方向設置於該第一基板上; 複數條資料線,沿一第二方向設置於該第一基板上;一平坦層,設置於該第一基板上並覆蓋該等閘極線與該等資料線,其中該平坦層具有至少一凹槽,該凹槽未貫穿該平坦層,且該凹槽係對應於一該閘極線與一該資料線之一交叉點;以及四個畫素電極,設置於該平坦層上並分別對應於該凹槽之四周,其中各該畫素電極分別具有一缺口面對該凹槽。 A liquid crystal display panel comprising: a first substrate; a plurality of gate lines disposed on the first substrate along a first direction; a plurality of data lines disposed on the first substrate along a second direction; a flat layer disposed on the first substrate and covering the gate lines and the data lines, wherein the flat layer has at least one recess a groove, the groove does not penetrate the flat layer, and the groove corresponds to a intersection of the gate line and one of the data lines; and four pixel electrodes are disposed on the flat layer and respectively correspond to Around the groove, each of the pixel electrodes has a notch facing the groove. 如申請專利範圍第11項所述之液晶顯示面板,其中設置於該凹槽四周之各該畫素電極分別與該凹槽部分重疊。 The liquid crystal display panel of claim 11, wherein each of the pixel electrodes disposed around the groove overlaps the groove portion. 如申請專利範圍第11項所述之液晶顯示面板,其中設置於該凹槽四周之各該畫素電極之該缺口與該凹槽之邊緣切齊。 The liquid crystal display panel of claim 11, wherein the notch of each of the pixel electrodes disposed around the groove is aligned with an edge of the groove. 如申請專利範圍第11項所述之液晶顯示面板,其中設置於該凹槽四周之各該畫素電極未與該凹槽重疊,且各該畫素電極與該凹槽具有一間隙。 The liquid crystal display panel of claim 11, wherein each of the pixel electrodes disposed around the groove does not overlap the groove, and each of the pixel electrodes has a gap with the groove. 如申請專利範圍第11項所述之液晶顯示面板,另包括;一第二基板,與該第一基板相對設置;以及至少一次間隙物,設置於該第二基板面對該第一基板之一表面,並大體上對應於該平坦層之該至少一凹槽,其中該次間隙物與該平坦層之間具有一距離。 The liquid crystal display panel of claim 11, further comprising: a second substrate disposed opposite to the first substrate; and at least one spacer disposed on the second substrate facing the first substrate a surface, and generally corresponding to the at least one groove of the planar layer, wherein the secondary spacer has a distance from the planar layer. 如申請專利範圍第15項所述之液晶顯示面板,另包括至少一主間隙物,設置於該第二基板面對該第一基板之該表面,該至少一主間隙物對應於一該閘極線與一該資料線之一交叉點,且該至少一主間隙物與該平坦層接觸。 The liquid crystal display panel of claim 15, further comprising at least one main spacer disposed on the surface of the second substrate facing the first substrate, the at least one main spacer corresponding to the gate The line intersects with one of the data lines, and the at least one main spacer is in contact with the flat layer. 如申請專利範圍第16項所述之液晶顯示面板,其中該至少一次間隙物與該至少一主間隙物具有相同之高度。 The liquid crystal display panel of claim 16, wherein the at least one spacer has the same height as the at least one main spacer. 如申請專利範圍第15項所述之液晶顯示面板,其中該次間隙物與該平坦層間之該距離與該凹槽之深度相等。 The liquid crystal display panel of claim 15, wherein the distance between the spacer and the flat layer is equal to the depth of the recess. 如申請專利範圍第11項所述之液晶顯示面板,其中該凹槽之深度範圍在0.44埃至0.84埃之間。 The liquid crystal display panel of claim 11, wherein the groove has a depth ranging from 0.44 angstroms to 0.84 angstroms.
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