TWI426543B - Method for reducing pitch in integrated circuit process - Google Patents

Description

Method for reducing pitch in integrated circuit process

The present invention relates to a process for integrating circuits (ICs) and semiconductor devices. More specifically, the present invention provides a method of reducing the pitch of integrated circuit components. By way of example only, the invention has been applied to integrated circuits including arrays and peripheral regions. However, it should be recognized that the invention has broader applicability. For example, the invention can be applied to form patterns having a smaller width and spacing than the smallest feature size.

Integrated circuits have evolved from a few interconnected components fabricated on a single germanium wafer to millions of components. In order to achieve improvements in the coverage and circuit density (eg, the number of components that can be placed over a given wafer area), the feature size of the smallest component, known as the "geometry" of the component, has been with each generation of ICs. Become smaller. Semiconductor devices are now fabricated with features that are less than one tenth of a micron wide.

Since the various processes and equipment used in IC fabrication have certain limits, it is very challenging to make components smaller. Conventional processes are typically limited to the smallest feature size that can be reworked. For example, the component pitch of an integrated circuit that is commonly used to measure the size of re-line and space is often limited by lithography equipment and processes. When the half pitch is less than 65 nm, especially less than 45 nm, the lithography process generally becomes difficult.

Accordingly, there is a need for an improved patterning technique that is not limited to the minimum feature sizes of conventional process equipment and processes.

The present invention relates to a process for an integrated circuit and a semiconductor device. More specifically, the present invention provides a method of reducing the pitch of integrated circuit components. By way of example only, the invention has been applied to integrated circuits including arrays and peripheral regions. However, it should be recognized that the invention has broader applicability. For example, the invention can be applied to form patterns having a smaller width and spacing than the smallest feature size.

In an embodiment, the invention provides a method of patterning a material. The method includes patterning a second material over a first material on a substrate. The surface portion of the patterned second material is converted to form a third material and the remaining patterned second material, wherein the third material is located around the remaining patterned second material. One of the remaining patterned second material and third material is removed to form a mask. The first material is patterned using a mask.

In an embodiment, the removing step includes selectively etching the third material or the remaining patterned second material. In another embodiment, the method further includes removing a portion of the third material to expose a top surface of the remaining patterned second material. In another embodiment, removing a portion of the third material includes using a chemical mechanical polishing (CMP) process. In yet another embodiment, removing a portion of the third material includes using an etch process. In one embodiment, the converting step includes oxidizing a surface portion of the patterned second material. In another embodiment, the second material comprises a ruthenium containing material. In another embodiment, the converting step includes at least one of an oxidation process, a nitridation process, and a metal deuteration process. In yet another embodiment, the third material comprises At least one of tantalum nitride, ruthenium oxide, and metal halide. In one embodiment, the mask comprises at least one of tantalum, niobium oxide, tantalum nitride, and metal telluride. In another embodiment, the method further includes forming a fourth material in at least one gap of the patterned second material. In another embodiment, the second material and the fourth material are substantially the same material.

Another embodiment of the invention provides a method of patterning a material. The method includes patterning a first material overlying the substrate. The first portion of the material is converted to form a plurality of second materials. A third material is filled in the gap between the joined second materials. At least one of the first material, the second material, and the third material is removed to form a plurality of features and a plurality of spaces.

The method of the present invention achieves a number of advantages over conventional techniques. For example, the present technology provides an easy to use process that relies on conventional techniques. In a particular embodiment, the spacing of the repeating patterns can be reduced using the methods provided by the present invention. However, this method is not limited to this pattern. In other embodiments, the methods provided herein can be used to form features having a smaller width and spacing than the smallest feature size. Additionally, this method can be applied repeatedly to form even smaller feature sizes, spacings or spacings. Since the critical dimensions are determined by the chemical reactions in the methods provided by the present invention, this method is not limited to the minimum feature size of the lithography process. In addition, the method provides a process that is compatible with conventional process technologies without the need to substantially alter traditional equipment and processes. Depending on the embodiment, one or more of these advantages may be realized. These and other advantages will be described in further detail in this specification and in particular in the following.

Additional objects, features and advantages of the present invention will be apparent from the description and appended claims appended claims.

The present invention relates to a process for an integrated circuit and a semiconductor device. More specifically, the present invention provides a method of reducing the pitch of integrated circuit components. By way of example only, the invention has been applied to integrated circuits including arrays and peripheral regions. However, it should be recognized that the invention has broader applicability. For example, the invention can be applied to form patterns having a smaller width and spacing than the smallest feature size.

As noted above, the minimum feature size typically limits the component spacing that can be made using conventional devices and processes. A variety of techniques have been proposed to make features that are smaller than the minimum feature size. These techniques often involve the formation of spacers and are often complicated. Another disadvantage of these techniques is that they generally cannot simultaneously reduce the width and spacing of line features. Therefore, there is a need for an improved patterning technique.

According to an embodiment, the invention includes a variety of features that can be used. These features include the following aspects: 1. Techniques for smaller lines and spaces than the minimum feature size of lithography; 2. Simultaneous reduction of line and space size; 3. Simple to use and weight of conventional process equipment and processes Overlay method; and 4. method for size of multiple lines and spaces that are smaller than the minimum feature.

As shown, the above features may exist in one or more of the following embodiments. These features are merely examples and should not be improperly qualified Apply for a patent scope. Anyone familiar with the art can make a variety of changes, modifications and alternatives.

1-4 are simplified cross-sectional views of a method of forming small patterned features in an integrated circuit in accordance with an embodiment of the present invention. These drawings are merely examples and should not unduly limit the scope of the patent application herein. Anyone familiar with the art can make other changes, modifications and alternatives. In a particular embodiment, the small patterned features are part of the integrated circuit fabrication process. As shown in FIG. 1, this method provides a substrate 101 that can include a semiconductor substrate, such as a germanium substrate. In addition, the substrate 101 may include an element structure fabricated using a conventional integrated circuit process technology. In the particular embodiment shown in FIG. 1, substrate 101 includes a layer of insulating material 103, such as an oxide or nitride, overlying underlying layer 102. In an embodiment, the lower layer 102 can comprise a conventional integrated circuit component structure. Next, a first layer of polysilicon overlying the substrate 101 is formed and patterned using conventional patterning techniques to form polysilicon features, such as 104. Such conventional patterning techniques can include lithography and etching processes. In one embodiment, each polysilicon feature 104 includes sidewalls and a top surface as shown in FIG. For example, the polysilicon feature 104 has a width L and is separated from adjacent polysilicon features by a spacing S. In a particular embodiment, the polysilicon feature can be a repeating pattern comprising line width L and spacing S in the pattern. In other embodiments, the size and spacing associated with the polysilicon feature can vary.

In FIG. 2, a chemical reaction process is performed to convert polysilicon features to form oxidized polysilicon features, such as 204. In an embodiment, the chemical reaction process includes thermal oxidation of polycrystalline germanium forming oxide 205. Each oxidized polysilicon feature includes A first region of the polysilicon feature 206 sandwiched between the two oxide regions 207 and 208 of width L1. As shown, each of the two oxide regions 207 and 208 is characterized by a thickness O1. In the oxidation process, the first thickness of the polysilicon at the sidewalls of each polysilicon feature 104 is converted to form an oxide having a thickness of O1. As shown in Figure 2, the spacing between the oxidized polysilicon feature 204 and the adjacent oxidized polysilicon feature is designated S1.

Next, the method includes forming a second layer of polysilicon 210 overlying the oxidized polysilicon features and the substrate. The second layer of polysilicon fills the gap between adjacent oxidized polysilicon features. As shown in FIG. 2, the designated gap 209 has an interval S1. According to the chemical reaction, a relationship as described below can be formed between the respective sizes.

In FIG. 3, the method includes forming a substantially planar structure 301 by selectively removing portions of the second polycrystalline germanium and portions of the oxidized polysilicon features. In one embodiment, a chemical mechanical polishing process is used to form a substantially planar structure. In another embodiment, an etch back process can be used. Referring to FIG. 2, a portion of the second polysilicon 210 and a portion of the oxidized polysilicon feature 204 are removed. The top surface of the polysilicon feature 206, the oxide region 207, and the oxide region 208 are exposed to form a substantially planar structure. As shown in FIG. 3, the substantially planar structure includes alternative features of polycrystalline germanium (e.g., 206) and oxide (e.g., 207). According to an embodiment, a pattern of polysilicon features or a pattern of oxide features as described below may be formed.

In FIG. 4, in accordance with a particular embodiment, the method includes removing polysilicon from the substantially planar structure 301 to form a pattern of oxide features (e.g., 207). A conventional etching process can be used here. For example, using polycrystalline germanium An etching process that aligns oxides to exhibit better etch selectivity is advantageous. It can be seen that the number of oxide features is greater than the number of original polysilicon features (104 in Figure 1). Additionally, as described below, the width of the oxide features can be made smaller than the width of the original polysilicon feature (e.g., 104).

Figure 5 is a simplified cross-sectional view of an alternative process of the method depicted in Figures 1-4, in accordance with an embodiment of the present invention. As shown, the method includes removing oxide from the substantially planar structure 301 in FIG. 3 to form a polysilicon feature (206 in FIG. 5) pattern. A conventional etching process can be used here. It can be seen that the number of polysilicon features is greater than the number of original polysilicon features (104 in Figure 1). As described below, the width of the polysilicon feature (e.g., 206) can be made smaller than the width of the original polysilicon feature (e.g., 104).

In the thermal oxidation of ruthenium, a certain amount of ruthenium can be converted to another amount of oxide. The ratio of the amount of ruthenium consumed to the amount of oxide synthesized is about 0.44. Referring again to FIG. 2, by designating a volume conversion ratio as a VCR, the following relationship can be established.

(1) L1=L-2*(O1*VCR)(2)S1=S-2*(O1*(1-VCR))(3)L+S=L1+S1+2*O1 The original size = L, the original size of the interval = S, L1 indicates the width of the characteristic material after the reaction, O1 indicates the thickness of the formed new material, and S1 is the interval between the converted features. In accordance with embodiments of the present invention, these parameters can be used to form patterns that include different combinations of feature sizes and spacing. As in the specific example of Figure 4, the spacing of the patterns is essentially a map. One half of the pattern spacing in 1 . Further, the line width in FIG. 4 (i.e., equivalent to O1 in FIG. 2) is smaller than the line width L in FIG. The interval in FIG. 4 (ie, S1 in FIG. 2) is smaller than the interval S in FIG. Similarly, the pitch, line width, and spacing in FIG. 5 are smaller than the pitch, line width, and spacing in FIG. 1, respectively. Of course, as described below, other variations and alternatives are possible.

6-10 are simplified cross-sectional views of another method of forming small features in an integrated circuit process in accordance with an embodiment of the present invention. This method includes a process similar to that described above. By adjusting the oxidation process, oxides O1 of different thicknesses can be formed on the sidewalls of the synthesized polysilicon. Therefore, different combinations of the width and the interval of the oxide pattern in FIG. 9 or the width and interval of the polysilicon pattern in FIG. 10 can be obtained.

11A-11C are simplified diagrams showing the size of features that can be implemented in the method of Figs. 1-10, in accordance with an embodiment of the present invention. 11A-11C are some examples showing the composite width L1 and the interval S1 which can be obtained by changing the initial width L, the initial interval S, and the oxide thickness O1. For example, in Figure 11A, L = 98 nm and S = 122 nm. L1 and S1 are listed in Table 1 as a function of O1, where the unit is nanometer.

In Fig. 11B, L = 103 nm, and S = 117 nm. L1 and S1 are listed in Table 2 below as a function of O1 (in nanometers)

In Figure 11C, L = 108 nm and S = 1212 nm. L1 and S1 are listed in Table 3 below as a function of O1 (in nanometers)

As mentioned above, different combinations of feature widths and intervals can be selected by selection The original width and spacing as well as the oxide thickness are obtained. For example, the final dimensions L1, O1, and S1 may satisfy one of the following conditions.

1. L1=O1=S12.L1=O1≠S13.L1≠O1=S14.L1=S1≠O15.L1≠O1≠S1 According to an embodiment of the present invention, the volume conversion ratio (VCR) can also be selected by selecting different The chemical reaction process changes. In one embodiment, the chemical reaction can be an oxidation process or other process that consumes Si to form a second material and reduce the spacing. For example, tantalum nitride can be formed using a tantalum nitride process. In another embodiment, a helium oxynitride process can be used to form bismuth oxynitride (SiON). In certain embodiments, the initial features in FIG. 1 can be formed in polycrystalline germanium, single crystal germanium, undoped germanium, or doped germanium. In other embodiments, the initial features in FIG. 1 can be formed on a metal layer, and the chemical reaction can be a metal silicidation process. In various embodiments, the metal can include platinum, nickel, cobalt, titanium, rhodium, platinum, or molybdenum, and the like. Thus, conventional deuteration processes can be used for selected metals to form metal silicides.

A method of forming a pattern on a substrate according to an embodiment of the present invention can be briefly described as follows.

1. providing a substrate; 2. forming a first layer of a first material overlying the substrate; 3. patterning the first layer of the first material to form a first plurality of a first material feature, the first plurality of first material features each having a sidewall and a top surface; 4. performing a chemical reaction process to convert the first plurality of first material features to form a corresponding plurality of conversion features, each of which is located A first thickness of the first material of the sidewalls of the first plurality of first material features is converted to form a second thickness of the second material, each transition feature comprising a first material region sandwiched between two regions of the second material The two regions of the second material are each characterized by having a second thickness; 5. forming a second layer overlying the conversion features and the first material over the substrate, the second layer of the first material filling adjacent transition features a gap between the second layer and a portion of the first layer and a portion of the transition feature to selectively form a substantially planar structure, the substantially planar structure comprising the second plurality A first material region, the second group being more in number than the first group, the substantially planar structure further comprising a third plurality of second material regions, the third group being more in number than the first group.

The method also includes selecting a pattern using the second plurality of first material regions or the third plurality of second material regions. In a particular embodiment, the method includes removing the second material from the substantially planar structure to form a second plurality of first material features. In another embodiment, the method includes removing the first material from the substantially planar structure to form a third plurality of second material features.

The above described process sequence provides a method of forming a pattern in accordance with an embodiment of the present invention. As shown, this method uses a combination of processes including performing chemical reaction methods and a combination of filling and planarization processes to form features with reduced pattern width and spacing. Some embodiments are discussed above with reference to Figures 1-10. Other alternatives may also be provided, adding processes, removing one or more steps, or changing the order of one or more processes without departing from the scope of the patent application. Further details of the method of the invention can be understood from this description.

12A-12G are simplified cross-sectional views of a method of fabricating an integrated circuit using a patterning method as outlined above, in accordance with an embodiment of the present invention. These drawings are merely examples and should not unduly limit the scope of the patent application herein. Anyone familiar with the art can make other changes, modifications and alternatives. In a particular embodiment, the patterning method is applied in the fabrication of an integrated circuit comprising an array region and a peripheral region. As shown, the left cross-sectional view in each of FIGS. 12A-12G is through the array area and the right cross-sectional view is in the peripheral area. The cross-sectional views are not necessarily drawn to scale, and in particular, the actual dimensions of the same layers or regions in the right and left cross-sectional views may not be the same.

In FIG. 12A, a method of patterning on a substrate includes providing a substrate 1201. In a particular embodiment, the substrate includes an oxide layer 1203 overlying the lower layer 1202. In the example, the lower layer is a tungsten telluride (WSix) or polysilicon (PL) layer, but may include any other material or component structure suitable for use in integrated circuit applications. The method includes forming a first layer of a first material overlying a substrate. As shown, a 100 nm polysilicon layer 1204 is formed in Figure 12A. On the substrate. Next, photoresist layer 1205 is formed and patterned, and is used to pattern polysilicon layer 1204 in FIG. 12B to form a first plurality of polysilicon features 1206. The polysilicon features 1206 each have side and top faces.

In Figure 12C, an oxidation process is performed to convert polycrystalline germanium features to form oxidized polysilicon features. The oxidized polysilicon features each include an oxide layer 1208 overlying the remaining polysilicon features 1207. A second layer of polysilicon 1209 is then formed overlying the oxidized polysilicon features and the substrate and filling the gap between adjacent conversion features. In FIG. 12D, the method includes forming a substantially planar structure using a chemical mechanical polishing process (CMP) to expose the top of the polysilicon layer and the top surface of the oxide layer. Next, in 12E, the array area on the left side is masked by the photoresist layer 1221 while the photoresist layer 1221 of the peripheral area on the right side is selectively patterned. In FIG. 12G, a polysilicon etch is performed to remove the exposed polysilicon in the peripheral region. The photoresist is then removed and an oxide etch is performed. Here, the exposed polysilicon features are used as a hard mask for etching the oxide layer 1203 within the substrate, as shown in Figure 12G.

In an alternate embodiment, the process of Figure 12F is performed immediately following the process in Figure 12D. Here, an oxide CMP or oxide etch back process is performed to expose the top surface of the polysilicon. Then, the array area on the left side is masked by the photoresist layer 1231 while the photoresist layer (1231) of the peripheral area on the right side is selectively patterned. Then, the process associated with FIG. 12G is performed to use the polysilicon feature as a hard mask to etch the oxide layer within the substrate.

As can be seen in Figures 12A-12G, the method of forming a pattern is applied to an integrated circuit process wherein the array area can include a repeating pattern. In a particular embodiment, the pitch of the repeating pattern can be reduced by the method provided by the present invention. small. However, this method is not limited to this pattern. For example, Figure 13 is a simplified top plan view showing a method of forming a pattern in accordance with an embodiment of the present invention. In a particular embodiment, the original features on the left may include the smallest feature sizes used in conventional patterning processes. On the right side, a plurality of features are formed that include a smaller width and spacing than the width and spacing of the original features on the left. As can be seen, the methods provided herein can be used to form features having a smaller width and spacing than the smallest feature size. Additionally, this method can be applied repeatedly to form even smaller feature sizes, spacings, and spacings. Since the critical dimensions are determined by chemical reactions, this method is not limited to the minimum feature size of conventional processes.

Although the preferred embodiments of the present invention have been disclosed above, the present invention is not limited to only these embodiments. Numerous modifications, changes, alterations, substitutions and equivalents may be made without departing from the spirit and scope of the invention.

101‧‧‧Substrate

102‧‧‧Under

103‧‧‧Insulation materials

104‧‧‧Original polysilicon characteristics

204‧‧‧Oxidized polysilicon characteristics

205‧‧‧Oxide

206‧‧‧ Polysilicon characteristics

207‧‧‧Oxide area

208‧‧‧Oxide area

209‧‧‧ gap

210‧‧‧Second layer polysilicon

301‧‧‧ planar structure

1201‧‧‧Substrate

1202‧‧‧Under

1203‧‧‧Oxide layer

1204‧‧‧Polysilicon layer

1205‧‧‧ photoresist layer

1206‧‧‧ Polysilicon characteristics

1207‧‧‧Remaining polysilicon characteristics

1208‧‧‧Oxide layer

1209‧‧‧Polysilicon

1221‧‧‧ photoresist layer

1231‧‧‧Photoresist layer

S1‧‧ interval

O1‧‧‧ thickness

L1‧‧‧Width

1-4 are simplified cross-sectional views of a method of forming small features in an integrated circuit in accordance with an embodiment of the present invention.

Figure 5 is a simplified cross-sectional view of an alternative process of the method depicted in Figures 1-4, in accordance with an embodiment of the present invention.

6-10 are simplified cross-sectional views of another method of forming small features in an integrated circuit in accordance with an embodiment of the present invention.

Figures 11A-11C are simplified diagrams showing the feature sizes achievable in the methods of Figures 1-4 and 6-9, in accordance with an embodiment of the present invention.

12A-12G are simplified cross-sectional views of a method of fabricating an integrated circuit in accordance with an embodiment of the present invention. And Figure 13 is a simplified top plan view showing a pattern formed using a method in accordance with an embodiment of the present invention.

101‧‧‧Substrate

102‧‧‧Under

103‧‧‧Insulation materials

204‧‧‧Oxidized polysilicon characteristics

205‧‧‧Oxide

206‧‧‧ Polysilicon characteristics

207‧‧‧Oxide area

208‧‧‧Oxide area

209‧‧‧ gap

210‧‧‧Second layer polysilicon

S1‧‧ interval

O1‧‧‧ thickness

L1‧‧‧Width

Claims (17)

A method of patterning a material, comprising: patterning a second material over a first material on a substrate, wherein the second material comprises a germanium containing material; converting the patterned first a surface portion of the two materials to form a third material, wherein the third material is located around the remaining patterned second material; selecting the remaining patterned second material and One of the third materials; removing the selection material to form a mask; and patterning the first material using the mask. A method of patterning a material as described in claim 1, wherein the removing step comprises selectively etching the third material or the remaining patterned second material. The method of patterning a material as described in claim 1, further comprising removing a portion of the third material to expose a top surface of the remaining patterned second material. A method of patterning a material as described in claim 3, wherein removing the portion of the third material comprises using a chemical mechanical polishing process. A method of patterning a material as described in claim 3, wherein removing the portion of the third material comprises using an etching process. A method of patterning a material as described in claim 1, wherein the converting step comprises oxidizing the surface portion of the patterned second material. The method of patterning a material as described in claim 1, wherein the converting step comprises an oxidation process, a nitridation process, and a metal tellurization process. At least one of the processes. A method of patterning a material as described in claim 1, wherein the third material comprises at least one of tantalum nitride, hafnium oxide, and metal telluride. A method of patterning a material as described in claim 1, wherein the mask comprises at least one of tantalum, niobium oxide, tantalum nitride, and metal telluride. The method of patterning a material as described in claim 1, further comprising forming a fourth material in at least one gap of the patterned second material. A method of patterning a material as described in claim 10, wherein the second material and the fourth material are substantially the same material. A method of patterning a material, comprising: patterning a first material overlying a substrate, wherein the first material comprises a germanium-containing material; and converting the first portion of the first material to form a plurality of a second material; filling a gap between adjacent second materials using a third material; selecting at least one of the first material, the second material, and the third material; and removing the The material is selected to form a plurality of features and a plurality of spaces. A method of patterning a material as described in claim 12, wherein any one of the features or the intervals is formed by the conversion process, and at least two of the features or two The interval is a predetermined width. The method of patterning a material according to claim 12, wherein the converting step comprises an oxidation process, a nitridation process, and a metal ruthenium. At least one of the processes. The method of patterning a material according to claim 12, wherein the second material comprises at least one of cerium oxide, cerium nitride, and metal cerium. A method of patterning a material as described in claim 12, wherein a selective etching process is used to remove one selected from the first material and the second material. The method of patterning a material as described in claim 12, further comprising forming a substantially planar structure by selectively removing a portion of the first material and a portion of the second material.