TWI426382B - Multidimensional architecture of the transceiver and the bus from the method - Google Patents

Description

Method for separating transceiver from bus under multi-point architecture

The invention provides a method for separating a transceiver from a bus in a multi-point architecture, which is provided with a signal comparator and an error detection controller for detecting and judging in the controller, so as to know that the transceiver or the bus occurs. Errors, and the use of relays that connect or disconnect the bus to the transceiver, so that the bus and transceiver do not interact with each other and continue to operate.

According to the popularity of the Internet and the continuous evolution of technology, enterprises with high traditional human concentration have gradually turned to the use of communication and data transmission between devices to replace a large number of manpower manufacturing methods, the establishment of highly automated equipment, not only The cost of reducing the labor cost of enterprises can also reduce the risk of talent flow. Under the construction of automation equipment, the overall process of production operations is mostly carried out through equipment, but now it is multi-point (Mulitpoint/Multidrop) Network architecture technology as a communication and communication mechanism between devices.

Generally speaking, in a multi-point architecture, enterprises will connect multiple communication devices on all buses to the system through the communication interface, so that multiple communication devices and systems can operate with each other, but in this case, on the system or on the bus. When there is a short circuit or abnormality in one device, the communication of all the multiple communication devices will not work properly.

Please refer to the fifth figure, which is a schematic diagram of a conventional transceiver and bus architecture. It can also be clearly seen that there is a system A under the multi-point architecture, which includes a central processing unit (Central Processing Unit, Referred to as CPU) A1 and Universal Asynchronous Receiver Tranamitter (UART) A2, the central processing unit A1 and the asynchronous receiving transmitter A2 are connected to the bus C through the transceiver B, and the bus has Multiple communication devices C1.

Referring to the sixth figure, it is a schematic diagram of the bus short-circuit condition of the conventional use. It can be clearly seen that there are multiple communication devices C1 on the bus C, wherein when the communication device C11 of the plurality of communication devices C1 is short-circuited, the bus The other complex communication device C12 on C will not be able to operate. Under this structure, it is impossible to know that there is a problem with the communication device C11 of the transceiver B or the bus C. The maintenance personnel must waste extra time to find out that it is a transceiver. B or communication device C11 has failed.

See also the seventh figure, which is a schematic diagram of the bus short circuit caused by the conventional transceiver damage. It can also be clearly seen that there are multiple communication devices C1 on the bus C. When the transceiver B is damaged, not only the bus C will be caused. The abnormal communication device C1 is abnormal, and the communication between the plurality of communication devices C1 cannot be smoothly performed. When the maintenance personnel arrives, it is impossible to clearly know that there is a problem with the transceiver B or the multiple communication device C1 of the bus C is faulty. This takes a lot of time to re-examine each communication device.

In this way, for enterprises whose main production methods are manufactured by machinery and equipment, when the transceiver error affects the bus and the time for checking the wrong device is also quite long, in this case, the mutual influence of the enterprise equipment is caused. The longer the downtime, the more tangible costs and profits will cause losses, and the intangible reputation may not be able to ship smoothly to customers, and the continued cooperation with them will cause difficulties. In today's competitive era, the ontology of the enterprise It will cause great damage.

Therefore, how to solve the above problems and shortcomings in the past is the direction for the relevant manufacturers engaged in this industry to research and improve.

Therefore, in view of the above problems and shortcomings, the inventors have collected relevant information, evaluated and considered through multiple parties, and have been engaged in the multi-point architecture of the multi-point architecture through continuous trial and modification through years of experience in the industry. The method of separating the device from the bus is the birth of the invention patent.

The main purpose of the present invention is to determine whether the data stored by the controller and the data recorded by the transceiver are different through the signal comparator in the controller, and the error detection control in the controller when the data has a difference The device will send a signal to the relay to disconnect the bus from the transceiver. This isolation method will not affect the operation of the various devices on the bus when there is a problem with the transceiver itself.

The secondary object of the present invention is that when the relay is disconnected and the signal comparator in the controller again judges the data stored by the controller and the data recorded by the transceiver, if the judgment is different, the controller transmits an error interrupt. The signal is given to the central processing unit in the system, so that the maintenance personnel can determine that the transceiver has an error. On the other hand, if it is judged to be the same, the controller will still transmit an error interrupt signal to the central processing unit in the system, so that the maintenance personnel It is determined that an error occurs in a device on the bus, so that the maintenance personnel can shorten the time for checking the error and reduce the operational loss caused by the equipment shutdown.

In order to achieve the above objects and effects, the technical means and the configuration of the present invention will be described in detail with reference to the preferred embodiments of the present invention.

Please refer to the first and second figures at the same time, which is a schematic diagram of the transceiver and the bus of the present invention, and a block diagram of the controller. As is clear from the figure, the present invention includes a system 1, a controller (Controller) 2 , the transceiver 3, the relay 4 and the bus 5, wherein: the system 1 is provided with a central processing unit (CPU) 11 and a Universal Asynchronous Receiver Transmitter (UART) 12, and The central processing unit 11 and the asynchronous receiving transmitter 12 are connected to the controller 2, and the controller 2 is provided with a signal comparator 21 and an error detecting controller 22. The controller 2 is further connected with a transceiver 3, and the transceiver 3 The plurality of communication devices 51 are connected to the plurality of communication devices 51 on the bus 5 via the relay 4. The plurality of communication devices 51 include a communication device 511 and a plurality of communication devices 512.

Please refer to the third and fourth figures, which is a flow chart of the transceiver and bus disconnection of the present invention. It can be clearly seen from the figure that the action flow is: (100) start (101) the controller 2 continues to transmit and receive one. The Enable Negative Receiver (ENR) receives a low (Low) signal to the transceiver 3, and the transceiver 3 continuously transmits a data to the asynchronous receive transmitter 12 through the controller 2. (102) The central processing unit 11 in the system 1 selects to transmit a transceiver transmit enable pin (ET) to a high (High) or low (Low) signal to the controller 2, if low, It means that the data does not need to be compared, and then step 101 is performed; if it is high, it means that the data must be compared, and then step 103 is performed.

(103) The central processor transmits the first data to the controller 2 via the asynchronous receiving transmitter 12.

(104) After the first data is stored by the controller 2, a transceiver transmits a high enable signal to the transceiver 3 to transmit the first data to the plurality of communications on the bus 5 via the transceiver 3. The device 51, at the same time, the transceiver 3 transmits the first data of the skid controller 2 to the bus 5 to form the second data, and converts the second data into a format acceptable to the controller 2, and then returns the device to the controller 2 .

(105) The signal comparator 21 in the controller 2 compares the first data stored in the controller 2 with the second data recorded on the side of the transceiver 3. If the data is the same, proceed to step 101; if the data is different, Then proceed to step 106.

(106) The signal comparator 21 transmits an abnormal signal to the error detection controller 22.

(107) The error detection controller 22 transmits a message to cause the switch in the relay 4 to be turned on.

(108) The controller 2 transmits the first data to the transceiver 3 again, after which the transceiver 3 will record and return the second data, and the signal comparator 21 will store the first data stored in the controller 2. Compared with the second data transmitted from the transceiver 3, if the data is different, step 109 is performed; if the data is the same, step 111 is performed.

(109) The error detection controller 22 transmits an error interrupt signal (Fail INT) to the central processing unit 11 in the system 1 to inform the transceiver 3 that a failure has occurred.

(110) The central processing unit 11 notifies the error detection controller 22 in the controller 2 to transmit a signal to the relay 4 to keep the switch open, and then proceeds to step 102.

(111) The error detection controller 22 transmits a signal informing the central processing unit 11 in the system 1 that the bus 5 has failed.

(112) The central processing unit 11 notifies the error detection controller 22 in the controller 2 to transmit a signal to the relay 4 to cause its switch to be turned off.

(113) End.

According to the above steps, the controller 2 continuously transmits a transceiver receiving enable pin (Enable Negative Receiver (ENR) to the transceiver 3 to enable the data to be continuously transmitted from the transceiver 3 to the non-transistor. Synchronously receiving the transmitter 12, and when the central processing unit 11 transmits a transceiver transmit enable pin (ET) to a high (High) signal to the controller 2, it indicates that the data must be correctly or incorrectly determined. In this case, the central processing unit 11 transmits the first data to the controller 2 via the asynchronous receiving transmitter 12, and after the controller 2 stores the data, it transmits a signal that the transceiver transmits the enabling pin high. To the transceiver 3, so that the first data is transmitted to the bus 5 via the transceiver 3. At this time, the first data is recorded by the transceiver 3 to form the second data, and the controller 2 is provided with a comparison data. The signal comparator 21, which is the same as the second data, and the error detection controller 22, which determines whether the transceiver 3 is connected to or disconnected from the bus 5, when the data is found to be different after the comparison, is indicated as an error. The signal comparator 21 transmits a signal to The error detection controller 22 in the controller 2 will further transmit a signal to make the switch of the relay 4 open, and when the relay 4 is turned on, the signal comparator 21 in the controller 2 will judge the controller 2 again. The stored first data is the same as the second data transmitted from the transceiver 3. If the data is the same, the relay 4 will be turned off; when the data is different, the relay 4 will remain open, and then the fault signal will be transmitted to the maintenance personnel. It is made quick to know whether the complex communication device 51 of the bus 5 has an error or the transceiver 3 itself has an error.

Therefore, the method can be used to determine the cause of the error is that the transceiver 3 or the plurality of communication devices 51 on the bus 5 are short-circuited, and the abnormality of the system 1 can also be notified, so that the maintainer only needs to repair the bus for maintenance. 5 of the plurality of communication devices 51 or transceivers 3, without having to check all of the plurality of communication devices 51 and transceivers 3, which will greatly shorten the maintenance time of the maintenance personnel, and the downtime caused by the failure of the machine equipment can also be reduced Therefore, the operational risks of the company can also be reduced.

The above detailed description is intended to be illustrative of a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and other modifications and changes may be made without departing from the spirit of the invention. All should be included in the scope of the patent covered by the present invention.

In summary, the method for separating the transceiver from the bus under the multi-point architecture of the present invention has significant power improvement in use, and is in conformity with the application requirements of the invention patent, and submits an application according to law, and hopes that the trial committee will grant the case as soon as possible to protect The inventor's hard work, if there is any doubt in the bureau, please do not hesitate to give instructions, the inventor will try his best to cooperate, and feel really good.

1. . . system

11. . . CPU

12. . . Asynchronous receive transmitter

2. . . Controller

twenty one. . . Signal comparator

twenty two. . . Error detection controller

3. . . transceiver

4. . . Relay

5. . . bus

51. . . Multiple communication devices

511. . . Communication device

512. . . Complex communication device

A. . . system

A1. . . CPU

A2. . . Asynchronous receive transmitter

B. . . transceiver

C. . . bus

C1. . . Multiple communication devices

C11. . . Communication device

C12. . . Complex communication device

The first figure is a schematic diagram of the transceiver of the present invention being separated from the bus.

The second figure is a block diagram of the controller of the present invention.

The third figure is a flow chart (1) of the transceiver of the present invention and the bus.

The fourth figure is a flow chart (2) of the transceiver of the present invention and the bus.

The fifth diagram is a schematic diagram of a conventional transceiver and bus architecture.

The sixth diagram is a schematic diagram of a conventional bus short circuit condition.

The seventh figure is a schematic diagram of a bus short circuit caused by the conventional transceiver damage.

1. . . system

11. . . CPU

12. . . Asynchronous receive transmitter

2. . . Controller

twenty one. . . Signal comparator

twenty two. . . Error detection controller

3. . . transceiver

4. . . Relay

5. . . bus

51. . . Multiple communication devices

511. . . Communication device

512. . . Complex communication device

Claims (7)

A method for separating a transceiver from a bus in a multi-point architecture, wherein a central processor and an asynchronous receiving transmitter are disposed in the system, and the central processor and the asynchronous receiving transmitter are connected to the transceiver through the controller, and The transceiver is connected to a plurality of devices on the bus through a relay, wherein the controller is provided with a signal comparator for comparing data similarities and differences and an error detection controller for determining whether the bus is connected or disconnected from the transceiver, and the processing steps are as follows: (1) The central processing unit transmits the first data to the controller via the asynchronous receiving transmitter; (2) after the first data is stored in the controller, the transceiver transmits a signal that the transmitting pin is high. To the transceiver, so that the first data is transmitted to the plurality of communication devices on the bus via the transceiver, and the transceiver will record the first data transmitted by the transceiver to the bus, which will form the second data and the second The data is converted into a format acceptable to the controller and then transmitted back to the controller. (3) The signal comparator in the controller stores the first data stored in the controller and the second resource recorded on the transceiver side. For comparison, when the signal comparator determines that the first data and the second data are different, the signal comparator transmits an abnormal signal to the error detection controller; and (4) the error detection controller transmits a message to enable the relay The switch is turned on to disconnect the bus from the transceiver. The transceiver is disconnected from the bus in the multipoint architecture as described in claim 1 The method, wherein the controller continuously transmits a transceiver to receive an Enable Negative Receiver (ENR) signal to the transceiver, and the transceiver continuously transmits data to the asynchronous receiving device through the controller. Transmitter. The method for separating a transceiver from a bus in a multipoint architecture as described in claim 1, wherein the central processor transmits a transceiver transmit enable pin (ET) to a high signal. When the controller is in use, the central processor transmits the first data to the controller via the asynchronous receiving transmitter. The method for separating a transceiver from a bus in a multi-point architecture according to claim 3, wherein the first processor does not transmit a transceiver transmit enable pin to a controller. Transfer to the controller via the asynchronous receive transmitter. The method for separating a transceiver from a bus in a multi-point architecture according to claim 1, wherein the signal comparator in the controller determines the first data stored in the controller and the second data recorded on the transceiver side If they are the same, it means that the communication device on the transceiver or bus is not damaged. The method for separating a transceiver from a bus in a multi-point architecture according to the first aspect of the patent application, wherein when the transceiver is disconnected from the bus, the controller transmits the first data to the transceiver again, and the transceiver Recording and returning the second data, if the signal comparator determines that the first data stored in the controller is different from the second data transmitted from the transceiver, the error detection controller transmits a notification The transceiver has a fault signal to the central processor and keeps the transceiver disconnected from the bus. The method for separating a transceiver from a bus in a multi-point architecture according to claim 6, wherein the signal comparator determines that the first data stored in the controller is the same as the second data transmitted from the transceiver. The error detection controller transmits a signal indicating that the plurality of communication devices on the bus have failed to the central processing unit and causes the transceiver to resume connection with the bus.