TWI425755B - Pwm buck converter with surge reduction and related method - Google Patents

Description

Pulse width modulation buck converter capable of mitigating power surge and related method

The present invention relates to an electronic device, and more particularly to a pulse width modulated buck converter and related method for mitigating power supply surge.

The pulse width modulation buck converter is a DC-to-DC voltage converter that steps down the input DC voltage to a predetermined voltage level to provide a stable operating voltage to the peripheral components. The pulse width modulated buck converter can be used in a power supply to provide a stable operating voltage for each component in the power supply to maintain a stable supply voltage, current or electrical energy supply.

Please refer to FIG. 1 , which is a schematic diagram of a conventional pulse width modulated buck converter 10 . The pulse width modulated buck converter 10 includes an output stage circuit unit 100, a feedback unit 110, and a comparator 120. The output stage circuit unit 100 operates on a power supply voltage V _IN and includes a transistor upper level switch 102, a transistor lower level switch 104, an inductor 106 and a voltage dividing circuit 108, and the feedback unit 110 includes an error. The amplifier 112 and a compensation line 114. The comparator 120 is configured to compare the error signal V _ERR and the slope (RAMP) signal V _{RAMP of the} compensation line 114 to generate a pulse width modulation signal V _PWM . The pulse width modulation signal V _PWM can control the on/off state of the transistor upper switch 102 and the transistor lower switch 104 to further control the energy storage and release energy of the inductor 106. Then, when the output voltage V _{out of} the inductor 106 via pressure points dividing circuit 108 generates a feedback voltage V _FB, which is fed back to the input terminal of the error amplifier 112. After the error amplifier 112 compares the feedback voltage V _FB with the reference voltage V _REF , the generated signal is again subjected to signal compensation through the compensation line 114 to obtain the error signal V _ERR again. Pulse width modulation step-down converter 10 according to the above permeable feedback mode to maintain the stability of the output voltage V _out.

Please refer to FIG. 2, which is a schematic diagram showing waveforms of voltages and currents of respective components in the pulse width modulation buck converter 10. When the power supply voltage V _{IN is} higher than a shutdown threshold voltage V _POR , the transistor upper switch 102 , the transistor lower switch 104 , the ramp signal V _RAMP , the error voltage V _ERR and the inductor 106 current according to the working principle described in FIG. 1 , A stable cycle state is formed, in other words, the pulse width modulation buck converter 10 operates in the normal mode. However, when the power supply voltage V _in drops to the shutdown threshold voltage V _POR , the electronic device to which the pulse width modulation buck converter 10 belongs enters the shutdown mode, and the upper transistor switch 102 and the lower transistor switch 104 are simultaneously turned off, resulting in The output inductor current I _{L of the} inductor 108 then drops to zero. Such a phenomenon causes the power supply voltage V _{IN to} instantaneously bounce and form a surge 202 on the power supply voltage V _IN . For the entire power circuit, the surge 202 is liable to cause malfunction of the entire system. Therefore, how to overcome the problem of the surge 202 when the electronic device is turned off is an important issue.

Therefore, the object of the present invention is to disclose a pulse width modulation buck converter capable of slowing the power surge to prevent the power supply voltage when an electronic device to which the pulse width modulation buck converter belongs enters the shutdown mode. The phenomenon of glitch is generated, thereby preventing other components in the electronic device from being damaged by the glitch.

The invention provides a pulse width modulation (PWM) step-down converter capable of mitigating a power surge, comprising a compensation circuit, a waveform adjuster, a comparator, an output and a circuit unit and a back Grant unit. The compensation circuit is configured to generate a first signal according to an error signal and a pulse width modulation one of the power supply voltages of the buck converter. The waveform adjuster is configured to change a period of the falling waveform portion of the one-cycle signal according to the power supply voltage to generate a second signal. The comparator is configured to compare the first signal with the second signal to generate a pulse width modulation signal. The output stage circuit unit is configured to generate a feedback signal according to the pulse width modulation signal. The feedback unit is configured to generate the error signal according to the feedback signal.

The invention further provides a method for mitigating a power surge, which is used in a pulse width modulation (PWM) step-down converter, the method comprising: adjusting the voltage according to an error signal and the pulse width. a power supply voltage of the converter, generating a first signal; changing a period of the falling waveform portion of the one-cycle signal according to the power supply voltage to generate a second signal; comparing the first signal with the second signal to generate a a pulse width modulation signal; generating a feedback signal according to the pulse width modulation signal; and comparing a reference voltage and the feedback signal to generate the error signal.

Please refer to FIG. 3, which is a schematic diagram of a pulse width modulated buck converter 30 that can mitigate power supply surges according to an embodiment of the present invention. The pulse width modulation controller 30 includes an output stage circuit unit 300, a feedback unit 310, a comparator 320, a compensation circuit 330, and a waveform adjuster 340. The operation principle of the output stage circuit unit 300 and the feedback unit 310 is the same as that of the output stage circuit unit 100 and the feedback unit 110 in FIG. 1 , and details are not described herein. The compensation circuit 330 is configured to generate a first signal V _ERR1 according to one of the error signal V _ERR generated by the feedback unit 310 and a power supply voltage V _IN1 . The pulse width modulation buck converter 30 can determine whether it is necessary to enter the shutdown according to a shutdown threshold voltage V _POR . In this case, when the power supply voltage V _{IN1 is} greater than the shutdown threshold voltage V _POR , the compensation circuit 330 generates the first signal V _ERR1 that is the same as the error signal V _ERR . Correspondingly, when the power supply voltage V _IN1 drops to the shutdown threshold voltage V _POR , the voltage of the first signal V _ERR1 generated by the compensation circuit 330 is locked at the error signal V _ERR at the power supply voltage V _{IN1 is the} same as the shutdown threshold voltage V _{POR .} The voltage level at that time, after the power supply voltage V _{IN1 is} less than the shutdown threshold voltage V _POR , remains at the same voltage level and does not change with the change of the error signal V _ERR . The waveform adjuster 340 is configured to change a period of a falling waveform portion of a ramp-shaped periodic signal (hereinafter referred to as a ramp signal V _RAMP ) according to the power supply voltage V _IN1 to generate a second signal V _RAMP1 . More specifically, when the power supply voltage V _{IN1 is} higher than the shutdown threshold voltage V _POR , the waveform adjuster 340 maintains the second signal V _RAMP1 and the ramp signal V _RAMP . When the power supply voltage V _IN1 falls to the shutdown threshold voltage V _POR , the waveform adjuster 340 changes the period of the falling waveform portion of the ramp signal V _RAMP to generate the second signal V _RAMP1 . The pulse width modulation comparator 320 is configured to generate a pulse width adjustment signal V _PWM1 according to the first signal V _ERR1 and the second signal V _RAMP1 , thereby controlling the transistor upper switch 302 and the transistor lower position in the output stage circuit unit 300 . The on/off state of switch 304, in turn, controls the energy storage and release of inductor 306.

Please refer to Figure 4. FIG. 4 is a schematic diagram showing waveforms of voltages and currents of respective components of the pulse width modulation buck converter 30 according to the embodiment of the present invention. When the power supply voltage V _{IN1 is} higher than the shutdown threshold voltage V _POR , the transistor upper switch 302 , the transistor lower switch 304 , the ramp signal V _RAMP1 , the error voltage V _ERR1 and the inductor 306 current are in a stable cycle state, and the pulse width is adjusted to decrease. The voltage converter 30 operates normally. However, when the power supply voltage V _IN1 falls to the shutdown threshold voltage V _POR , the pulse width modulation buck converter 30 enters a state ready to be turned off, and the compensation circuit 330 maintains the first signal V _ERR1 at a voltage value, and the waveform adjuster 340 generates a second signal V _{RAMP1 in} which the falling waveform portion is gradually elongated. Then, by comparing the first signal V _ERR1 and the second signal V _RAMP1 , the comparator 320 generates a pulse width adjustment signal V _PWM1 that can gradually lengthen the on-time of the transistor upper switch 302 and the off time of the transistor lower switch 304. At this time, the output inductor current I _L1 generated by the inductor 306 also gradually decreases correspondingly, thereby slowing the surge phenomenon of the power supply voltage V _IN1 .

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a compensation circuit 330 according to an embodiment of the present invention. The compensation circuit 330 includes a first switching unit 500, a second switching unit 502, a third switching unit 504, an inverter 506, and a capacitor C _COMP . The principle and structure of the first switching unit 500, the second switching unit 502, and the third switching unit 504 are the same. When the power supply voltage V _IN is higher than the shutdown threshold voltage V _POR , the input terminal PASS voltage of the first switching unit 500 and the second switching unit 502 is set to a high level, and the input terminal PASS voltage of the third switching unit 504 is The relationship of an inverter 506 is at a low level. In this case, the first switching unit 500 and the second switching unit 502 are in an on state, and the output voltages of the two terminals are equal to the voltage COMP of the input terminals IN (ie, the voltage of the error signal V _ERR ), and the third The switch unit 504 turns off its output terminal OUT and the input terminal IN. Therefore, the voltage of the output terminal OUT of the first switching unit 500 stores the capacitor C _COMP to the input terminal IN of the first switching unit 500, that is, the voltage of the error signal V _ERR , and the voltage COMPO of the output terminal OUT of the second switching unit 502 (ie, the voltage of the first signal V _ERR1 ) will be equal to the voltage of the error signal V _ERR .

More particularly, when the power supply voltage V _IN drops to the shutdown threshold voltage V _POR, pulse width modulation step-down converter 30 into a state ready shutdown, the input terminal of the first switching unit and second switching unit PASS 500 502 The voltage is set to a low level, and the input PASS of the third switching unit 504 becomes a high level. Therefore, the output terminal OUT and the input terminal IN of the first switching unit 500 and the second switching unit 502 are both in an off state, and the third switching unit 504 is in an on state. Since the previous capacitor C _COMP has been charged to the voltage of the error signal V _ERR , when the capacitor C _{COMP is} discharged to the IN input of the third switching unit 504, the voltage COMPO of the output terminal OUT of the third switching unit 504 is converted into an error signal. V _ERR voltage. By using a capacitor C _COMP with a large capacitance value, the voltage COMPO can maintain the voltage of the error signal V _ERR for a period of time. It can be seen from the above that when the power supply voltage V _{IN1 is} higher than the shutdown critical point voltage V _POR , the COMPO voltage at the output end of the compensation line 330 (ie, the voltage of the first signal V _ERR1 ) fluctuates with the voltage of the error signal V _ERR ; when the power supply voltage V _{When IN1} drops to the shutdown critical point voltage V _POR and after, the output COMPO voltage can be maintained at a stable voltage.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of a second switch unit 502 according to an embodiment of the present invention. The second switching unit 502 includes a P-type transistor 600, an N-type transistor 602, and an inverter 604. When the input terminal PASS voltage is at a high level, the P-type transistor 600 is turned on with the N-type transistor 602, and therefore, the output terminal OUT of the second switching unit 502 and the input terminal IN are in an on state; correspondingly, when the input terminal When the PASS voltage is at a low level, both the P-type transistor 600 and the N-type transistor 602 are turned off, and therefore, the output terminal OUT of the second switching unit 502 is disconnected from the input terminal IN. It should be noted that the above embodiment is merely an example of one of the switching units of the present invention, and the switching unit includes a first switching unit 500, a second switching unit 502, and a third switching unit 504. Those skilled in the art can appropriately modify them according to actual needs without being limited thereto. For example, the switching mode can be implemented using other kinds of circuit components, and the related operations are similar to the above embodiments, and are not described herein.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of a waveform adjuster 340 according to an embodiment of the present invention. The waveform adjuster 340 includes a comparison unit 700, a current regulator 710, and switches S ₁ , S ₂ . The comparison unit 700 has an input terminal IN ₁ that receives an upper threshold voltage V _H or a lower threshold voltage V _L and another input terminal IN ₂ for switching the current regulator 710 through the switching of the switches S ₁ and S ₂ . A ramp signal V _RAMP1 is generated. Please note that the input signal of the input terminal IN ₂ is not limited to the ramp signal, but also a sawtooth wave signal and the like. The comparing unit 700 is configured to compare the second signal V _RAMP1 with the upper threshold voltage V _H or the second signal V _RAMP1 and the lower threshold voltage V _L to generate a clock signal OSC_OUT. In addition, the clock signal OSC_OUT is fed back to the current regulator 710 to control the waveform generating operation of the second signal V _RAMP1 . The current regulator 710 includes a fixed current source CS ₁ , a variable current source CS ₂ , an energy storage switch S ₃ , an inverter 712 , a release switch S _{4 ,} and a capacitor C _RAMP1 . The fixed current source CS ₁ and the variable current source CS ₂ are respectively used to provide a capacitor C _{RAMP1 -} a storage current I _CHAR1 and a _discharge current I _DIS1 . The energy storage switch S _{3 is} controlled by the clock signal OSC_OUT, and the release switch S _{4 is} controlled by the inverted clock signal OSC_OUT _{INV which} inverts the clock signal OSC_OUT through the inverter 712. The capacitor C _{RAMP1 is} stored by the energy storage switch S ₃ with the storage current I _CHAR1 , and is discharged by the release switch S ₄ with the release current I _DIS1 to generate the second signal V _RAMP1 . In the current regulator 710, when the power supply voltage V _IN drops to the shutdown threshold voltage V _POR , the variable current source CS _{2 is} used to reduce the _discharge current I _DIS1 according to the power supply voltage V _IN . Since the period of the falling waveform portion of the second signal V _RAMP1 is inversely proportional to the _discharge current I _DIS1 , when the release current I _{DIS1 is} smaller, the period of the falling waveform portion of the second signal V _RAMP1 is extended.

Please refer to FIG. 8. FIG. 8 is a schematic diagram of a waveform adjuster 340 according to another embodiment of the present invention. The waveform adjuster 340 includes a transimpedance amplifier 800, a capacitor C _RAMP2 , a storage current I _CHAR2 and a _discharge current I _DIS2 . Wherein the capacitance C _RAMP2, the tank current and discharging current I _CHAR2 I _DIS2 effect reference capacitor C _RAMP1 respectively of FIG. 7, the tank current and the discharging current I _CHAR1 I _DIS1. In the transimpedance amplifier 800, a total current I _TOTAL is a fixed current and is a sum of a minute current I ₁ and a minute current I ₂ . The divided current I ₁ and the divided current I ₂ flow through the transistors Q ₁ and Q ₂ , respectively, and the switches of the transistors Q ₁ and Q ₂ are controlled by an operating voltage V _IN2 and a comparison voltage V _A . The operating voltage V _IN2 is in a specific proportional relationship with the power supply voltage V _IN1 . When the operating voltage V _{IN2 is} greater than or equal to the comparison voltage V _A , the values of the divided current I ₁ and the divided current I ₂ are fixed, and the release current I _DIS2 is the mirror current of the divided current I ₂ , therefore, the divided current I _{2 is} equivalent to the release current I _DIS2 . However, when the operating voltage V _IN2 falls to the comparison voltage V _A , part of the divided current I ₂ flows to the divided current I ₁ according to the ratio of the operating voltage VI _N2 to the comparison voltage V _A . In this way, the divided current I ₂ is reduced, so that the _discharge current I _{DIS2 is} reduced, and the effect of adjusting the release current I _DIS2 is achieved. Therefore, the _discharge current I _DIS2 can thereby control the capacitor C _RAMP2 to output the second signal V _RAMP1 whose period of the falling waveform portion is extended. In this embodiment, a person skilled in the art can adjust the working voltage V _IN2 and the comparison voltage V _{A to} reduce the operating voltage V _IN2 to the comparison voltage V _A , that is, the power supply voltage V _IN1 drops to the shutdown critical point voltage. The moment of V _POR .

In summary, the compensation circuit 330 and the waveform adjuster 340 in the embodiment of the present invention are used to avoid the phenomenon that the power supply voltage generates a glitch when the pulse width modulation buck converter enters the shutdown mode, thereby avoiding the electronic device. Other components are subject to surge damage.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, 30. . . Pulse width modulated buck converter

100, 300. . . Output stage circuit unit

102, 302. . . Transistor upper switch

104, 304. . . Transistor lower switch

106, 306. . . inductance

108. . . Voltage dividing circuit

110, 310. . . Feedback unit

112, 312. . . Error amplifier

114, 314. . . Compensation line

120, 320. . . Comparators

330. . . Compensation circuit

340. . . Waveform adjuster

500. . . First switch unit

502. . . Second switching unit

504. . . Third switch unit

506. . . inverter

600. . . P-type transistor

602. . . N type transistor

604. . . inverter

700. . . Comparison unit

710. . . Current regulator

800. . . Transimpedance amplifier

C _RAMP1 , C _RAMP2 . . . capacitance

CS ₁ . . . Fixed current source

CS ₂ . . . Variable current source

I ₁ , I ₂ . . . Current sharing

I _CHAR1 , I _CHAR2 . . . Energy storage current

I _DIS1 , I _DIS2 . . . Release current

I _TOTAL . . . Total current

Q ₁ , Q ₂ . . . Transistor

IN, PASS. . . Input

IN ₁ , IN ₂ . . . Input

OUT. . . Output

S ₁ , S ₂ , S ₃ , S ₄ . . . switch

V _A . . . Comparison voltage

V _DD . . . power source

V _ERR . . . Error signal

V _ERR1 . . . First signal

V _H . . . Upper threshold voltage

V _IN , V _IN1 . . . voltage

V _IN2 . . . Operating Voltage

V _L . . . Lower threshold voltage

V _POR . . . Shutdown threshold voltage

V _RAMP . . . Slope signal

V _RAMP1 . . . Second signal

V _PWM , V _PWM1 . . . Pulse width adjustment signal

V _out , V _out1 . . . The output voltage

I _out , I _out1 . . . Output load current

Figure 1 is a schematic diagram of a conventional pulse width modulated buck converter.

Figure 2 is a schematic diagram of the relationship between voltage and current of each component.

FIG. 3 is a schematic diagram of a pulse width modulated buck converter with a power supply spurt for mitigating power surges according to an embodiment of the present invention.

Figure 4 is a schematic diagram showing the relationship between voltage and current of each component in the first embodiment of the present invention.

FIG. 5 is a schematic diagram of a compensation circuit according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a second switching unit according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a waveform adjuster according to an embodiment of the present invention.

Figure 8 is a schematic diagram of a waveform adjuster according to another embodiment of the present invention.

30. . . Pulse width modulated buck converter

300. . . Output stage circuit unit

302. . . Transistor upper switch

304. . . Transistor lower switch

306. . . inductance

310. . . Feedback unit

312. . . Error amplifier

314. . . Compensation line

320. . . Comparators

330. . . Compensation circuit

340. . . Waveform adjuster

V _IN1 . . . voltage

V _ERR . . . Error signal

V _ERR1 . . . First signal

V _POR . . . Shutdown threshold voltage

V _RAMP . . . Slope signal

V _RAMP1 . . . Second signal

V _PWM1 . . . Pulse width adjustment signal

V _out1 . . . The output voltage

I _out1 . . . Output load current

Claims (10)

A pulse width modulation (PWM) step-down converter capable of mitigating power surges includes: a compensation circuit for generating a first signal according to an error signal, a shutdown threshold voltage, and a power supply voltage a waveform adjuster receiving the power supply voltage, a ramp signal, and the shutdown threshold voltage to generate a second signal; a comparator comparing the first signal and the second signal to generate a pulse width modulation a change signal unit; an output stage circuit unit generates a feedback signal according to the pulse width modulation signal; and a feedback unit that generates the error signal according to the feedback signal. The pulse width modulation buck converter of claim 1, wherein the compensation circuit generates a first signal equal to the error signal when the power supply voltage is higher than the shutdown threshold voltage, and the power supply voltage drops to the shutdown At the threshold voltage, the voltage of the first signal is maintained at the voltage of the error signal. The pulse width modulation buck converter of claim 1, wherein the waveform adjuster elongates a period of the falling waveform portion of the periodic signal when the power supply voltage drops to the shutdown threshold voltage. The pulse width modulation buck converter of claim 1, wherein the compensation circuit comprises: a capacitor; a first switching unit configured to couple the error signal when the power supply voltage is higher than the shutdown threshold voltage The capacitor is configured to store the capacitor to the error signal, and when the power supply voltage drops to the shutdown threshold voltage, disconnect the error signal from the capacitor to store the capacitor to the error signal; a second switching unit configured to output the first signal by the error signal when the power supply voltage is higher than the shutdown threshold voltage; and a third switching unit configured to when the power supply voltage is higher than the shutdown threshold voltage The coupling between the first signal and the capacitor is disconnected, and when the power voltage drops to the shutdown threshold voltage, the coupling between the first signal and the capacitor is disconnected. The pulse width modulation buck converter of claim 1, wherein the waveform adjuster comprises: a capacitor for generating a discharge current to output the second signal; and a transimpedance amplifier for When the power supply voltage drops to the shutdown threshold voltage, the release current is reduced to lengthen the period of the falling waveform portion of the second signal. The pulse width modulation buck converter of claim 1, wherein the output stage circuit unit comprises: a transistor upper switch for turning on or off according to the pulse width modulation signal; a transistor lower level switch for modulating a signal according to the pulse width, turning on or off; an inductor coupled to the transistor upper level switch and the transistor lower level switch; and a voltage dividing circuit for dividing the voltage The output voltage of the inductor is used to generate the feedback signal. The pulse width modulation buck converter of claim 1, wherein the feedback unit comprises: an error amplifier for comparing a reference voltage and the feedback signal to generate an error amplifier output signal; and a compensation circuit And used to generate the error signal according to the error amplifier output signal. A method for mitigating a power surge is used in a pulse width modulation (PWM) step-down converter, the method comprising: generating according to an error signal, a shutdown threshold voltage, and a power voltage a first signal; generating a second signal according to the power voltage, a ramp signal, and the shutdown threshold voltage; comparing the first signal with the second signal to generate a pulse width modulation signal; The width modulation signal generates a feedback signal; and compares a reference voltage with the feedback signal to generate the error signal. The method of claim 8, wherein generating a first signal according to an error signal, a shutdown threshold voltage, and a power supply voltage comprises: generating a first signal equal to the error signal when the power supply voltage is higher than the shutdown threshold voltage Signal; and When the power supply voltage drops to the shutdown threshold voltage, the voltage of the first signal is maintained at the voltage of the error signal. The method of claim 8, wherein generating a second signal according to the power supply voltage, a ramp signal, and the shutdown threshold voltage comprises: extending the falling waveform portion of the periodic signal when the power supply voltage drops to the shutdown threshold voltage Cycle to generate the second signal.