TWI425521B - Method of forming bit line - Google Patents

Description

Bit line manufacturing method

The present invention relates to a method of fabricating a dynamic random access memory cell, and more particularly to a method of fabricating a bit line of a dynamic random access memory cell.

Dynamic Random Access Memory (DRAM) belongs to a kind of volatile memory. The main principle of operation is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0 to store data. To achieve high density requirements, the most effective method at present is to reduce the size of the wafer by reducing the manufacturing process and using cell design techniques. Another way to reduce the size of the wafer is to implement a more efficient array architecture. After several generations of development, storage techniques often become a limitation of a certain cell layout. Every improvement in cell size requires a lot of work to reduce etching. The smallest size.

Therefore, there is a need for a method of fabricating a dynamic random access memory having a novel structure.

In view of the above, an embodiment of the present invention provides a method for fabricating a bit line, comprising: providing a substrate; forming a trench in the substrate; forming a bottom insulation on the sidewall and the bottom surface of the lower portion of the trench; a pad layer; a top insulating pad layer is formed on the sidewall of the upper portion of the trench; a barrier layer is formed on the sidewall of the trench, and a portion of the top insulating pad layer and the bottom insulating pad layer are covered: Forming a first hard mask layer in the trench and covering a portion of the barrier layer; conforming to forming a barrier layer of a lower layer and a second hard mask layer of an upper layer in the trench, and covering the foregoing a hard mask layer; an opening is formed in the barrier layer and the second hard mask layer to expose a portion of the first hard mask layer and a portion of the barrier layer on a side of the trench; a portion of the barrier layer covered by the barrier layer and the second hard mask layer; removing the second hard mask layer; simultaneously removing the barrier layer, the first hard mask layer, and the barrier layer Covering the above bottom Cushion edge, to expose the sidewalls of the groove portion; of the substrate adjacent to said trench sidewalls in the exposed regions to form a diffusion; a conductive plug is formed, and covering the diffusion region to the trench sidewalls.

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

Fig. 1 is a perspective view showing a dynamic random access memory cell (hereinafter referred to as DRAM cell) 600 according to an embodiment of the present invention. In an embodiment of the invention, the DRAM 600 has a cell size of 4F2 (where F is the minimum lithography process size, or cell size). As shown in FIG. 1, a vertical transistor 300, a buried bit line (BL) 500, and a word line (WL) 308 of the DRAM cell 600 are disposed in a substrate 200. . As shown in FIG. 1, the DRAM cell 600 includes a substrate 200. A vertical transistor 300 is formed in the substrate 200. The vertical transistor 300 has a vertically stacked lower layer drain region 314, an intermediate layer channel region 316, and an upper layer source region 318. Additionally, vertical transistor 300 has at least one vertical sidewall 302. A word line 308 is formed in the substrate 200 along a first direction 322, wherein the word line 308 is disposed on the vertical sidewall 302 of the vertical transistor 300 and serves as a gate of the vertical transistor 300. An insulating layer 306 is disposed between the word line 308 and the vertical transistor 300 to serve as a gate insulating layer of the vertical transistor 300. As shown in FIG. 1, the DRAM cell 600 further includes a bit line 500 formed in a trench 202 in the substrate 200 along a second direction 320 different from the first direction 322, and located in the vertical transistor 300. Bottom, and electrically contacting the drain region 314 of the pair of vertical transistors 300 by a diffusion region 230 formed in a portion of the substrate 200 adjacent to the sidewall of the trench 202. In addition, the DRAM cell 600 further includes a capacitor 312 electrically contacting the source region 318 of the vertical transistor 300.

Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1 showing a cross-sectional view of a bit line 500 of a DRAM cell 600 according to an embodiment of the present invention. In an embodiment of the invention, the bit line 500 is a buried bit line. As shown in FIG. 2, the buried bit line 500 includes a bottom insulating pad layer 208 covering the bottom surface 204 and a portion of the sidewall 206a of the trench 202; a diffusion layer 230 formed on a portion of the sidewall 226 of the trench 202; A conductive plug 220 is formed in the trench 202 to cover the insulating pad layer 208 and adjacent the sidewall of the diffusion layer 230.

3 to 12 are schematic cross-sectional views showing a method of manufacturing the bit line 500 of the dynamic random access memory (DRAM) according to the embodiment of the present invention as shown in Fig. 2. As shown in FIG. 3, first, a substrate 200 is provided. In an embodiment of the invention, the substrate 200 can be a germanium substrate. In other embodiments, silicon germanium (SiGe), bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI), Or other commonly used semiconductor substrates are used as the substrate 200. The substrate 200 can be implanted with a p-type or n-type dopant to change its conductivity type for design needs. In an embodiment of the invention, the substrate 200 can be implanted with a p-type dopant.

As further shown in FIG. 3, a patterned hard mask layer 201 is then formed on the substrate 200 by a deposition and patterning process, and the formation locations of the trenches 202 are defined. In an embodiment of the invention, the patterned hard mask layer 201 may include a stacked structure formed of a lower layer of a hafnium oxide underlayer and an upper layer of tantalum nitride. Then, the patterned hard mask layer 201 and the photoresist pattern can be used as an etch hard mask layer to perform an anisotropic etching process to remove the unmasked hard mask layer 201. A portion of the substrate 200 is formed to form a trench 202 in the substrate 200.

Thereafter, a deposition method such as a chemical vapor deposition (CVD) method, a low pressure chemical vapor deposition (LPCVD) method, or a high temperature oxidation deposition (HTP) method may be used to form a conformance on the sidewall 206 and the bottom surface 204 of the trench 202. The first insulating mat. In an embodiment of the invention, the first insulating pad layer may include an oxide layer, a nitride layer, or a combination thereof. In this embodiment, the insulating mat layer 208 may be an oxide layer formed using a furnace control.

Then, a conductive material can be formed by a chemical vapor deposition (CVD) deposition method and filled into the trenches 202. In an embodiment of the invention, the electrically conductive material may comprise, for example, polycrystalline germanium. Thereafter, an electrically conductive material over the substrate 200 and partially in the trench 202 may be removed using an etching back process to form a conductive layer 210 in the trench 202, wherein the conductive layer 210 covers the bottom surface of the trench 202. 204 and lower sidewall 206a, and the top surface thereof is lower than the surface of the substrate 200.

Then, the conductive layer 210 is used as an etch hard mask, and a wet etching process is performed to remove the first insulating pad layer not covered by the conductive layer 210, and a bottom portion is formed on the sidewall 206a and the bottom surface 204 of the lower portion of the trench 202. Insulating mat 208.

Then, a second insulating underlayer may be formed by using a deposition method such as a chemical vapor deposition (CVD) method, a low pressure chemical vapor deposition (LPCVD) method, or a high temperature oxidation deposition (HTP) method, and covering the trench 202. Upper sidewall 206b and conductive layer 210. In an embodiment of the invention, the second insulating pad layer may be a nitride layer. Thereafter, a second insulating pad layer and a portion of the conductive layer 210 above the substrate 200 and partially on the conductive layer 210 may be removed by an etching back process to form a top insulating pad on the upper sidewall 206b of the trench 202. Layer 212, while the top surface of conductive layer 210 is lower than bottom insulating layer 208. In the present embodiment, the top insulating pad layer 212 is a stacked structure including an oxide layer 212a and a nitride layer 212b as shown in FIG. In addition, the bottom insulating pad layer 208 and the top insulating pad layer 212 are adjacent to each other.

Next, a barrier layer 214 can be formed by a deposition method such as atomic layer deposition (ALD), and the top insulating pad layer 212, the bottom insulating pad layer 208, and the conductive layer 210 can be covered. In the present embodiment, the barrier layer 214 may be titanium nitride (TiN). Then, a first hard mask layer 216 may be formed in the trench 202 and covered with a portion of the barrier layer 214 by a deposition method such as a chemical vapor deposition (CVD) method and a subsequent etching back process. In an embodiment of the invention, the first hard mask layer 216 may comprise an insulating material of an oxide. Thereafter, the first hard mask layer 216 can be used as an etch hard mask to perform a dry etching process to remove the barrier layer 214 not covered by the first hard mask layer 216, so that the etched barrier layer 214 is removed. It is formed on the sidewall of the trench 202 and covers a portion of the top insulating pad layer 212 and the bottom insulating pad layer 208. As shown in FIG. 3, the top surfaces of the first hard mask layer 216 and the barrier layer 214 are both lower than the top surface of the patterned hard mask layer 201.

Next, referring to FIG. 4, a barrier layer 240 can be formed by the deposition method of the low pressure chemical vapor deposition (LP-CVD) method, and the top insulating layer 212, the first hard mask layer 216, and the top insulating layer 212 are formed. Barrier layer 214. In an embodiment of the invention, the barrier layer 240 may comprise an insulating material of oxide, the thickness of which may be between 10 To 100 between.

Then, referring to FIG. 5, a second hard mask layer 242 is formed in the trench 202 by the deposition method of the chemical vapor deposition (CVD) method, and the barrier layer 240 is covered. In an embodiment of the invention, the second hard mask layer 242 and the barrier layer 240 are made of different materials, and the second hard mask layer 242 is, for example, an undoped amorphous silicon insulating material. In an embodiment of the invention, the thickness of the second hard mask layer 242 is greater than the thickness of the barrier layer 240.

Then, referring to FIG. 6, the second hard mask layer 242 can be subjected to an ion implantation step 262 in one direction (ie, the direction of the arrow of the symbol 262). As shown in Fig. 6, since the direction of the ion implantation step 262 (i.e., the direction of the arrow of the symbol 262) has an angle a with the surface of the substrate 200, the value may be determined by the position or size of the subsequent diffusion region, for example, Between 10 ° ~ 80 °. Therefore, the ion implantation step 262 can form a doped region 242a and an undoped region 242b on the second hard mask layer 242. In an embodiment of the invention, the dopant of ion implantation step 262 can be boron difluoride (BF ₂ ).

Next, referring to FIG. 7, a second wet etching process may be performed on the second hard mask layer 242 by using ammonia as an etchant, and a portion of the doped region 242a and the undoped region 242b are removed. A portion of the barrier layer 240 is exposed. During the first wet etching process, the doping region 242a having the dopant as shown in FIG. 7 may have an etching rate lower than that of the non-doped region 242b having no dopant, and the two have an etching selectivity ratio with each other, so When the undoped region 242b is completely removed, a portion of the doped region 242a remains.

Then, a suitable etchant can be selected, for example, hydrofluoric acid (DHF) can be used as an etchant, so that the barrier layer 240 has a higher etch rate (with a good etching selectivity ratio) than the doped region 242a to perform a second The wet etching process removes the barrier layer 240 covered by the undoped region 242a to form an opening 246 in the second hard mask layer 242 and the barrier layer 240, and exposes a portion of the first hard mask layer 216 and is located in the trench A portion of the barrier layer 214 on one side of the trench 202. In an embodiment of the invention, the location of the opening 246 may determine the location at which the diffusion region is subsequently formed. In an embodiment of the present invention, since the barrier layer 240 and the first hard mask layer 216 under it may be the same material, such as an oxide, the opening portion 246 is also removed when the barrier layer 240 is removed. A hard mask layer 216 is formed in the first hard mask layer 216 to form a recess 247 and expose a sidewall of the portion of the barrier layer 214.

Next, please refer to FIG. 8. A suitable etchant can be selected. For example, hydrogen peroxide (H ₂ O ₂ ) and sulfuric acid (H ₂ SO 4 ) can be used as an etching solution, so that the barrier layer 214 has a more doped region 242 and the first layer. The hard mask layer 216 has a high etch rate (having a good etch selectivity) for performing a third wet etch process to remove portions of the barrier layer 214 that are not covered by the barrier layer 240 and the second hard mask layer 242. To form recesses 248, the top insulating pad layer 212 and the bottom insulating pad layer 208 on the sidewalls 206a and 206b of the portion of the trench 202 are exposed.

During the wet etching process, the barrier layer 240 under the second hard mask layer 242 prevents the etching solution from infiltrating into the die gap of the second hard mask layer 242 such as polysilicon, and the damage is located in the second hard mask. A portion of the barrier layer 214 that is not desired to be removed under layer 242 causes a decrease in manufacturing yield.

Then, referring to FIG. 9, the doped region 242a of the remaining second hard mask layer 242 may be removed by dry etching.

Next, referring to FIG. 10, in an embodiment of the present invention, since the barrier layer 240, the first hard mask layer 216 and the bottom insulating spacer layer 208 may be the same material, for example, an oxide, The appropriate etchant is selected, for example, hydrofluoric acid (DHF) can be used as the etching solution, so that the barrier layer 240, the first hard mask layer 216 and the bottom insulating pad layer 208 have a barrier layer 214, a nitride layer 212b and a conductive layer. The layer 210 has a high etch rate (having a good etch selectivity) for performing a fourth wet etch process while removing the barrier layer 240, the first hard mask layer 216 thereunder, and the barrier layer 214 that is not remaining. A bottom insulating layer 208 is covered by the conductive layer 210 to expose the sidewall 226 of the portion of the trench 202. At this time, the barrier layer 214, the nitride layer 212b, and the conductive layer 210 can be regarded as an etched hard mask layer of the fourth wet etching process, which can avoid damaging the portion of the bottom insulating pad layer 208 that is not desired to be removed.

Then, please refer to Fig. 11, and an appropriate etchant can be selected. For example, hydrogen peroxide (H ₂ O ₂ ) and sulfuric acid (H ₂ SO4) can be used as an etching solution to perform a fifth wet etching process to remove residual resistance. Barrier layer 214.

Then, referring to FIG. 12, a diffusion region 230 is formed in a portion of the substrate 200 adjacent to the sidewall 226 of the trench 202. The dopant gas can be injected into the adjacent portion of the substrate 200 from the exposed sidewalls 226 of the trench 202 by gas phase doping to form the diffusion region 230. In an embodiment of the invention, the gas phase doping method may include high temperature rapid gas phase doping (RVD), room temperature gas phase doping, gas immersion laser doping (GILD), and the like. In an embodiment of the invention, the diffusion region 230 can serve as a diffusion junction of the bit line and the drain of the vertical transistor. In an embodiment in which the conductivity type of the substrate 200 is a p-type, the conductivity type of the diffusion region 230 may be an n-type. The conductivity type of the diffusion region 230 depends on the conductivity type of the gas dopant, but is not limited to the embodiment.

Then, the conductive layer 210 is removed by dry etching, and then a conductive material is formed by a chemical vapor deposition (CVD) deposition method, and the trench 202 is filled. In the present embodiment, the conductive material may include a metal such as tungsten. Thereafter, the conductive material above the substrate 200 and partially located in the trench 202 may be removed using an etching back process to form the conductive plug 220, wherein the top surface of the conductive plug 220 is lower than the surface of the substrate 200. And covering the sidewall of the diffusion region 230. In another embodiment, another barrier layer such as titanium nitride may be formed in the trench 202 compliance prior to forming the conductive plug 220. Thereafter, a capping layer 258 can be formed in the trench 202 and covered by the conductive plug 220 using, for example, chemical vapor deposition (CVD) and subsequent etching, for example, an etching back process. In an embodiment of the invention, the material of the cover layer 258 may be, for example, an insulating material of cerium oxide. Next, a subsequent planarization process such as chemical mechanical polishing (CMP) is performed to form the bit line 500 of an embodiment of the present invention as shown in FIG.

Embodiments of the present invention provide a method of fabricating a buried bit line 500 of a dynamic random access memory. The doped polysilicon hard mask is used during the use of the doped polysilicon (doped region 242a of the second hard mask layer 242) as a wet etch hard mask to remove the metal barrier layer on one side of the trench. The oxidized thin layer under the layer (barrier layer 240) prevents the etching solution of the wet etching process from infiltrating into the die gap of the doped polysilicon hard mask layer, and damages a part of the barrier layer located below it without being removed, resulting in Manufacturing yield is falling.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is defined as defined in the scope of the patent application.

200. . . Substrate

201. . . Patterned hard mask layer

202. . . Trench

204. . . Bottom

206, 206a, 206b, 226. . . Side wall

208. . . Bottom insulating mat

210. . . Conductive layer

212. . . Top insulating mat

212a. . . Oxide layer

212b. . . Nitride layer

214. . . Barrier layer

216. . . First hard mask layer

220. . . Conductive plug

230. . . Diffusion zone

240. . . Barrier layer

242. . . Second hard mask layer

242a. . . Doped region

242b. . . Undoped area

246. . . Opening

247, 248. . . Depression

262. . . Ion implantation step

258. . . Cover layer

300. . . Vertical transistor

302. . . Vertical side wall

306. . . Insulation

308. . . Word line

312. . . capacitance

314. . . Bungee area

316. . . Channel area

318. . . Source area

320. . . First direction

322. . . Second direction

500. . . Bit line

600. . . Dynamic random access memory cell

a. . . angle

Fig. 1 is a perspective view showing a dynamic random access memory cell of an embodiment of the present invention.

Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1 showing a bit line of an embodiment of the present invention.

3 to 12 are schematic cross-sectional views showing a method of manufacturing a bit line of the dynamic random access memory according to the embodiment of the present invention as shown in Fig. 2.

200. . . Substrate

201. . . Patterned hard mask layer

202. . . Trench

204. . . Bottom

206, 206a, 206b. . . Side wall

208. . . Bottom insulating mat

210. . . Conductive layer

212. . . Top insulating mat

212a. . . Oxide layer

212b. . . Nitride layer

214. . . Barrier layer

216. . . First hard mask layer

240. . . Barrier layer

242a. . . Doped region

248. . . Depression

Claims (12)

A method for manufacturing a bit line includes the steps of: providing a substrate; forming a trench in the substrate; forming a bottom insulating pad layer on the sidewall and the bottom surface of the lower portion of the trench; Compliance on the sidewall forms a top insulating pad layer; a barrier layer is formed on the sidewall of the trench, and a portion of the top insulating pad layer and the bottom insulating pad layer are covered: a first layer is formed in the trench a hard mask layer covering a portion of the barrier layer; a barrier layer formed in the trench and a second hard mask layer on the upper layer are covered in the trench, and the first hard mask layer is covered; Forming an opening in the layer and the second hard mask layer to expose a portion of the first hard mask layer and a portion of the barrier layer on a side of the trench; removing the barrier layer and the second hard mask a portion of the barrier layer covered by the cap layer; removing the second hard mask layer; simultaneously removing the barrier layer, the first hard mask layer, and the bottom insulating pad layer not covered by the barrier layer to Exposing a portion of the sidewall of the trench; the substrate adjacent to the exposed sidewall of the trench Forming a diffusion region; and forming a conductive plug, and covering the diffusion region in the trench sidewalls. The method for manufacturing a bit line according to claim 1, wherein the step of forming the bottom insulating layer further comprises: forming a first insulating pad layer on the sidewalls and the bottom surface of the trench; Forming a conductive layer in the trench covering the bottom surface and a portion of the sidewall of the trench; and removing the first insulating pad layer not covered by the conductive layer to form the bottom insulating pad layer. The method for manufacturing a bit line according to claim 2, wherein the step of forming the top insulating pad further comprises: conforming to form a second insulating pad layer, and covering the sidewall of the trench and the conductive layer And etching back the second insulating pad layer and a portion of the conductive layer thereunder to form the top insulating pad layer. The method for manufacturing a bit line according to claim 1, wherein the step of forming the opening further comprises: performing an ion implantation step on the second hard mask layer in one direction, for the second hard The mask layer forms a doped region and an undoped region; performing a first etching process to remove the undoped region until a portion of the barrier layer is exposed; and performing a second etching process to remove the exposed The barrier layer. The method for manufacturing a bit line according to claim 4, wherein the angle between the direction and the surface of the substrate is between 10° and 80°. The method of manufacturing a bit line according to claim 4, wherein the first and second etching processes are wet etching processes. The method for manufacturing a bit line according to claim 1, wherein the barrier layer has a thickness of 10 To 100 between. The method of manufacturing a bit line according to claim 1, wherein the barrier layer, the first hard mask layer and the bottom insulating layer are the same material. The method of fabricating the bit line of claim 8, wherein the barrier layer, the first hard mask layer, and the bottom insulating pad layer are oxides. The method of manufacturing a bit line according to claim 2, wherein the conductive layer and the second hard mask layer are the same material. The method of manufacturing a bit line according to claim 9, wherein the conductive layer and the second hard mask layer are polysilicon. The method for manufacturing a bit line according to claim 1, wherein the top insulating pad layer is a nitride layer or a stacked structure of an oxide layer and a nitride layer.