TWI423398B - Memory cell and its manufacturing method and memory structure - Google Patents

Description

Memory cell and its manufacturing method and memory structure

The present invention includes a memory cell, a method of fabricating the same, and a memory structure, and more particularly to a memory cell capable of reducing the occurrence of a punch-through phenomenon and having a channel boosting capability. And its manufacturing method and memory structure.

Memory, as the name suggests, is a semiconductor component used to store data or data. As the functions of computer microprocessors become stronger and stronger, and the programs and operations performed by software become larger and larger, the demand for memory becomes higher and higher. In order to manufacture large-capacity and inexpensive memory to meet this demand. The trend, the technology and process of making memory components, has become the driving force behind the continued high level of semiconductor technology.

Among various memory products, non-volatile memory that has the advantage of being able to store, read, or erase multiple data and the stored data does not disappear after power-off has become a personal computer. A memory component widely used in electronic devices. Flash memory is a widely used non-volatile memory.

As the size of components shrinks, bit line breakdown in flash memory becomes more and more serious. In addition, during the operation of the flash memory, program-inhibited self-boosting also suffers from leakage current problems such as junction leakage currents and The gate induces gate induced drain leakage (GIDL) and thus causes boost failure.

Therefore, how to reduce the occurrence of bit line breakdown and better boosting capability has become an important issue in the development of flash memory.

The invention provides a memory cell comprising a substrate, an insulating layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The insulating layer is disposed on the substrate. The gate is disposed on the insulating layer. The charge storage structure is disposed on the insulating layer and the gate. The first source/drain region is disposed on the charge storage structure on both sides of the gate. The second source/drain region is disposed on the charge storage structure at the top of the gate. The channel layer is disposed on the charge storage structure on the sidewall of the gate and electrically connected to the first source/drain region and the second source/drain region.

According to the memory cell of the embodiment of the invention, the material of the insulating layer is, for example, an oxide or a nitride.

According to the memory structure of the embodiment of the invention, the insulating layer is, for example, a composite insulating layer.

According to the memory cell of the embodiment of the invention, the charge storage structure includes a first dielectric layer, a charge trap layer and a second dielectric layer. The first dielectric layer is disposed on the insulating layer and the gate. The charge trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the charge trap layer.

According to the memory cell of the embodiment of the invention, the material of the charge trapping layer is, for example, a nitride or a high dielectric constant material.

According to the memory cell of the embodiment of the invention, the charge storage structure includes a first dielectric layer, a nano-crystal layer and a second dielectric layer. The first dielectric layer is disposed on the insulating layer and the gate. The nanograin layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the nanograin layer.

According to the memory cell of the embodiment of the invention, the charge storage structure includes a first dielectric layer, a polysilicon layer and a tunneling dielectric layer. The first dielectric layer is disposed on the insulating layer and the gate. The polysilicon layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the polysilicon layer.

According to the memory cell of the embodiment of the present invention, the material of the first source/drain region and the second source/drain region is, for example, a polysilicon having a first conductivity type or a single crystal having a first conductivity type. Hey.

According to the memory cell of the embodiment of the present invention, the material of the channel layer is, for example, a polysilicon having a second conductivity type, a single crystal germanium having a second conductivity type, an undoped polysilicon or an undoped single. Crystal.

According to an embodiment of the present invention, the memory cell can reduce the occurrence of a breakdown phenomenon.

The invention further provides a method of manufacturing a memory cell. A substrate is provided to form an insulating layer on the substrate. A gate is formed on the insulating layer. A charge storage structure is formed on the gate and the insulating layer. A channel material layer is formed on the charge storage structure. A first source/drain region is formed in the channel material layer on both sides of the gate, and a second source/drain region is formed in the channel material layer on the top of the gate.

According to the method for fabricating a memory cell according to an embodiment of the invention, the method for forming the channel material layer is, for example, depositing an undoped polysilicon layer on the charge storage structure.

According to the method for fabricating a memory cell according to an embodiment of the invention, the method for forming the channel material layer is, for example, forming an amorphous germanium layer on the charge storage structure. A metal induced lateral crystallization process is performed to convert the amorphous germanium layer into a single crystal germanium layer.

According to the method for fabricating a memory cell according to an embodiment of the invention, the channel material layer may be further formed after forming the channel material layer and before forming the first source/drain region and the second source/drain region. Ion implantation process.

According to the method for manufacturing a memory cell according to the embodiment of the present invention, the first source/drain region and the second source/drain region are formed, for example, prior to the channel material layer on both sides of the gate. A spacer is formed on the upper side. The ion implantation process is performed by using a spacer as a mask.

According to the method of manufacturing a memory cell according to an embodiment of the invention, after the ion implantation process is performed, a thermal activation process is performed.

A method of fabricating a memory cell according to an embodiment of the invention can increase an effective channel length of a memory cell.

The invention further provides a memory structure comprising a substrate and at least one memory array. The memory array is disposed on the substrate. The memory array includes an insulating layer, two select lines, a plurality of word lines, a charge storage structure, a plurality of first bit lines, a plurality of second bit lines, and a plurality of channel layers. The insulating layer is disposed on the substrate. The selection line is disposed on the insulating layer. The word lines are disposed on the insulating layer and are located between the selection lines. The charge storage structure is disposed on the insulating layer, the selection line, and the word line. The first bit line is respectively disposed on the charge storage structure between the two sides of the selection line and the word line. The second bit lines are respectively disposed on the charge storage structures located at the top of the select lines and the word lines. The channel layers are respectively disposed on the charge storage structures on the sidewalls of the selection lines and the word lines, and each channel layer is electrically connected to the corresponding first bit line and the corresponding second bit line.

According to the memory structure of the embodiment of the invention, the at least one memory array is, for example, a plurality of memory arrays, and the memory arrays are stacked on each other.

The memory structure according to the embodiment of the invention may further have a dielectric layer, a first bit line contact window and a second bit line contact window. The dielectric layer covers these memory arrays separately and is used to isolate these memory arrays. The first bit line contact window is disposed in the dielectric layer for electrically connecting the rightmost first bit line of the memory array. The second bit line contact window is disposed in the dielectric layer for electrically connecting the leftmost first bit line of the memory array.

According to the memory structure of the embodiment of the invention, the material of the dielectric layer is, for example, an oxide or a nitride.

According to the memory structure of the embodiment of the invention, the dielectric layer is, for example, a composite dielectric layer.

The memory structure according to an embodiment of the invention has a better channel boosting capability.

Based on the above, in the present invention, since the channel layer is on the insulating material and is not in contact with the substrate, the channel layer can be fully-depleted during operation, and leakage current can be prevented, and thus Good channel boost capability. In addition, the present invention can also control the length of the channel region by adjusting the height of the gate, so that the effective channel length can be increased without increasing the width of the gate, thereby reducing the occurrence of the breakdown phenomenon.

The above described features and advantages of the present invention will be more apparent from the following description.

1A-1D are cross-sectional views showing a manufacturing process of a memory cell according to an embodiment of the invention. First, referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a crucible substrate. Then, an insulating layer 102 is formed on the substrate 100. The method of forming the insulating layer 102 is, for example, a chemical vapor deposition method. The material of the insulating layer 102 is, for example, an oxide or a nitride. In another embodiment, the insulating layer 102 can also be a composite insulating layer. Next, a gate 104 is formed on the insulating layer 102. The gate 104 is formed by, for example, depositing an undoped polysilicon layer on the insulating layer 102 before performing a patterning process. In addition, an ion implantation process may be performed after depositing the undoped polysilicon layer and prior to the patterning process to implant the p-type dopant into the polysilicon layer.

Then, referring to FIG. 1B, a charge storage structure 106 is formed on the insulating layer 102 and the gate 104. In the present embodiment, the charge storage structure 106 is formed by, for example, forming a dielectric layer 106a, a charge trap layer 106b, and a dielectric layer 106c on the insulating layer 102 and the gate 104. The material of the dielectric layer 106a is, for example, an oxide. The material of the charge trap layer 106b is, for example, a nitride or a high dielectric constant material. The material of the dielectric layer 106c is, for example, an oxide. In another embodiment, the charge storage structure may be formed by sequentially forming a first dielectric layer, a nano-grain layer, and a second dielectric layer on the insulating layer 102 and the gate 104. The material of the nanograin layer is, for example, ruthenium, osmium or a metal. In another embodiment, the charge storage structure may be formed by sequentially forming a first dielectric layer, a polysilicon layer, and a second dielectric layer on the insulating layer 102 and the gate 104. The polysilicon layer is used as a floating gate of a memory cell. Next, a channel material layer 108 is formed over the charge storage structure 106. The material of the channel material layer 108 is, for example, an undoped polysilicon, and the formation method thereof is, for example, a chemical vapor deposition method. In addition, the material of the channel material layer 108 may also be an undoped single crystal germanium formed by, for example, forming an amorphous germanium layer on the charge storage structure 106, and then performing a metal induced lateral crystallization process to The amorphous germanium layer is transformed into a single crystal germanium layer. In addition, in order to control the threshold voltage (Vt) of the memory cell, the channel material layer 108 may be selectively subjected to an ion implantation process after the channel material layer 108 is formed to implant the dopant into the channel material layer 108. . In the present embodiment, the ion implantation process described above is, for example, implanting a p-type dopant into the channel material layer 108.

Next, referring to FIG. 1C, a spacer 110 is formed on the channel material layer 108 on both sides of the gate 104. The material of the spacers 110 is, for example, an oxide. The spacer 110 is formed by, for example, forming a layer of spacer material conformally on the channel material layer 108, and then performing an anisotropic etching process. Then, using the spacers 110 as a mask, an ion implantation process 112 is performed to implant dopants into the channel material layer 108 to form doped regions 114. In particular, the dopant implanted in this step has a different conductivity type than the dopant implanted in the step depicted in Figure 1B. That is, the dopant implanted in this step is an n-type dopant.

Thereafter, referring to FIG. 1D, a thermal process is performed to form source/drain regions 116 in the channel material layer 108 on both sides of the gate 104, and in the channel material layer 108 at the top of the gate 104. The source/drain region 118 is used to complete the fabrication of the memory cell 10. At this time, the remaining channel material layer 108 serves as the channel layer 120 of the memory cell 10. The purpose of performing the thermal process described above is to further diffuse the dopants in the doped regions 114 on both sides of the gate 104 below the spacers 110. In particular, the thermal process described above may be a thermal process performed in a subsequent process, or may be an additional separate thermal process.

The memory cell of the present invention will be described below by taking FIG. 1D as an example.

Referring to FIG. 1D, the memory cell 10 includes a substrate 100, an insulating layer 102, a gate 104, a charge storage structure 106, a source/drain region 116, a source/drain region 118, and a channel layer 120. The insulating layer 102 is disposed on the substrate 100. The gate 104 is disposed on the insulating layer 102. The charge storage structure 106 is disposed on the insulating layer 102 and the gate 104. The source/drain regions 116 are disposed on the charge storage structures 106 on both sides of the gate 104. The source/drain region 118 is disposed on the charge storage structure 106 at the top of the gate 104. The channel layer 120 is disposed on the charge storage structure 106 on the sidewall of the gate 104 and is electrically connected to the source/drain region 116 and the source/drain region 118.

In the memory cell 10, since the channel layer 120 is located on the insulating material (the dielectric layer 106c of the charge storage structure 106), rather than being located in the substrate as in a general flash memory, in the process of operating the memory cell 10. It is possible to avoid leakage current (the channel layer 120 is not in contact with the substrate 100), and thus it is possible to have a better channel boosting capability. In addition, in the memory cell 10, the length of the channel region (i.e., the height of the channel layer 120) can also be controlled by adjusting the height of the gate 104 to increase the effective channel length without increasing the width of the gate 104. In turn, the purpose of reducing the occurrence of breakdown can be achieved.

The memory structure formed by the plurality of memory cells 10 will be described below with reference to FIG.

2 is a cross-sectional view of a memory structure in accordance with an embodiment of the invention. Referring to FIG. 2, the memory structure 200 includes a substrate 202 and a memory array 204. The memory array 204 is disposed on the substrate 202. The memory array 204 includes an insulating layer 206, select lines 208-1 and 208-2, word lines 210-1~210-n, charge storage structure 212, bit lines 214, bit lines 216, spacers 217 and channels. Layer 218. The substrate 202, the insulating layer 206, the charge storage structure 212, the spacer 217, and the channel layer 218 are the same as the substrate 100, the insulating layer 102, the charge storage structure 106, the spacer 110, and the channel layer 120 in FIG. 1D, unless otherwise stated. . The insulating layer 206 is disposed on the substrate 200. The selection lines 208-1 and 208-2 are disposed on the insulating layer 206. The word lines 210-1~210-n are disposed on the insulating layer 206 and are located between the select lines 208-1 and 208-2. The charge storage structure 212 is disposed on the insulating layer 206, the select lines 208-1 and 208-2, and the word lines 210-1~210-n. Bit line 214 is disposed on charge storage structure 212 between two sides of select lines 208-1 and 208-2 and word lines 210-1~210-n. Bit line 216 is disposed on charge storage structure 212 at the top of select lines 208-1 and 208-2 and word lines 210-1~210-n. The channel layer 218 is disposed on the charge storage structure 212 on the sidewalls of the select lines 208-1 and 208-2 and the word lines 210-1~210-n, and the channel layer 218 and the corresponding bit line 214 and corresponding The bit line 216 is electrically connected.

In the memory structure 200, since the channel layer 218 is not in contact with the substrate 202, the channel layer 218 can be fully depleted during operation, and leakage current can be avoided, thereby providing better channel boosting capability. In addition, in the memory structure 200, it is also possible to have a long effective channel length, so that the occurrence of a breakdown phenomenon can be reduced.

In particular, the memory structure of the present invention may be a three-dimensional structure formed by stacking a plurality of memory arrays in addition to the structure of the memory structure 200.

3 is a cross-sectional view of a memory structure in accordance with another embodiment of the present invention. Referring to FIG. 3, the memory structure 300 is stacked on the substrate 202 by a plurality of memory arrays 204. The memory array 204 is shown in FIG. 2 and will not be described here. In memory structure 300, dielectric layer 304 covers memory array 204 and is used to isolate these memory arrays 204. The material of the dielectric layer 304 is, for example, an oxide or a nitride. In another embodiment, each of the dielectric layers 304 may also be a composite dielectric layer formed of a plurality of dielectric layers. In addition, the bit line contact window 306 is disposed in the dielectric layer 304 for electrically connecting the rightmost bit line 214 of the memory array 204. The bit line contact window 308 is disposed in the dielectric layer 304 for electrically connecting the leftmost bit line 214 of the memory array 204. Therefore, during operation, only the voltage applied to the bit line contact windows 306, 308 can simultaneously operate the memory array 204 of each layer.

In the present embodiment, the memory structure 300 is formed by stacking two memory arrays 204. Of course, in other embodiments, the memory structure can also be stacked by more memory arrays 204 depending on actual needs.

Since the memory structure of the present invention can be stacked by a plurality of memory arrays such as the memory array 204, in addition to having better channel boosting capability, avoiding leakage current generation, and reducing the occurrence of breakdown phenomena. It can also effectively increase the density of memory arrays per unit area.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Memory cell

100, 202. . . Base

102, 206. . . Insulation

104. . . Gate

106, 212. . . Charge storage structure

106a, 106c. . . Dielectric layer

106b. . . Charge trapping layer

108. . . Channel material layer

110,217. . . Clearance wall

112. . . Ion implantation process

114. . . Doped region

116, 118. . . Source/bungee area

120, 218. . . Channel layer

200, 300. . . Memory structure

204. . . Memory array

208-1, 208-2. . . Selection line

210-1~210-n. . . Word line

214, 216. . . Bit line

304. . . Dielectric layer

306, 308. . . Bit line contact window

1A-1D are cross-sectional views showing a manufacturing process of a memory cell according to an embodiment of the invention.

2 is a cross-sectional view of a memory structure in accordance with an embodiment of the invention.

3 is a cross-sectional view of a memory structure in accordance with another embodiment of the present invention.

10. . . Memory cell

100. . . Base

102. . . Insulation

104. . . Gate

106. . . Charge storage structure

106a, 106c. . . Dielectric layer

106b. . . Charge trapping layer

110. . . Clearance wall

116, 118. . . Source/bungee area

120. . . Channel layer

Claims (20)

A memory cell includes: a substrate; an insulating layer disposed on the substrate; a gate disposed on the insulating layer; a charge storage structure disposed on the insulating layer and the gate; a first source a / drain region disposed on the charge storage structure on both sides of the gate; a second source/drain region disposed on the charge storage structure at the top of the gate; and a channel layer And being disposed on the charge storage structure on the sidewall of the gate and electrically connected to the first source/drain region and the second source/drain region. The memory cell of claim 1, wherein the material of the insulating layer comprises an oxide or a nitride. The memory cell of claim 1, wherein the insulating layer is a composite dielectric layer. The memory cell of claim 1, wherein the charge storage structure comprises: a first dielectric layer disposed on the insulating layer and the gate; a charge trapping layer disposed on the first dielectric layer And a second dielectric layer disposed on the charge trapping layer. The memory cell of claim 4, wherein the material of the charge trapping layer comprises a nitride or a high dielectric constant material. The memory cell of claim 1, wherein the charge storage structure comprises: a first dielectric layer disposed on the insulating layer and the gate; and a nano-grain layer disposed on the first dielectric layer And a second dielectric layer disposed on the nano-grain layer. The memory cell of claim 1, wherein the charge storage structure comprises: a first dielectric layer disposed on the insulating layer and the gate; and a polysilicon layer disposed on the first dielectric layer And a second dielectric layer disposed on the polysilicon layer. The memory cell of claim 1, wherein the material of the first source/drain region and the second source/drain region comprises a polysilicon having a first conductivity type or having a first conductivity type. Single crystal germanium. The memory cell of claim 8, wherein the material of the channel layer comprises polycrystalline germanium having a second conductivity type, single crystal germanium having a second conductivity type, undoped poly germanium or undoped Single crystal germanium. A method for fabricating a memory cell, comprising: providing a substrate; forming an insulating layer on the substrate; forming a gate on the insulating layer; forming a charge storage structure on the gate and the insulating layer; Forming a channel material layer on the storage structure; and forming a first source/drain region in the channel material layer on both sides of the gate, and forming the channel material layer at the top of the gate A second source/drain region. The method of fabricating a memory cell according to claim 10, wherein the method of forming the channel material layer comprises depositing an undoped polysilicon layer on the charge storage structure. The method for fabricating a memory cell according to claim 10, wherein the method for forming the channel material layer comprises: forming an amorphous germanium layer on the charge storage structure; and performing a metal induced lateral crystallization process to The amorphous germanium layer is converted into a single crystal germanium layer. The method of manufacturing a memory cell according to claim 10, further comprising, after forming the channel material layer and before forming the first source/drain region and the second source/drain region, An ion implantation process is performed on the material layer of the channel. The method for fabricating a memory cell according to claim 10, wherein the method of forming the first source/drain region and the second source/drain region comprises: on two sides of the gate A spacer is formed on the material layer of the channel; and an ion implantation process is performed by using the spacer as a mask. The method for fabricating a memory cell according to claim 14, wherein after performing the ion implantation process, further comprising performing a thermal process. A memory structure, comprising: a substrate; and at least one memory array disposed on the substrate, wherein the memory array comprises: an insulating layer disposed on the substrate, two select lines, disposed on the insulating layer; a plurality of word lines disposed on the insulating layer and located between the select lines; a charge storage structure disposed on the insulating layer, the select lines and the word lines; and a plurality of first bits The lines are respectively disposed on the charge storage structure between the two sides of the select lines and the word lines; the plurality of second bit lines are respectively disposed on the select lines and the word lines The top of the charge storage structure; and a plurality of channel layers respectively disposed on the charge storage structures on the select lines and sidewalls of the word lines, and each of the channel layers and the corresponding one The first bit line and the corresponding second bit line are electrically connected. The memory structure of claim 16, wherein the at least one memory array is a plurality of the memory arrays, and the memory arrays are stacked on each other. The memory structure of claim 17 further comprising: a dielectric layer covering the memory arrays and isolating the memory arrays; a first bit line contact window disposed on The dielectric layer is configured to electrically connect the first bit lines of the rightmost ones of the memory arrays; and a second bit line contact window is disposed in the dielectric layer for The first bit lines of the leftmost ones of the memory arrays are electrically connected. The memory structure of claim 18, wherein the material of the dielectric layer comprises an oxide or a nitride. The memory structure of claim 18, wherein the dielectric layer is a composite dielectric layer.