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TWI422030B - Contant current semiconductor device with schottky barrier structure - Google Patents

Contant current semiconductor device with schottky barrier structure Download PDF

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TWI422030B
TWI422030B TW100127075A TW100127075A TWI422030B TW I422030 B TWI422030 B TW I422030B TW 100127075 A TW100127075 A TW 100127075A TW 100127075 A TW100127075 A TW 100127075A TW I422030 B TWI422030 B TW I422030B
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metal electrode
schottky barrier
semiconductor device
constant current
epitaxial layer
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TW100127075A
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TW201306253A (en
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Sheau Feng Tsai
Wen Ping Huang
Tzuu Chi Hu
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Formosa Microsemi Co Ltd
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Description

具備蕭特基能障(Schottky Barrier)之定電流半導體元件Constant current semiconductor components with Schottky Barrier

本發明為一種與半導體有關之技術,特別是指一種利用金屬/半導體接觸原理製成具備蕭特基能障(Schottky Barrier)之定電流半導體元件,其結構/特性與蕭特基二極體有所差異。The present invention relates to a semiconductor-related technology, and more particularly to a constant current semiconductor device having a Schottky Barrier using a metal/semiconductor contact principle, the structure/characteristics of which have a Schottky diode. The difference.

以半導體基材所製成的PN二極體,其基本原理是將P型及N型半導體基材藉由半導體擴散等技術形成接合後封裝,並分別以電極連接外部端子所構成;較常見的使用狀況是藉由電流由P型區流向N型區容易通過,相反方向不易通過的特性,來做為整流器(Rectifier)使用。另外,蕭特基二極體是藉由金屬/半導體接合的蕭特基能障也有單向可通過電流,另一方向電流不通的特性而做整流之用。特別是用在交流電源轉換成直流電源,以提供給一般電子產品的電子電路使用。The basic principle of a PN diode made of a semiconductor substrate is to form a P-type and N-type semiconductor substrate by a semiconductor diffusion technique, and to form an external package by electrodes, respectively; The use condition is a rectifier (Rectifier) used by a current flowing from a P-type region to an N-type region and passing through in a reverse direction. In addition, the Schottky diode is a metal-semiconductor-bonded Schottky barrier that also has a unidirectional current through current and a non-passing current in the other direction. It is especially used in the conversion of AC power to DC power for use in electronic circuits for general electronic products.

上述PN二極體/蕭特基二極體除了做為整流器以外,根據其功能及材質特性上的不同,還分為定電壓二極體(Zener Diode)、關關二極體(Switching Diode)、光電二極體(Photo Diode)等等。又,發光二極體(LED,Light Emitting Diode)以節省能源、輕薄短小之特性而早已廣泛應用在各類電子產品上;近年來LED發展出高亮度(HI-POWER LED)技術後,更有取代傳統各種照明用發光裝置之趨勢,舉凡工業用、家用照明、交通道路等、都可見到LED使用的蹤跡。In addition to being a rectifier, the above-mentioned PN diode/Schottky diode is also classified into a Zener Diode and a Switching Diode depending on its function and material properties. , Photo Diode and so on. In addition, LEDs (Light Emitting Diodes) have been widely used in various electronic products to save energy, light weight and shortness. In recent years, LEDs have developed high-brightness (HI-POWER LED) technology. In place of the traditional trend of various lighting illuminators, the use of LEDs can be seen in industrial, household lighting, traffic roads, and the like.

在上述LED以及一般應用電路設計上,較常見的是使用定電壓電源來對LED陣列做定電壓控制,只要電源電路輸出電壓符合LED陣列的額定電壓時,即可驅動LED陣列。惟LED陣列因所使用場所的不同而有不同數量及電壓值,必須依照LED單體數量加上適配的串聯限流電阻以限制輸出過高的電壓到電源電路上,如此一來就會造成功率損耗,而且當LED陣列中,有某一部分LED單體損壞時,將造成整體電壓降低、電流加大而致使其他LED單體亦陸續損壞;另外,定電壓電源亦常因電壓不穩而造成LED在使用時有閃爍的問題。In the above LED and general application circuit design, it is more common to use a constant voltage power supply to perform constant voltage control on the LED array. As long as the output voltage of the power supply circuit meets the rated voltage of the LED array, the LED array can be driven. However, LED arrays have different numbers and voltage values depending on the place used. It is necessary to add an excessive series voltage to the power supply circuit according to the number of LEDs and the matching series current limiting resistor. Power loss, and when a certain part of the LED array is damaged in the LED array, the overall voltage will decrease and the current will increase, causing other LED units to be damaged one after another; in addition, the constant voltage power supply is often caused by voltage instability. LEDs have problems with flicker when in use.

為了克服上述問題,理論上採用定電流電源控制方式優於定電壓電源控制,但目前定電流控制的實施方式,多以複雜的積體電路設計整合組成,成本非常高;若以兩極定電流的方式採用複雜PN接面電晶體平面技術而製成,不但良品率欠佳、無法大量生產,而且不容易產生較大驅動電流。In order to overcome the above problems, the theoretical use of constant current power supply control method is better than constant voltage power supply control, but the current implementation of constant current control is mostly composed of complex integrated circuit design, and the cost is very high; The method is made by using complex PN junction transistor plane technology, which not only has poor yield, can not be mass produced, and is not easy to generate large driving current.

有鑒於此,本發明人乃累積多年半導體技術領域的研究以及實務經驗,發明出一種「具備蕭特基能障(Schottky Barrier)之定電流半導體元件」,以期能改善先前技術的缺點。In view of this, the present inventors have accumulated years of research and practical experience in the field of semiconductor technology, and have invented a "constant current semiconductor device having a Schottky Barrier" in order to improve the disadvantages of the prior art.

本發明之目的在於提供一種具備蕭特基能障(Schottky Barrier)之定電流半導體元件,該半導體元件具備蕭特基能障及定電流之特性,不但具有較低啟動電壓,而且其製程中容易將數個半導體元件單體隔離,並積體組合成適用於較大驅動電流的定電流半導體元件或設計成定電流半導體元件陣列(Arrays)的方式來使用;其結構/特性與蕭特基二極體有所差異。It is an object of the present invention to provide a constant current semiconductor device having a Schottky Barrier having a Schottky barrier and a constant current characteristic, which has a low starting voltage and is easy to process. Separating a plurality of semiconductor element elements and combining them into a constant current semiconductor element suitable for a large driving current or an array designed as a constant current semiconductor element (Arrays); its structure/characteristics and Schottky II The polar body is different.

為達成上述目的,本發明「具備蕭特基能障(Schottky Barrier)之定電流半導體元件」,係於一成長在半絕緣基板上的N型或P型半導體磊晶層(Epitaxial Layer)表面,設置有可供電氣連接的一個第一金屬電極端及第二金屬電極端,其中第一金屬電極端與磊晶層之間包括有一第一毆姆接觸(Ohmic Contact)區段以及一蕭特基接觸(Schottky Contact)區段,第二金屬電極端與上述磊晶層之間則為一第二毆姆接觸區段,且蕭特基接觸區段位於第一、二毆姆接觸區段之間,與第二毆姆接觸區段相互隔離,使該半導體元件在蕭特基接觸區段位置具備蕭特基能障較低啟動電壓之特性,並藉由該磊晶層之厚度、材質、以及第一、二金屬電極端之間的距離設計而具備定電流功能,且其結構/特性與蕭特基二極體有所差異。In order to achieve the above object, the present invention "a constant current semiconductor device having a Schottky Barrier" is formed on an N-type or P-type semiconductor epitaxial layer surface which is grown on a semi-insulating substrate. A first metal electrode end and a second metal electrode end are provided for electrical connection, wherein the first metal electrode end and the epitaxial layer include a first Ohmic Contact section and a Schottky a Schottky Contact section, a second ohmic contact section between the second metal electrode end and the epitaxial layer, and the Schottky contact section between the first and second ohmic contact sections Separating from the second ohmic contact section, the semiconductor element has a Schottky barrier lower starting voltage at the Schottky contact section, and the thickness, material, and thickness of the epitaxial layer The distance between the first and second metal electrode terminals is designed to have a constant current function, and its structure/characteristic is different from that of the Schottky diode.

本發明的第二種實施方式,係於一成長在半絕緣基板上的N型或P型半導體磊晶層(Epitaxial Layer)表面,設置有可供電氣連接且相互隔離的一個第一金屬電極端及第二金屬電極端,且磊晶層在第一、第二金屬電極端之間設置有一呈凹陷的階段平台(Recessed Mesa);其中第一金屬電極端與磊晶層間為一第一毆姆接觸(Ohmic Contact)區段,且該第一金屬電極端沿磊晶層表面延伸到階段平台,與階段平台之間為一蕭特基接觸(Schottky Contact)區段,第二金屬電極與磊晶層之間則為一第二毆姆接觸區段,且第二毆姆接觸區段與蕭特基接觸區段相互隔離,使該半導體元件在蕭特基接觸區段位置具備蕭特基能障較低啟動電壓之特性,並藉由磊晶層之厚度、材質以及該階段平台深度或寬度設計而具備定電流功能,且其結構/特性與蕭特基二極體有所差異。A second embodiment of the present invention is an N-type or P-type epitaxial layer surface grown on a semi-insulating substrate, and is provided with a first metal electrode end electrically connectable and isolated from each other. And a second metal electrode end, and the epitaxial layer is provided with a recessed stage platform (Recessed Mesa) between the first and second metal electrode ends; wherein the first metal electrode end and the epitaxial layer are a first 殴m Contacting an (Ohmic Contact) section, and the first metal electrode end extends along the surface of the epitaxial layer to the stage platform, and is a Schottky Contact section, a second metal electrode and an epitaxial layer Between the layers is a second 接触 contact section, and the second 接触 接触 contact section and the Schottky contact section are isolated from each other, so that the semiconductor element has a Schottky barrier at the Schottky contact section The characteristics of the lower starting voltage, and the constant current function by the thickness and material of the epitaxial layer and the depth or width of the platform at this stage, and its structure/characteristics are different from those of the Schottky diode.

上述定電流半導體元件實施時,第一金屬電極端及第二金屬電極端可供電氣連接,因此後續製程可以先將半導體元件固定於支架上,並藉由第一、第二金屬電極端與支架上的端子電氣連接,則在經過覆晶封裝(Flip-Chip)以及分割製程後,即可形成定電流二極體。當然,第一、第二金屬電極端若選用適當材質,直接曝露在外部以作為SMD(表面黏著型元件)的端子使用,亦為可行的實施方式之一。When the constant current semiconductor component is implemented, the first metal electrode end and the second metal electrode end are electrically connected, so that the subsequent process can first fix the semiconductor component on the bracket, and the first and second metal electrode ends and the bracket When the upper terminal is electrically connected, a constant current diode can be formed after the Flip-Chip and the division process. Of course, it is also one of the feasible embodiments that the first and second metal electrode ends are directly exposed to the outside as the terminals of the SMD (Surface Adhesive Element) if a suitable material is selected.

除此,若在製程中直接在一大面積晶圓上將上述複數個具備蕭特基能障之定電流半導體元件彼此單體隔離(Isolation),即可利用製程中的光罩及照相技術設計而積體組合成適用於較大驅動電流的定電流半導體元件。也可利用支架設計複數個具備蕭特基能障之定電流半導體元件,後續同樣經過覆晶封裝(Flip-Chip)即可形成定電流元件陣列(Arrays),不但具有節省工時、容易設計製造等優點,而且使用時結構體在表面散熱,故其散熱性尤佳,具有更為寬廣地適用範圍。In addition, if the above-mentioned plurality of constant current semiconductor devices having Schottky barriers are isolated from each other directly on a large-area wafer in the process, the photomask and the photographic technology in the process can be utilized. The integrated body is combined into a constant current semiconductor element suitable for a large driving current. It is also possible to design a plurality of constant current semiconductor components with Schottky barriers by using a bracket, and then form a current-regulating device array (Arrays) through a flip chip package (Flip-Chip), which not only saves man-hours, but also is easy to design and manufacture. The advantages are as follows, and when the structure is used to dissipate heat on the surface, the heat dissipation is particularly good, and the utility model has a wider application range.

以下進一步說明本發明的其他具體實施方式:製程中,為了方便將所述的第一、第二金屬電極端與支架上的端子電氣連接及固定,實施時可以在第一、第二金屬電極端表面分別各設置一焊球。若如前述令第一、第二金屬電極端直接曝露在外部以作為SMD(表面黏著型元件)的端子使用時,焊球亦可以作為SMT(表面黏著技術)焊接於PC板或其他基板上的焊料。Other embodiments of the present invention are further described below. In the process, the first and second metal electrode ends are electrically connected and fixed to the terminals on the bracket for convenience, and may be implemented at the first and second metal electrode ends. A solder ball is placed on each surface. If the first and second metal electrode terminals are directly exposed to the outside as terminals of the SMD (Surface Adhesive Element) as described above, the solder balls can also be soldered to the PC board or other substrate as SMT (Surface Adhesion Technology). solder.

為了增加產品良率,所述的第一、第二金屬電極端之間可以設置一絕緣保護層,俾能確保第一、第二金屬電極端之間的絕緣狀態。In order to increase the product yield, an insulating protective layer may be disposed between the first and second metal electrode ends to ensure an insulation state between the first and second metal electrode ends.

為了達成上述大型定電流元件及定電流元件陣列(Arrays)的效果,讓同一晶圓上的複數個具備蕭特基能障之定電流半導體元件彼此單體隔離(Isolation),可以在磊晶層兩側施予擴散(Diffusion)製程,以形成隔離層。In order to achieve the effect of the above-mentioned large-scale constant current element and constant current element array (Arrays), a plurality of constant current semiconductor elements having Schottky barriers on the same wafer can be isolated from each other by an Isolation layer. Diffusion processes are applied to both sides to form an isolation layer.

製程中,為了後續將同一晶圓上的複數個具備蕭特基能障之定電流半導體元件進行分割製程,可以在磊晶層兩側施予高台(Mesa)蝕刻製程以形成兩側隔離溝槽,並於兩側隔離溝槽內填充設置玻璃(Glass)或是氧化層等物質所形成的一層被動保護層(Passivation)。In the process, in order to subsequently divide a plurality of fixed current semiconductor components having Schottky barriers on the same wafer, a Mesa etching process may be applied on both sides of the epitaxial layer to form isolated trenches on both sides. And a passive protective layer (Passivation) formed by the glass or the oxide layer is filled in the isolation trenches on both sides.

實施時,前述階段平台之形成可以與此高台(Mesa)蝕刻製程同時或分次進行;被動保護層則可以和前述絕緣保護層在同一製程或分次實施。In implementation, the formation of the aforementioned stage platform may be performed simultaneously or in stages with the Mesa etching process; the passive protective layer may be implemented in the same process or in stages as the foregoing insulating protective layer.

相較於習知技術,本發明「具備蕭特基能障(Schottky Barrier)之定電流半導體元件」,除了具備蕭特基能障較低啟動電壓、以及定電流之特性以外,不但結構/特性與蕭特基二極體有所差異,而且其製程中容易將數個半導體元件單體隔離,並積體組合成適用於較大驅動電流的定電流半導體元件,因此還具有節省工時、容易設計製造等諸多優點;在使用時,由於其結構體在表面散熱,故其散熱性尤佳,具有更為寬廣地適用範圍。Compared with the prior art, the present invention has a Schottky Barrier constant current semiconductor component, and has a structure/characteristics in addition to a low starting voltage and a constant current characteristic of the Schottky barrier. Different from the Schottky diode, and it is easy to isolate several semiconductor components in the process, and combine them into a constant current semiconductor component suitable for a large driving current, thereby saving labor and time. Many advantages such as design and manufacture; in use, because the structure is heat-dissipated on the surface, its heat dissipation is particularly good, and it has a wider application range.

以下依據本發明之技術手段,列舉出適於本發明之實施方式,並配合圖式說明如後:如第一圖所示,本發明具備蕭特基能障(Schottky Barrier)之定電流半導體元件100,係於一成長在半絕緣基板10上的N型或P型半導體磊晶層(Epitaxial Layer)20表面,設置有可供電氣連接的一個第一金屬電極端30及第二金屬電極端40;其中,第一金屬電極端30與磊晶層20之間包括有一第一毆姆接觸(Ohmic Contact)區段31以及一蕭特基接觸(Schottky Contact)區段32,而所述的第二金屬電極端40與上述磊晶層20之間則為一第二毆姆接觸區段41,以令蕭特基接觸區段32位於第一、二毆姆接觸區段31、41之間,且蕭特基接觸區段32與第二毆姆接觸區段41相互隔離,使該半導體元件100在蕭特基接觸區段32位置具備蕭特基能障較低啟動電壓之特性,並藉由該磊晶層20之厚度、材質及第一、二金屬電極端30、40之間的距離設計而具備定電流功能,且其結構/特性與蕭特基二極體有所差異。In the following, according to the technical means of the present invention, embodiments suitable for the present invention are listed, and the following description is made in conjunction with the following description: As shown in the first figure, the present invention has a Schottky Barrier constant current semiconductor component. 100 is disposed on an surface of an N-type or P-type semiconductor epitaxial layer 20 grown on a semi-insulating substrate 10, and is provided with a first metal electrode end 30 and a second metal electrode end 40 for electrical connection. Wherein, the first metal electrode end 30 and the epitaxial layer 20 include a first Ohmic Contact section 31 and a Schottky Contact section 32, and the second Between the metal electrode terminal 40 and the epitaxial layer 20 is a second contact region 41 such that the Schottky contact portion 32 is located between the first and second contact regions 31, 41, and The Schottky contact section 32 and the second ohmic contact section 41 are isolated from each other such that the semiconductor element 100 has a Schottky barrier lower starting voltage characteristic at the Schottky contact section 32, and Thickness, material of the epitaxial layer 20 and between the first and second metal electrode ends 30, 40 Design includes a constant current from the function and the structure / characteristics of the Schottky diode differ.

如第二圖所示,本發明第二種實施方式的半導體元件100,係於一成長在半絕緣基板10上的N型或P型半導體磊晶層(Epitaxial Layer)20表面,設置有可供電氣連接的一個第一金屬電極端30以及一個第二金屬電極端40,且磊晶層20在第一、第二金屬電極端30、40之間設置有一呈凹陷的階段平台(Recessed Mesa)21;其中第一金屬電極端30與磊晶層20間為一第一毆姆接觸(Ohmic Contact)區段31,且該第一金屬電極端30沿磊晶層20表面向下彎折延伸到階段平台21的凹陷部位,第一金屬電極端30的向下延伸段底部與階段平台21頂面之間為一蕭特基接觸(Schottky Contact)區段32;而所述的第二金屬電極40與磊晶層20之間則為一第二毆姆接觸區段41,且第二毆姆接觸區段41與前述蕭特基接觸區段32相互隔離,使該半導體元件100在蕭特基接觸區段32位置具備蕭特基能障較低啟動電壓之特性,並藉由磊晶層20之厚度、材質以及該階段平台21的深度或寬度設計而具備定電流功能,且其結構/特性與蕭特基二極體有所差異。As shown in the second figure, the semiconductor device 100 of the second embodiment of the present invention is provided on the surface of an N-type or P-type semiconductor epitaxial layer 20 grown on the semi-insulating substrate 10. A first metal electrode end 30 and a second metal electrode end 40 are electrically connected, and the epitaxial layer 20 is provided with a recessed stage platform (Recessed Mesa) 21 between the first and second metal electrode ends 30, 40. Wherein the first metal electrode end 30 and the epitaxial layer 20 are a first Ohmic Contact section 31, and the first metal electrode end 30 is bent down along the surface of the epitaxial layer 20 to the stage. a recessed portion of the platform 21, a bottom portion of the downwardly extending portion of the first metal electrode end 30 and a top surface of the stage platform 21 is a Schottky Contact section 32; and the second metal electrode 40 is Between the epitaxial layers 20 is a second ohmic contact section 41, and the second ohmic contact section 41 is isolated from the aforementioned Schottky contact section 32, so that the semiconductor element 100 is in the Schottky contact area. Segment 32 has the characteristics of a lower start-up voltage of the Schottky barrier and is controlled by epitaxy 20 thickness, the material and the depth or width of the stage platform 21 is designed to have constant current function, and the structure / characteristics of the Schottky diode differ.

上述半導體元件100具備蕭特基能障較低啟動電壓之特性以及定電流功能,其特性曲線如第三圖所示:當半導體元件處於較低電壓,此區段A兩電極之間呈現電阻特性;因控制蕭特基之電壓,即改變蕭特基能障下之空乏區(Depletion Layer),到VKP 時開始轉折線性電阻特性即切斷(cut-off)導電管道電流而進入飽和的定電流IP (即圖示中的區段B);此時,藉由前述設計磊晶層20之厚度、材質、以及第一、二金屬電極端之間的距離,或階段平台的深度、寬度,可以控制特性曲線隨電壓昇高(V SP~V B)而進入崩潰(Breakdown)區段C,則因蕭特基能障之設計即可達成前述低啟動電壓(V KP)以及定電流(IP)之效果。The semiconductor device 100 has a low start-up voltage characteristic and a constant current function, and its characteristic curve is as shown in the third figure: when the semiconductor element is at a lower voltage, the resistance characteristics between the two electrodes of the segment A are exhibited. Because the voltage of Schottky is controlled, that is, the Depletion Layer under the Schottky barrier is changed, and when it is V KP , the linear resistance characteristic is turned, that is, the cut-off conductive pipe current is turned into saturation. Current I P (ie, segment B in the figure); at this time, the thickness, material, and distance between the first and second metal electrode terminals, or the depth and width of the stage platform, are designed by the foregoing design. It is possible to control the characteristic curve to enter the breakdown phase C as the voltage rises (V SP~VB), and the low start voltage (V KP) and the constant current (IP) can be achieved by the design of the Schottky barrier. ) The effect.

又,上述本發明具備蕭特基能障(Schottky Barrier)之定電流半導體元件經實驗確實能達成效果,例如:前述半絕緣基板採用約電阻係數20Ω-cm、磊晶層約為2Ω-cm厚度10μm、蕭特基能障寬度約2μm、半導體元件尺寸約為300~600μm X 300~600μm正方,則可以製成電壓在10V-100V間、約20mA之定電流半導元件成品。Moreover, the above-described constant current semiconductor device having the Schottky Barrier of the present invention can achieve an effect by experiments. For example, the semi-insulating substrate has a resistivity of 20 Ω-cm and an epitaxial layer of about 2 Ω-cm. 10μm, Schottky barrier width of about 2μm, semiconductor component size of about 300~600μm X 300~600μm square, can be made into a constant current semi-conductive component with a voltage between 10V-100V and about 20mA.

上述定電流半導體元件實施時,第一金屬電極端及第二金屬電極端可供電氣連接,因此後續製程可以先將半導體元件固定於支架上,並藉由第一、第二金屬電極端與支架上的端子電氣連接,則在經過覆晶封裝(Flip-Chip)以及分割製程後,即可形成定電流二極體。當然,第一、第二金屬電極端若選用適當材質,直接曝露在外部以作為SMD(表面黏著型元件)的端子使用,亦為可行的實施方式之一;所述支架、端子、覆晶封裝、分割製程以及SMD等皆屬習知技術,在此不另贅述。When the constant current semiconductor component is implemented, the first metal electrode end and the second metal electrode end are electrically connected, so that the subsequent process can first fix the semiconductor component on the bracket, and the first and second metal electrode ends and the bracket When the upper terminal is electrically connected, a constant current diode can be formed after the Flip-Chip and the division process. Of course, if the first and second metal electrode ends are directly exposed to the outside as the terminals of the SMD (Surface Adhesive Element), it is also one of the feasible embodiments; the bracket, the terminal, and the flip chip package are used. , the division process and the SMD are all known techniques, and are not described here.

除此,若在製程中直接在一大面積晶圓上將上述複數個具備蕭特基能障之定電流半導體元件彼此單體隔離(Isolation),即可利用製程中光罩及照相技術設計而積體組合成適用於較大驅動電流的定電流半導體元件。也可利用支架設計複數個具備蕭特基能障之定電流半導體元件,後續同樣經過覆晶封裝(Flip-Chip)即可形成定電流元件陣列(Arrays),不但具有節省工時、容易設計製造等優點,而且使用時由於結構體在表面散熱,故其散熱性尤佳,具有更為寬廣地適用範圍。In addition, if the above-mentioned plurality of constant current semiconductor devices having Schottky barriers are directly isolated from each other on a large-area wafer in the process, the process can be designed by using the mask and the photographic technology in the process. The integrated body is combined into a constant current semiconductor element suitable for a large driving current. It is also possible to design a plurality of constant current semiconductor components with Schottky barriers by using a bracket, and then form a current-regulating device array (Arrays) through a flip chip package (Flip-Chip), which not only saves man-hours, but also is easy to design and manufacture. It has the advantages, and the heat dissipation is particularly good due to the heat dissipation of the structure on the surface during use, and has a wider application range.

以下進一步說明本發明的其他具體實施方式:如第四、五圖所示,為了方便將半導體元件固定於前述支架上,可以在第一、第二金屬電極端30、40表面分別各設置一焊球50,俾能藉由焊球50與支架上的端子焊接固定,並且電氣連接。若如前述令第一、第二金屬電極端30、40直接曝露在外部以作為SMD(表面黏著型元件)的端子使用時,焊球50亦可以作為SMT(表面黏著技術)焊接於PC板或其他基板上的焊料。Further embodiments of the present invention are further described below. As shown in the fourth and fifth figures, in order to facilitate the fixing of the semiconductor element to the holder, a solder may be respectively disposed on the surfaces of the first and second metal electrode ends 30, 40. The ball 50, which can be soldered to the terminal on the bracket by the solder ball 50, is electrically connected. If the first and second metal electrode terminals 30, 40 are directly exposed to the outside as the terminals of the SMD (Surface Adhesive Element), the solder ball 50 can also be soldered to the PC board as an SMT (Surface Adhesion Technology) or Solder on other substrates.

製程中,為了增加產品良率,實施時可以在所述的第一、第二金屬電極端30、40之間設置一絕緣保護層60,俾能確保第一、第二金屬電極端30、40之間的絕緣狀態。In the process, in order to increase the product yield, an insulating protective layer 60 may be disposed between the first and second metal electrode ends 30, 40 to ensure the first and second metal electrode ends 30, 40. The state of insulation between.

製程中,為了達成上述大型定電流元件及定電流元件陣列(Arrays)製程,讓同一晶圓上的複數個具備蕭特基能障之定電流半導體元件100彼此單體隔離(Isolation),可以在磊晶層20的兩側施予擴散(Diffusion)製程,使兩相鄰的半導體元件100、100’之磊晶層20、20’之間形成隔離層70,則隔離層70即可以讓兩相鄰的半導體元件100、100’彼此單體隔離,以達成前述積體組合成適用於較大驅動電流的定電流半導體元件,並且經過後續製程後,製成適用於大電流之大型定電流元件及定電流元件陣列(Arrays)。In the process, in order to achieve the above-mentioned large-scale constant current element and constant current element array (Arrays) process, a plurality of fixed-current semiconductor elements 100 having Schottky barriers on the same wafer are isolated from each other (Isolation). A diffusion process is applied to both sides of the epitaxial layer 20 to form an isolation layer 70 between the epitaxial layers 20, 20' of the two adjacent semiconductor elements 100, 100'. The isolation layer 70 allows two phases. The adjacent semiconductor elements 100, 100' are individually isolated from each other to achieve the above-mentioned integrated body assembly into a constant current semiconductor element suitable for a large driving current, and after a subsequent process, a large-sized constant current element suitable for a large current is formed. Constant current element arrays (Arrays).

如第一、二圖所示,製程中,為了後續將同一晶圓上的複數個具備蕭特基能障之定電流半導體元件100進行分割製程,可以在磊晶層20兩側施予高台(Mesa)蝕刻製程以形成兩側隔離溝槽22,並於兩側隔離溝槽22內填充設置玻璃(Glass)或是氧化層等物質所形成的一層被動保護層(Passivation)23,如此即可在每一經分割製程後的半導體元件100兩側形成被動保護效果。As shown in the first and second figures, in the process, in order to carry out the dividing process of the plurality of constant current semiconductor elements 100 having the Schottky barrier on the same wafer, the high stage can be applied on both sides of the epitaxial layer 20 ( Mesa) etching process to form two isolation trenches 22, and a passive protective layer 23 formed by filling a glass or an oxide layer on the two isolation trenches 22, so that A passive protection effect is formed on both sides of the semiconductor component 100 after each divided process.

實施時,前述階段平台21之形成可以與此高台(Mesa)蝕刻製程同時或分次進行;而被動保護層23則可以和前述絕緣保護層60在同一製程或分次實施,以節省工時及製造流程。In implementation, the formation of the stage stage 21 can be performed simultaneously or in stages with the Mesa etching process; and the passive protective layer 23 can be implemented in the same process or in stages as the insulating protective layer 60 to save man-hours and Manufacturing process.

上述各名稱係為方便描述本發明之技術內容所定,而非用以限制本案之權利範圍,舉凡依據本案之創作精神所作的等效元件轉換、替代,均應涵蓋在本案之保護範圍內,謹此聲明。The above names are intended to describe the technical content of the present invention, and are not intended to limit the scope of the present invention. All equivalent component conversions and substitutions made in accordance with the creative spirit of this case should be covered in the scope of this case. This statement.

100...半導體元件100. . . Semiconductor component

10...半絕緣基板10. . . Semi-insulating substrate

20...磊晶層20. . . Epitaxial layer

21...階段平台twenty one. . . Stage platform

22...隔離溝槽twenty two. . . Isolation trench

23...被動保護層twenty three. . . Passive protective layer

30...第一金屬電極端30. . . First metal electrode end

31...第一毆姆接觸區段31. . . First 接触m contact section

32...蕭特基接觸區段32. . . Schottky Contact Section

40...第二金屬電極端40. . . Second metal electrode end

41...第二毆姆接觸區段41. . . Second 接触m contact section

50...焊球50. . . Solder ball

60...絕緣保護層60. . . Insulating protective layer

70...隔離層70. . . Isolation layer

第一圖係本發明第一實施例之側面剖視結構示意圖。The first figure is a side cross-sectional structural view of a first embodiment of the present invention.

第二圖係本發明第二實施例之側面剖視結構示意圖。The second drawing is a side cross-sectional structural view of a second embodiment of the present invention.

第三圖係本發明實施時蕭特基能障及定電流之特性曲線示意圖。The third figure is a schematic diagram showing the characteristic curves of Schottky barrier and constant current in the implementation of the present invention.

第四圖係本發明第一實施例之其他實施方式結構示意圖。The fourth figure is a schematic structural view of another embodiment of the first embodiment of the present invention.

第五圖係本發明第二實施例之其他實施方式結構示意圖。The fifth drawing is a schematic structural view of another embodiment of the second embodiment of the present invention.

100...半導體元件100. . . Semiconductor component

10...半絕緣基板10. . . Semi-insulating substrate

20...磊晶層20. . . Epitaxial layer

22...隔離溝槽twenty two. . . Isolation trench

23...被動保護層twenty three. . . Passive protective layer

30...第一金屬電極端30. . . First metal electrode end

31...第一毆姆接觸區段31. . . First 接触m contact section

32...蕭特基接觸區段32. . . Schottky Contact Section

40...第二金屬電極端40. . . Second metal electrode end

41...第二毆姆接觸區段41. . . Second 接触m contact section

60...絕緣保護層60. . . Insulating protective layer

Claims (9)

一種具備蕭特基能障之定電流半導體元件,係於一成長在半絕緣基板上的N型或P型半導體磊晶層表面,設置有可供電氣連接的一個第一金屬電極端及第二金屬電極端,且磊晶層在第一、第二金屬電極端之間設置有一呈凹陷的階段平台;該第一金屬電極端與磊晶層間為一第一毆姆接觸區段,且該第一金屬電極端沿磊晶層表面向下彎折延伸到階段平台的凹陷部位,第一金屬電極端的向下延伸段底部與階段平台頂面之間為一蕭特基接觸區段,第二金屬電極與磊晶層之間則為一第二毆姆接觸區段,且該第二毆姆接觸區段與所述的蕭特基接觸區段相互隔離。 A constant current semiconductor device having a Schottky barrier is formed on a surface of an N-type or P-type semiconductor epitaxial layer grown on a semi-insulating substrate, and is provided with a first metal electrode terminal and a second for electrical connection a metal electrode end, and the epitaxial layer is provided with a recessed stage platform between the first and second metal electrode ends; the first metal electrode end and the epitaxial layer are a first contact region, and the first A metal electrode end is bent downward along the surface of the epitaxial layer to a recessed portion of the stage platform, and a bottom portion of the downward extending portion of the first metal electrode end and a top surface of the stage platform is a Schottky contact section, and the second metal Between the electrode and the epitaxial layer is a second ohmic contact section, and the second ohmic contact section is isolated from the Schottky contact section. 如申請專利範圍第1項所述具備蕭特基能障之定電流半導體元件,其中,階段平台係利用高台蝕刻製程所形成。 A fixed current semiconductor device having a Schottky barrier according to the first aspect of the patent application, wherein the stage platform is formed by a high etching process. 如申請專利範圍第1項所述具備蕭特基能障之定電流半導體元件,其中第一、第二金屬電極端進一步在表面分別各設置一焊球。 A constant current semiconductor device having a Schottky barrier according to the first aspect of the invention, wherein the first and second metal electrode ends are further provided with a solder ball on each surface. 如申請專利範圍第1項所述具備蕭特基能障之定電流半導體元件,其中第一、第二金屬電極端之間進一步設置一絕緣保護層。 A constant current semiconductor device having a Schottky barrier according to the first aspect of the invention, wherein an insulating protective layer is further disposed between the first and second metal electrode ends. 如申請專利範圍第1項所述具備蕭特基能障之定電流半導體元件,其中,磊晶層的兩側進一步設置有隔離層,使製程中兩相鄰的半導體元件彼此單體隔離。 A fixed current semiconductor device having a Schottky barrier according to the first aspect of the invention, wherein an isolation layer is further disposed on both sides of the epitaxial layer to isolate two adjacent semiconductor elements from each other in the process. 如申請專利範圍第5項所述具備蕭特基能障之定電流半導體元 件,其中,隔離層是由擴散製程所構成。 A constant current semiconductor element having a Schottky barrier as described in claim 5 And wherein the isolation layer is formed by a diffusion process. 如申請專利範圍第1項所述具備蕭特基能障之定電流半導體元件,其中,磊晶層的兩側進一步設置有隔離溝槽。 A constant current semiconductor device having a Schottky barrier according to the first aspect of the invention, wherein an isolation trench is further provided on both sides of the epitaxial layer. 如申請專利範圍第7項所述具備蕭特基能障之定電流半導體元件,其中,隔離溝槽內填充設置有一層被動保護層。 A fixed current semiconductor device having a Schottky barrier according to the seventh aspect of the invention, wherein the isolation trench is filled with a passive protective layer. 如申請專利範圍第7項所述具備蕭特基能障之定電流半導體元件,其中,隔離溝槽係利用高台蝕刻製程所形成。 A fixed current semiconductor device having a Schottky barrier according to the seventh aspect of the invention, wherein the isolation trench is formed by a high etching process.
TW100127075A 2011-07-29 2011-07-29 Contant current semiconductor device with schottky barrier structure TWI422030B (en)

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TW100127075A TWI422030B (en) 2011-07-29 2011-07-29 Contant current semiconductor device with schottky barrier structure

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI267193B (en) * 2001-08-30 2006-11-21 Sanyo Electric Co Schottky barrier diode and process therefor
US20070210335A1 (en) * 2004-04-30 2007-09-13 The Furukawa Electric Co., Ltd. GaN SEMICONDUCTOR DEVICE
US20100258899A1 (en) * 2009-04-08 2010-10-14 Chih-Tsung Huang Schottky diode device with an extended guard ring and fabrication method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI267193B (en) * 2001-08-30 2006-11-21 Sanyo Electric Co Schottky barrier diode and process therefor
US20070210335A1 (en) * 2004-04-30 2007-09-13 The Furukawa Electric Co., Ltd. GaN SEMICONDUCTOR DEVICE
US20100258899A1 (en) * 2009-04-08 2010-10-14 Chih-Tsung Huang Schottky diode device with an extended guard ring and fabrication method thereof

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