TWI420637B - Package substrate - Google Patents
Package substrate Download PDFInfo
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- TWI420637B TWI420637B TW98135063A TW98135063A TWI420637B TW I420637 B TWI420637 B TW I420637B TW 98135063 A TW98135063 A TW 98135063A TW 98135063 A TW98135063 A TW 98135063A TW I420637 B TWI420637 B TW I420637B
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- Prior art keywords
- layer
- package substrate
- dielectric layer
- oxidation resistant
- circuit layer
- Prior art date
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- 239000000758 substrate Substances 0.000 title claims description 47
- 230000003647 oxidation Effects 0.000 claims description 24
- 238000007254 oxidation reaction Methods 0.000 claims description 24
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- -1 hydrogen compound Chemical class 0.000 claims description 6
- 239000012964 benzotriazole Substances 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 239000002861 polymer material Substances 0.000 claims description 5
- 125000001931 aliphatic group Chemical group 0.000 claims description 3
- 125000003354 benzotriazolyl group Chemical group N1N=NC2=C1C=CC=C2* 0.000 claims 1
- 239000010410 layer Substances 0.000 description 105
- 238000000034 method Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 description 4
- 230000003064 anti-oxidating effect Effects 0.000 description 3
- 239000003963 antioxidant agent Substances 0.000 description 3
- 230000003078 antioxidant effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明係有關一種封裝基板,尤指一種能提高產品可靠度之封裝基板。 The invention relates to a package substrate, in particular to a package substrate capable of improving product reliability.
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件高整合度(integration)及微型化(miniaturization)的封裝需求,以供更多主被動元件及線路載接,封裝基板亦逐漸由雙層電路板演變成多層線路板(multi-layer board),俾於有限的空間下運用層間連接技術(interlayer connection)以擴大封裝基板上可供利用的線路佈局面積,並能配合高線路密度之積體電路(integrated circuit)的使用需求,且降低封裝基板的厚度,而能達到封裝件輕薄短小及提高電性功能之目的。 With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the requirements of high integration and miniaturization of semiconductor packages for more active and passive components and lines, the package substrate has gradually evolved from a two-layer circuit board to a multilayer circuit board (multi- Layer board), which uses an interlayer connection to expand the layout area available on the package substrate in a limited space, and can be used in conjunction with a high line density integrated circuit. The thickness of the package substrate is reduced, and the package is light and thin, and the electrical function is improved.
而為符合封裝基板輕薄短小、多功能、高速度及高頻化的開發方向,封裝基板已朝向細線路及小孔徑發展。目前於封裝基板之增層製程中,為避免於熱循環製成中,該封裝基板中之介電層與銅線路之間產生剝離,常藉由柴氏法(Czochralski,CZ)或黑化製程於封裝基板之內層銅線路表面上形成粗糙面,亦即於該銅線路表面上生成一層均勻的氧化層,藉由該氧化層以改善內層銅線路之銅鍵結強度,以令介電層壓合於該銅線路後,藉以增加銅線路表面的粗糙度,俾能增強該介電層與銅線路之間的結合強度。 In order to meet the development direction of thin, versatile, high-speed and high-frequency packaging substrates, the package substrate has developed toward thin lines and small apertures. Currently, in the build-up process of the package substrate, in order to avoid the thermal cycle, the dielectric layer and the copper line in the package substrate are peeled off, often by Czochralski (CZ) or blackening process. Forming a rough surface on the surface of the inner copper channel of the package substrate, that is, forming a uniform oxide layer on the surface of the copper line, and the oxide layer is used to improve the copper bonding strength of the inner copper line to make the dielectric After lamination is combined with the copper line, the roughness of the surface of the copper line is increased, and the bonding strength between the dielectric layer and the copper line can be enhanced.
請參閱第1A及1C圖,係為習知封裝基板之內層銅線路表面形成氧化層以提高粗糙度的製法。 Please refer to FIGS. 1A and 1C for a method of forming an oxide layer on the surface of the inner copper channel of a conventional package substrate to improve the roughness.
如第1A圖所示,首先,提供一表面具有線路層11之基板本體10,且該線路層11具有複數導電跡線110及複數電性接觸墊111,又形成該線路層11之材料係為銅。 As shown in FIG. 1A, first, a substrate body 10 having a circuit layer 11 on its surface is provided, and the circuit layer 11 has a plurality of conductive traces 110 and a plurality of electrical contact pads 111, and the material layer of the circuit layer 11 is formed. copper.
如第1B圖所示,接著,進行CZ或黑化製程,以於該線路層11之全部外露表面上形成粗糙面12。 As shown in FIG. 1B, a CZ or blackening process is then performed to form a rough surface 12 on all exposed surfaces of the wiring layer 11.
如第1C圖所示,最後,於該基板本體10與粗糙面12上形成介電層13,且該介電層13中形成複數開孔130,以令各該電性接觸墊111外露於各該開孔130中;其中,形成該介電層13之材料係為環氧樹脂。 As shown in FIG. 1C, a dielectric layer 13 is formed on the substrate body 10 and the rough surface 12, and a plurality of openings 130 are formed in the dielectric layer 13 to expose the electrical contact pads 111 to the respective layers. The opening 130 is formed; wherein the material forming the dielectric layer 13 is an epoxy resin.
惟,習知封裝基板之製法中,當該線路層11之線寬與線距縮小時,經過粗糙化之線路層11,易受該粗糙面12之粗糙度影響,而造成線路層11之阻抗產生變化,或該導電跡線110產生斷裂、浮起等缺點,導致該封裝基板無法滿足細間距(fine pitch)之需求;另外,進行CZ或黑化製程的成本過高,因而降低經濟效益。 However, in the conventional method of manufacturing a package substrate, when the line width and the line pitch of the circuit layer 11 are reduced, the roughened circuit layer 11 is susceptible to the roughness of the rough surface 12, thereby causing the impedance of the circuit layer 11. The change, or the conductive trace 110 causes defects such as cracking and floating, which causes the package substrate to fail to meet the requirement of fine pitch; in addition, the cost of performing the CZ or blackening process is too high, thereby reducing economic efficiency.
因此,如何避免習知技術中,該線路層經CZ或黑化製程而產生上述之種種問題,實已成目前亟欲解決的課題。 Therefore, how to avoid the above-mentioned various problems caused by the CZ or the blackening process in the conventional technology has become a problem to be solved at present.
鑑於上述習知技術之種種缺失,本發明之一目的係提供一種能增強線路與介電層之結合力且滿足線路細間距需求之封裝基板。 In view of the above-mentioned various deficiencies of the prior art, it is an object of the present invention to provide a package substrate which can enhance the bonding force between a line and a dielectric layer and meet the fine pitch requirements of the line.
本發明之另一目的係提供一種能降低製造成本之封 裝基板。 Another object of the present invention is to provide a seal that can reduce manufacturing costs. Mount the substrate.
為達上述及其他目的,本發明揭露一種封裝基板,係包括:基板本體;線路層,係設於該基板本體上;抗氧化層,係形成於該線路層之外露表面上,且該抗氧化層含有氮;以及介電層,係設於該基板本體與抗氧化層上,令該抗氧化層之氮與該介電層中之原子形成鍵結,俾以增強該介電層與該抗氧化層之間的結合力。 To achieve the above and other objects, the present invention discloses a package substrate comprising: a substrate body; a circuit layer disposed on the substrate body; an oxidation resistant layer formed on the exposed surface of the circuit layer, and the oxidation resistance The layer contains nitrogen; and a dielectric layer is disposed on the substrate body and the oxidation resistant layer, such that nitrogen of the oxidation resistant layer forms a bond with atoms in the dielectric layer to enhance the dielectric layer and the anti-corrosion layer The bonding force between the oxide layers.
前述之封裝基板中,形成該線路層之材料係為銅,且該線路層具有複數導電跡線及複數電性接觸墊。 In the above package substrate, the material forming the wiring layer is copper, and the circuit layer has a plurality of conductive traces and a plurality of electrical contact pads.
前述之封裝基板中,較佳地,該抗氧化層係為含氮之脂肪族單環氫化物(Aliphatic single ring hydrogen compound)所形成者,如苯并三唑(Benzotriazole)。 In the above package substrate, preferably, the oxidation resistant layer is formed of a nitrogen-containing Aliphatic single ring hydrogen compound such as Benzotriazole.
前述之封裝基板中,該介電層係為高分子材料所形成者,較佳地,係為環氧樹脂所形成者。 In the above package substrate, the dielectric layer is formed of a polymer material, and preferably formed of an epoxy resin.
由上可知,本發明之封裝基板藉由該線路層上形成該抗氧化層,以藉由該抗氧化層與介電層之間的鍵結而增強該線路層與介電層之結合力,無須如習知藉由CZ或黑化製程,以於該線路層之外露表面上形成粗糙面,因此本發明可降低該線路層表面之粗糙度而減少線路層之阻值與阻抗變化,以有利於細間距製作,而達到增強線路與介電層之結合力且滿足細間距之需求之目的;再者,該抗氧化層易於形成,而能達到降低製造成本之目的。 As can be seen from the above, the package substrate of the present invention forms the anti-oxidation layer on the circuit layer to enhance the bonding force between the circuit layer and the dielectric layer by bonding between the oxidation resistant layer and the dielectric layer. There is no need to use a CZ or blackening process to form a rough surface on the exposed surface of the circuit layer. Therefore, the present invention can reduce the roughness of the surface of the circuit layer and reduce the resistance and impedance change of the circuit layer to facilitate It is made at a fine pitch to achieve the purpose of enhancing the bonding force between the wiring and the dielectric layer and satisfying the requirement of fine pitch; further, the oxidation resistant layer is easy to form, and the manufacturing cost can be reduced.
以下藉由特定的具體實施例說明本發明之實施方 式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The embodiments of the present invention are described below by way of specific embodiments. Other advantages and effects of the present invention will be readily apparent to those skilled in the art from this disclosure.
請參閱第2A至2C圖,係為本發明所揭露之一種封裝基板之製法。 Please refer to FIGS. 2A-2C , which are a method for fabricating a package substrate according to the present invention.
如第2A圖所示,提供一表面具有線路層21之基板本體20,且該線路層21具有複數導電跡線210及複數電性接觸墊211,又形成該線路層21之材料係為銅。 As shown in FIG. 2A, a substrate body 20 having a circuit layer 21 on its surface is provided, and the circuit layer 21 has a plurality of conductive traces 210 and a plurality of electrical contact pads 211. The material of the circuit layer 21 is copper.
如第2B圖所示,於該線路層21之全部外露表面上形成含氮之抗氧化層22,例如:該抗氧化層22係為含氮之脂肪族單環氫化物(Aliphatic single ring hydrogen compound)所形成者,如苯并三唑(Benzotriazole)。該苯并三唑之化學結構式如下:
如第2C圖所示,於該基板本體20與抗氧化層22上形成介電層23,且該介電層23中形成複數開孔230,以令各該電性接觸墊211對應外露於各該開孔230中。該介電層23係為高分子材料所形成者,例如:該高分子材料可為如環氧樹脂者。 As shown in FIG. 2C, a dielectric layer 23 is formed on the substrate body 20 and the oxidation resistant layer 22, and a plurality of openings 230 are formed in the dielectric layer 23, so that the respective electrical contact pads 211 are exposed to each other. The opening 230 is in the middle. The dielectric layer 23 is formed of a polymer material. For example, the polymer material may be, for example, an epoxy resin.
如第2C’圖所示,該抗氧化層22中之氮22a係與該介電層23中之原子23a形成鍵結K,以藉由該鍵結K增強該介電層23與該抗氧化層22之間的結合力,俾能增加該 介電層23與線路層21之間的結合強度,以避免該介電層23與線路層21之間於熱循環製程中產生剝離。 As shown in FIG. 2C', the nitrogen 22a in the oxidation resistant layer 22 forms a bond K with the atom 23a in the dielectric layer 23 to enhance the dielectric layer 23 and the oxidation resistance by the bonding K. The bonding force between the layers 22 can increase the The bonding strength between the dielectric layer 23 and the wiring layer 21 prevents the dielectric layer 23 and the wiring layer 21 from being peeled off during the thermal cycle process.
本發明於該線路層21上壓合該介電層23前,令該線路層21先經過抗氧化劑處理,以令該線路層21與該介電層23之間產生鍵結K,而能提高結合力而避免該線路層21與介電層23產生剝離,俾以增加產品之可靠度;再者,相較於習知技術,本發明不僅降低該線路層21表面之粗糙度,以有效減少導電跡線210之阻值與阻抗變化,且因受粗糙度之影響極小,而有利於該線路層21之細間距需求;又該抗氧化層22之材料易於製作,故可大幅減少成本而符合經濟效益。 Before the dielectric layer 23 is pressed onto the circuit layer 21, the circuit layer 21 is first treated with an antioxidant to cause a bond K between the circuit layer 21 and the dielectric layer 23, thereby improving The bonding force avoids the peeling of the circuit layer 21 and the dielectric layer 23 to increase the reliability of the product; furthermore, the present invention not only reduces the roughness of the surface of the circuit layer 21, but also effectively reduces the roughness of the circuit layer 21 compared with the prior art. The resistance and impedance of the conductive traces 210 vary, and are affected by the roughness, which is advantageous for the fine pitch requirement of the circuit layer 21. The material of the oxidation resistant layer 22 is easy to manufacture, so the cost can be greatly reduced. Economic benefits.
本發明係提供一種封裝基板,係包括:基板本體20、設於該基板本體20上之線路層21、附著於該線路層21之外露表面上的抗氧化層22、以及設於該基板本體20與抗氧化層22上之介電層23;其中,該抗氧化層22係含有氮並與該介電層23中之原子形成鍵結K,以增強該介電層23與該抗氧化層22之間的結合力。 The present invention provides a package substrate, comprising: a substrate body 20, a circuit layer 21 disposed on the substrate body 20, an oxidation resistant layer 22 attached to the exposed surface of the circuit layer 21, and a substrate body 20 disposed on the substrate body 20. And a dielectric layer 23 on the oxidation resistant layer 22; wherein the oxidation resistant layer 22 contains nitrogen and forms a bond K with atoms in the dielectric layer 23 to enhance the dielectric layer 23 and the oxidation resistant layer 22 The bond between the two.
所述之線路層21具有複數導電跡線210及複數電性接觸墊211,且形成該線路層21之材料係為銅。 The circuit layer 21 has a plurality of conductive traces 210 and a plurality of electrical contact pads 211, and the material forming the circuit layer 21 is copper.
所述之抗氧化層22係為含氮22a之脂肪族單環氫化物(Aliphatic single ring hydrogen compound)所形成者,如苯并三唑(Benzotriazole)。 The anti-oxidation layer 22 is formed by an aliphatic single ring hydrogen compound containing nitrogen 22a, such as Benzotriazole.
所述之介電層23係為高分子材料所形成者,較佳地,係為環氧樹脂所形成者。 The dielectric layer 23 is formed of a polymer material, and is preferably formed of an epoxy resin.
綜上所述,本發明之封裝基板於該線路層上形成該抗氧化層,以藉由該抗氧化層與介電層之間的鍵結而增強該線路層與介電層之結合力,而無須如習知藉由CZ或黑化製程,以於該線路層之外露表面上形成粗糙面,因此本發明可降低該線路層表面之粗糙度而減少線路層之阻值與阻抗變化,並有利於細間距製作,而達到增強線路與介電層之結合力且滿足細間距之需求之目的;再者,該抗氧化層易於形成,而能達到降低製造成本之目的。 In summary, the package substrate of the present invention forms the anti-oxidation layer on the circuit layer to enhance the bonding force between the circuit layer and the dielectric layer by bonding between the oxidation resistant layer and the dielectric layer. Therefore, it is not necessary to form a rough surface on the exposed surface of the circuit layer by a CZ or blackening process, so that the present invention can reduce the roughness of the surface of the circuit layer and reduce the resistance and impedance change of the circuit layer, and It is advantageous for fine pitch fabrication, and achieves the purpose of enhancing the bonding force between the wiring and the dielectric layer and meeting the requirement of fine pitch; further, the oxidation resistant layer is easy to form, and the manufacturing cost can be reduced.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
10,20‧‧‧基板本體 10,20‧‧‧Substrate body
11,21‧‧‧線路層 11, 21‧‧‧ circuit layer
110,210‧‧‧導電跡線 110,210‧‧‧ conductive traces
111,211‧‧‧電性接觸墊 111,211‧‧‧Electrical contact pads
12‧‧‧粗糙面 12‧‧‧Rough surface
13,23‧‧‧介電層 13,23‧‧‧ dielectric layer
130,230‧‧‧開孔 130,230‧‧‧ openings
22‧‧‧抗氧化層 22‧‧‧Antioxidant layer
22a‧‧‧氮 22a‧‧‧Nitrate
23a‧‧‧原子 23a‧‧‧Atomic
K‧‧‧鍵結 K‧‧‧ Bond
第1A至1C圖係為習知封裝基板之製法之示意圖;以及第2A至2C圖係為本發明封裝基板之製法之示意圖;其中,第2C’圖係為局部放大示意圖。 1A to 1C are schematic views showing a method of manufacturing a conventional package substrate; and Figs. 2A to 2C are schematic views showing a method of manufacturing the package substrate of the present invention; wherein the 2C' is a partially enlarged schematic view.
20‧‧‧基板本體 20‧‧‧Substrate body
21‧‧‧線路層 21‧‧‧Line layer
210‧‧‧導電跡線 210‧‧‧ conductive traces
211‧‧‧電性接觸墊 211‧‧‧Electrical contact pads
22‧‧‧抗氧化層 22‧‧‧Antioxidant layer
23‧‧‧介電層 23‧‧‧Dielectric layer
230‧‧‧開孔 230‧‧‧ openings
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98135063A TWI420637B (en) | 2009-10-16 | 2009-10-16 | Package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98135063A TWI420637B (en) | 2009-10-16 | 2009-10-16 | Package substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201115708A TW201115708A (en) | 2011-05-01 |
| TWI420637B true TWI420637B (en) | 2013-12-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW98135063A TWI420637B (en) | 2009-10-16 | 2009-10-16 | Package substrate |
Country Status (1)
| Country | Link |
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| TW (1) | TWI420637B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6614663B1 (en) * | 1998-07-29 | 2003-09-02 | Hitachi, Ltd. | Reducing impedance of power supplying system in a circuit board by connecting two points in one of a power supply pattern and a ground pattern by a resistive member |
| US6764931B2 (en) * | 2001-08-24 | 2004-07-20 | Shinko Electric Industries Co., Ltd. | Semiconductor package, method of manufacturing the same, and semiconductor device |
| US20070194432A1 (en) * | 2006-02-23 | 2007-08-23 | Hsing-Chou Hsu | Arrangement of non-signal through vias and wiring board applying the same |
| TW200822302A (en) * | 2006-11-07 | 2008-05-16 | Unimicron Technology Corp | Package substrate having embedded capacitor |
| TW200837908A (en) * | 2007-03-09 | 2008-09-16 | Advanced Semiconductor Eng | Package substrate stripe, metal surface treatment method thereof and chip package structure |
-
2009
- 2009-10-16 TW TW98135063A patent/TWI420637B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6614663B1 (en) * | 1998-07-29 | 2003-09-02 | Hitachi, Ltd. | Reducing impedance of power supplying system in a circuit board by connecting two points in one of a power supply pattern and a ground pattern by a resistive member |
| US6764931B2 (en) * | 2001-08-24 | 2004-07-20 | Shinko Electric Industries Co., Ltd. | Semiconductor package, method of manufacturing the same, and semiconductor device |
| US20070194432A1 (en) * | 2006-02-23 | 2007-08-23 | Hsing-Chou Hsu | Arrangement of non-signal through vias and wiring board applying the same |
| TW200822302A (en) * | 2006-11-07 | 2008-05-16 | Unimicron Technology Corp | Package substrate having embedded capacitor |
| TW200837908A (en) * | 2007-03-09 | 2008-09-16 | Advanced Semiconductor Eng | Package substrate stripe, metal surface treatment method thereof and chip package structure |
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| Publication number | Publication date |
|---|---|
| TW201115708A (en) | 2011-05-01 |
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