TWI419110B - Image display systems and methods for driving pixel array - Google Patents

Description

Image display system and pixel array driving method

The present invention relates to an image display system, and more particularly to a source driver.

In an image display system, more than one source driver can be fixed on a pixel array of a glass substrate for transmitting a data signal to a data line to drive the pixel array.

In order to reduce costs and downsize, a smaller size source driver is required.

The present invention discloses an image display system having a small-sized source driver.

According to an embodiment of the invention, the source driver comprises a first digit to analog converter, a second digit to analog converter, a first switching circuit and a second switching circuit. The first digit to analog converter is used to convert the N-bit digital code into a first analog signal, where N is a positive integer. A second digit to analog converter is used to convert the K bit digital code into a second analog signal, where K is a positive integer and less than N. The first switching circuit controls a coupling relationship between the first display data, the second display data, and the first and second digits to the analog converter. The second switching circuit controls the first and second analog signals and the connection relationship between the first operational amplifier and the second operational amplifier, wherein the first operational amplifier is coupled to the first data line of the pixel array, and the second operational amplifier is coupled Connect to the second data line of the pixel array.

In the above embodiment, the first and second display materials all have N bits. The invention also discloses a control method of the first and second switching circuits. According to an embodiment of the invention, the control mechanism comprises at least two modes. The first switching circuit is configured to couple all the bits of the first display data to the first digit to the analog converter and couple the second display data in a first time interval of one of the first columns of the scanning pixel array The K most significant bits to the second digit to the analog converter. The second switching circuit is controlled to connect the first analog signal to the first operational amplifier and to connect the second analog signal to the second operational amplifier. After the first time interval, and in one of the first time intervals of the first column of the scan pixel array, the first switching circuit is controlled to couple all the bits of the second display data to the first digit to the analog converter. And the second switching circuit is controlled to connect the first analog signal to the second operational amplifier.

In the first time interval, the pixels in the first column and connected to the first data line are directly charged to their target voltage, and the pixels in the first column and connected to the second data line are only precharged to their target voltage. Median. In the second time interval, the pixels in the first column and connected to the first data line do not need to be charged, and the source driver is dedicated to the pixel in the first column and connected to the second data line from the middle of its target voltage. The value is charged to its target voltage.

In order to make the manufacturing, operating methods, objects and advantages of the present invention more apparent, the following detailed description of the preferred embodiments and the accompanying drawings

Example:

1 shows an image display system 100 including a source driver 102, a gate driver 104, and a pixel array 106 in accordance with an embodiment of the present invention. The gate driver 104 is used to control the process of scanning the pixel array 106. The source driver 102 transmits the material signals Data1, Data2, Data3, ..., Data2M (as shown in FIG. 3) to the pixel array 106 through the data lines DL1, DL2, DL3, ..., DL2M, respectively. In this embodiment, the source driver 102 controls the pixel array 106 to display images according to a column inversion technique, wherein the column inversion technique is such that pixels on the same column are controlled by voltages having the same polarity, and Pixels on one adjacent column are controlled by voltages of opposite polarity.

Figure 2 shows the concept of voltage polarity as described above. As shown, the voltages of the data signals Data1, Data2, Data3, ... Data2M transmitted by the data lines DL1, DL2, DL3, ..., DL2M can be allowed to be distributed over a voltage range of the supply voltage VDD to the ground voltage GND. . A common voltage VCOM can be between the supply voltage VDD and the ground voltage GND. The voltage between the common voltage VCOM and the supply voltage VDD can be regarded as a positive polarity (labeled as +) voltage, and the voltage between the common voltage VCOM and the ground voltage GND can be regarded as a negative polarity ( Negative polarity, labeled as -) voltage.

Figure 3 is a block diagram showing a source driver 102 in accordance with an embodiment of the present invention. The source driver 102 includes a plurality of channels 302_1, 302_2...302_M. Each channel receives two pieces of display data (digits) for the two data lines of the pixel array 106, and outputs two data signals (analog). For example, two pieces of display data IN1 and IN2 are transmitted to the channel 302_1 for being converted into two data signals Data1 and Data2 for transmission to the data lines DL1 and DL2. Similarly, the two pieces of display data IN3 and IN4 are transmitted to the channel 302_2 for conversion into two data signals Data3 and Data4 for transmission to the data lines DL3 and DL4. As for the rightmost channel 302_M of the source driver 102, the two pieces of display data IN(2M-1) and IN2M are converted into two data signals Data(2M-1) and Data2M for transmission to the data line DL(2M-1). With DL2M.

Figure 4 is a diagram showing an example of a channel in accordance with an embodiment of the present invention. The channel 400 includes four digital-to-analog converters (DACs) 402_1, 402_2, 402_3, and 402_4, a first switching circuit 404 and a second switching circuit 406, and may further include a first operational amplifier. OP1 and second operational amplifier OP2, latches 408_1-408_4 and voltage level shifters 410_1-410_4. The operational amplifiers OP1 and OP2 may be rail-to-rail operational amplifiers, and in other embodiments, the first and second operational amplifiers OP1 and OP2 may be disposed outside of the source driver 102. The latches 408_1-408_4 and the voltage level shifters 410_1-410_4 may be disposed after the first switching circuit 404 and before the digital to analog converters 402_1-402_4, and are optional devices.

The digital to analog converter 402_1 is configured to convert an N-bit digital code into an analog signal S1, where N is a positive integer. The digital to analog converter 402_2 is used to convert a K-bit digital code into an analog signal S2, where K is a positive integer and less than N. The digital to analog converter 402_3 has the same resolution as the digital to analog converter 402_1 for converting an N-bit digital code into an analog signal S3. The digital to analog converter 402_4 has the same resolution as the digital to analog converter 402_2 for converting a K bit digital code into an analog signal S4. The digital to analog converters 402_1 and 402_2 are positive polarity converters (hence labeled PDAC), and the voltages of the analog signals S1 and S2 are distributed across a common voltage (such as VCOM shown in FIG. 2) and a supply voltage ( A first voltage range between VDD) as shown in Figure 2. The digital to analog converters 402_3 and 402_4 are negative polarity converters (hence the designation NDAC), and the voltages of the analog signals S3 and S4 generated are distributed between the common voltage (such as VCOM shown in FIG. 2) and the ground voltage ( A second voltage range between GND as shown in Figure 2. It is worth noting that the digital to analog converters 402_2 and 402_4 are specifically designed to have lower resolution than analog to analog converters 402_1 and 402_3 (since K < N). Thus, the digital to analog converters can have the same resolution as compared to conventional source drivers, and the source driver 102 can have a smaller size. In some embodiments, N can be 64 and K can be 4.

In the following discussion, to simplify the description, portions of the latches 408_1-408_4 and the voltage level shifters 410_1-410_4 will be omitted. The first switching circuit 404 can determine how to couple the first display material IN1 and the second display material IN2 to the input terminals of the digital to analog converters 402_1, 402_2, 402_3 and 402_4. The second switching circuit 406 controls the connection relationship between the output of the digital to analog converters 402_1, 402_2, 402_3, and 402_4 and the inputs of the first operational amplifier OP1 and the second operational amplifier OP2. The first and second switching circuits 404 and 406 are controlled by at least one control signal CS. The 5A to 5D drawings show different connection results controlled by the first and second switching circuits 404 and 406.

Figure 5A shows the first connection mode provided by the first and second switching circuits 404 and 406. As shown, the first switching circuit 404 couples all the bits IN1[0:(N-1) of the first display data to the digital to analog converter 402_1, and couples the K most of the second display data. Most significant bits IN2[((NK):(N-1))]) to digital to analog converter 402_2. The second switching circuit 406 connects the analog signal S1 to the first operational amplifier OP1, and connects the analog signal S2 to the second operational amplifier OP2. The first data signal Data1 is generated at the output of the first operational amplifier OP1 and is transmitted to the first data line of the pixel array (such as DL1 shown in FIG. 1). The second data signal Data2 is generated at the output of the second operational amplifier OP2 and is transmitted to the second data line of the pixel array (such as DL2 shown in FIG. 1). A positive polarity voltage is supplied to the first and second data lines DL1 and DL2. In the first connected mode, the digital to analog converters 402_3 and 402_4 have no effect.

Figure 5B shows the second connection mode provided by the first and second switching circuits 404 and 406. As shown, the first switching circuit 404 is coupled to all of the bits IN2[0:(N-1)] of the second display data to the digital to analog converter 402_1, and the second switching circuit 406 transmits the analog signal S1 to The second operational amplifier OP2 is used to generate the second data signal Data2 such that a positive polarity voltage can be supplied to the second data line DL2 as shown in FIG. In the second connection mode, the digital to analog converters 402_2, 402_3, 402_4 and the first operational amplifier OP1 have no effect.

Figure 5C shows the third connection mode provided by the first and second switching circuits 404 and 406. As shown, the first switching circuit 404 couples all the bits IN1[0:(N-1) of the first display material to the digital to analog converter 402_3, and couples the K most of the second display data. Most significant bits IN2[((NK):(N-1))]) to digital to analog converter 402_4. The second switching circuit 406 is connected to the analog signal S3 to the first operational amplifier OP1 for generating the first data signal Data1, and is connected to the analog signal S4 to the second operational amplifier OP2 for generating the second data signal Data2. The negative polarity voltage is supplied to the first and second data lines DL1 and DL2 (refer to FIG. 1) for respectively transmitting the data signals Data1 and Data2. In the third connected mode, the digital to analog converters 402_1 and 402_2 have no effect.

The 5D diagram shows the fourth connection mode provided by the first and second switching circuits 404 and 406. As shown, the first switching circuit 404 is coupled to all of the bits IN2[0:(N-1)] of the second display data to the digital to analog converter 402_3, and the second switching circuit 406 transmits the analog signal S3 to The second operational amplifier OP2 is configured to generate the second data signal Data2 such that a negative polarity voltage can be supplied to the second data line DL2 as shown in FIG. In the fourth connection mode, the digital to analog converters 402_1, 402_2, 402_4 and the first operational amplifier OP1 do not function.

Figure 6A shows the source of at least one control signal CS used to control the first and second switching circuits 404 and 406 of the channel 400. As shown, image display system 600 includes a channel 400 and a control circuit 602. The control circuit 602 generates a signal TP1' based on the horizontal synchronizing signal TP1 to form at least one control signal CS accompanied by a polarity bit POL. The horizontal sync signal TP1 and the polarity bit POL are provided by a timing controller (not shown, but are well known in the art). The horizontal synchronization signal TP1 is used to distinguish the columns of the display data of the pixel array. The polarity bit POL shows the polarity of the scan column. In some embodiments, control circuit 602 can be built into the timing controller. On the other hand, in some embodiments, control circuit 602 can be built into the source driver (including channel 400) rather than being built into the timing controller. In other embodiments, control circuit 602 can be one of a timing controller and a source external to the source driver.

According to the control signals POL and TP1' as shown in Fig. 6A, Fig. 6B shows the mechanism of the first switching circuit 404 and the second switching circuit 406 of the control channel 400 using a waveform diagram. First, the function of the horizontal synchronization signal TP1 and the polarity bit POL when the column inversion technique is applied will be discussed first. According to the first pulse of the horizontal synchronization signal TP1, a time interval Trow1 may be provided for scanning the first column of one of the pixel arrays, and the state of the polarity bit POL may indicate that the positive polarity voltage must be applied to the first column of pixels. Upper to perform positive polarity drive. At this time, the display material IN1 includes a first digit value to be displayed by the first pixel (located in the first column and coupled to the data line DL1 as shown in FIG. 1), and the display material IN2 contains the second pixel to be located (located The first column is coupled to the second digit value displayed by the data line DL2) as shown in FIG. According to the second pulse of the horizontal synchronization signal TP1, a time interval Trow2 may be provided for scanning the second column of one of the pixel arrays, and the state of the polarity bit POL may indicate that the negative polarity voltage must be applied to the second column of pixels. Above, to perform negative polarity drive. At this time, the display material IN1 includes a third digit value to be displayed by the third pixel (located in the second column and coupled to the data line DL1 as shown in FIG. 1), and the display material IN2 contains the fourth pixel to be located (located at The second column is coupled to the fourth digit value displayed by the data line DL2) as shown in FIG. A control signal including a polarity bit POL and a signal TP1' as shown in FIG. 6A is correspondingly applied to the first switching circuit 404 and the second switching circuit 406 of the control channel 400, and the first and second, The third and fourth connection modes (as shown in Figures 5A-5D) are generated in four time intervals T1-T4 (as shown in Figure 6B), respectively. Referring to the explanatory text on the waveforms of the data signals Data1 and Data2 shown in FIG. 6B, it is shown that in the first time interval T1, the content of the data signal Data1 comes from the digital to analog converter (N-to-1). PDAC) 402_1, and the content of the data signal Data2 is from the digital to analog converter (K-to-1 PDAC) 402_2, so that the voltage level of the data signal Data1 is charged to the first digital value (included in the display data IN1) The target voltage, and at this time, the voltage level of the data signal Data2 is only precharged to the intermediate value of the voltage level of the second digit value (included in the display data IN2); in the second time interval T2, the data signal Data1 is not Change, and at this time, the content of the data signal Data2 comes from the digital to analog converter (N-to-1 PDAC) 402_1 to compensate for the shortage of the second digit value; in the third time interval T3, the content of the data signal Data1 comes from The digital to analog converter (N-to-1 NDAC) 402_3, and the content of the data signal Data2 comes from the digital to analog converter (K-to-1 NDAC) 402_4, so that the voltage level of the data signal Data1 is charged to the first The target voltage of the three-digit value, and this The voltage level of the data signal Data2 is only precharged to the intermediate value of the voltage level of the fourth digit value; in the fourth time interval T4, the data signal Data1 is not changed, and the content of the data signal Data2 is from the digit. To the analog converter (N-to-1 NDAC) 402_3 to compensate for the lack of the fourth digit value.

Figure 7A shows another source for controlling at least one control signal CS of the first and second switching circuits of channel 400. As shown, image display system 700 includes a channel 400 and a control circuit 702. The control circuit 702 generates a signal POL' according to the polarity bit POL to form at least one control signal CS for controlling the first switching circuit 404 and the second switching circuit 406 of the channel 400. In some embodiments, control circuit 702 can be built into the timing controller to provide horizontal sync signal TP1 and polarity bit POL. On the other hand, in some embodiments, control circuit 702 can be built into the source driver (including channel 400) rather than being built into the timing controller. In other embodiments, control circuit 702 can be one of a timing controller and a source external to the source driver. It is worth noting that when the control circuit 702 is not built into the source driver, the source driver may require an extra pin to receive the signal POL'.

According to the control signal POL' as shown in Fig. 7A, Fig. 7B shows the mechanism of the first switching circuit 404 and the second switching circuit 406 of the control channel 400 using a waveform diagram. As shown, the first switching circuit 404 and the second switching circuit 406 of the channel 400 are controlled by a control signal POL', the first, second, third, and fourth connection modes (eg, 5A-5D) The display will be generated in four time intervals T1-T4 (as shown in FIG. 7B) to implement the above column inversion technique.

In summary, in the pre-charging procedure described (provided by the digital-to-analog converter (K-to-1 PDAC) 402_2 and (K-to-1 NDAC) 402_4), each channel allows the resolution to be used. Low digit to analog converter. For example, in conventional column inversion techniques, in order to achieve a smooth display, one of the channels serving the two data lines typically requires at least four high resolution digital to analog converters. However, in channel 400, a smooth display is still achievable, and only two high-resolution digital to analog converters are needed, including digital to analog converters (N-to-1 PDAC) 402_1 and (N-to- 1 NDAC) 402-3, while the remaining two digit-to-analog converters can be used with low-resolution digital to analog converters (including digital to analog converters (K-to-1 PDAC) 402_2 and (K-to- 1 NDAC) 402-4) to complete. Therefore, the circuit size and cost of the source driver can be greatly reduced.

In addition, the connection established by the first switching circuit and the second switching circuit can also be completed by software instead of electronic circuit. The method of controlling the coupling relationship between the display data, the digital to analog converter and the operational amplifier is also included in the scope of the present invention.

The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 600, 700. . . Image display system

102. . . Source driver

104. . . Gate driver

106. . . Pixel array

302_1, 302_2, 302_M, 400. . . aisle

402_1, 402_2, 402_3, 402_4, K-to-1 NDAC, N-to-1

NDAC, K-to-1 PDAC, N-to-1 PDAC. . . Digital to analog converter

404. . . First switching circuit

406. . . Second switching circuit

408_1, 408_2, 408_3, 408_4. . . Latch

410_1, 410_2, 410_3, 410_4. . . Voltage level shifter

602, 702. . . Control circuit

CS, S1, S2, S3, S4, TP1, TP1'. . . signal

Data1, Data2, Data3, Data4, Data(2M-1), Data2M. . . Data signal

DL1, DL2, DL3, DL2M. . . Data line

GND, VCOM, VDD. . . Voltage

IN1, IN1[0:(N-1)], IN2, IN2[0:(N-1)], IN2[((NK):(N-1))], IN3, IN4, IN(2M-1) ), IN2M. . . Display data

OP1, OP2. . . Operational Amplifier

POL, POL’. . . Polar bit

T1, T2, T3, T4, Trow1, Trow2. . . Time interval

1 is a view showing an image display system according to an embodiment of the present invention.

Figure 2 shows the concept of voltage polarity.

Figure 3 is a block diagram showing a source driver in accordance with an embodiment of the present invention.

Figure 4 is a diagram showing an example of a channel in accordance with an embodiment of the present invention.

Figures 5A through 5D show four different connection modes controlled by the first and second switching circuits.

Figure 6A shows the source of at least one control signal CS used to control the first and second switching circuits of channel 400.

Fig. 6B is a diagram showing signal waveforms when the first and second switching circuits of the control signal CS control channel 400 as shown in Fig. 6A are applied.

Figure 7A shows another source for controlling at least one control signal CS of the first and second switching circuits of channel 400.

Fig. 7B is a diagram showing signal waveforms when the first and second switching circuits of the control signal CS control channel 400 as shown in Fig. 7A are applied.

100. . . Image display system

102. . . Source driver

104. . . Gate driver

106. . . Pixel array

DL1, DL2, DL3, DL2M. . . Data line

Claims (14)

An image display system includes a source driver, wherein the source driver includes: a first digit to analog converter for converting an N-bit digital code into a first analog signal, wherein N is a positive integer a second digit to analog converter for converting a K-bit digital code into a second analog signal, wherein K is a positive integer and less than N; a first switching circuit controls a first display data, a second display data and a coupling relationship between the first and the second digits to the analog converter, wherein the first and the second display materials both have N bits; and a second switching circuit that controls the First and the second analog signal and a connection relationship between the first operational amplifier and a second operational amplifier; wherein: the first operational amplifier is coupled to one of the first data lines of a pixel array, and the second An operational amplifier is coupled to a second data line of the pixel array; and in a first time interval of scanning one of the first columns of the pixel array, the first switching circuit is coupled to all the bits of the first display data to the a digital to analog converter, and coupled to the K most significant bits of the second display data to the second digital to analog converter, and the second switching circuit connects the first analog signal to the first operational amplifier And connecting the second analog signal to the second operational amplifier; and after the first time interval, and scanning a second time interval of the first column of the pixel array, the first switching circuit is coupled to the Second display All bits of the data are shown to the first digit to the analog converter, and the second switching circuit connects the first analog signal to the second operational amplifier. The image display system of claim 1, further comprising: a third digit to analog converter for converting a N-bit digital code into a third analog signal; and a fourth digit to analogy a converter for converting a K-bit digital code into a fourth analog signal; wherein the first and the second digital-to-analog converters limit the first and second analog signals when performing a positive polarity display a first voltage range; the third and the fourth digits to the analog converter limit the third and fourth analog signals to a second voltage range when performing the negative polarity display; the first switching circuit further controls the first a display data, a coupling relationship between the second display data and the third and fourth digits to the analog converter; and the second switching circuit further controls the third analog signal, the fourth analog signal and the a connection relationship between the first and the second operational amplifier. The image display system of claim 2, wherein: in scanning a third time interval of one of the second columns of the pixel array, the first switching circuit couples all the bits of the first display data to The third digit to the analog converter, and coupled to the K most significant bits of the second display material to the fourth digit to the analog converter, and the second switching circuit connects the third analog signal to the first An operational amplifier, and connecting the fourth analog signal to the second operational amplifier; and after the third time interval, and scanning the pixel array a fourth time interval of the second column, the first switching circuit is coupled to all the bits of the second display data to the third digit to the analog converter, and the second switching circuit connects the third analog signal to the The second operational amplifier. The image display system of claim 3, further comprising a timing controller for providing a horizontal synchronization signal, a polarity bit and a modified horizontal synchronization signal, wherein the timing controller is based on the level The sync signal generates the modified horizontal sync signal, and the modified horizontal sync signal and the polarity bit are applied to control the first and second switching circuits. The image display system of claim 3, further comprising a timing controller for providing a polarity bit and a modified polarity bit, wherein the timing controller generates the modification according to the polarity bit The polarity bit is passed, and the modified polarity bit is applied to control the first and second switching circuits. The image display system of claim 3, further comprising a timing controller for providing a horizontal synchronization signal and a polarity bit. The image display system of claim 6, wherein the source driver further comprises a control circuit for generating a modified horizontal synchronization signal according to the horizontal synchronization signal from the timing controller, according to the The modified horizontal sync signal and the polarity bit from the timing controller control the first and second switching circuits. The image display system of claim 6, wherein the source driver further comprises a control circuit for generating a modified polarity bit according to the polarity bit from the timing controller for controlling The First and second switching circuits. The image display system of claim 6, further comprising a control circuit coupled between the timing controller and the source driver, wherein the control circuit is based on the horizontal synchronization signal from the timing controller A modified horizontal sync signal is generated to control the first and second switching circuits in accordance with the modified horizontal sync signal and the polarity bit from the timing controller. The image display system of claim 6, further comprising a control circuit coupled between the timing controller and the source driver, wherein the control circuit is based on the polarity bit from the timing controller A modified polarity bit is generated for controlling the first and second switching circuits. The image display system of claim 1, wherein the first and second operational amplifiers are rail-to-rail operational amplifiers. A method for driving a pixel array for displaying an image, comprising: providing a first digit to analog converter for converting an N-bit digital code into a first analog signal, wherein N is a positive integer; a second digit to analog converter for converting a K-bit digital code into a second analog signal, wherein K is a positive integer and less than N; scanning one of the first columns of the pixel array The time interval is coupled to all the bits of the first display data to the first digit to the analog converter, and coupled to the K most significant bits of the second display data to the second digit to the analogy Converter, connect to the first class Comparing a signal to a first operational amplifier coupled to one of the first data lines of the pixel array, and connecting the second analog signal to a second operational amplifier coupled to one of the second data lines of the pixel array; After the first time interval, and in scanning a second time interval of the first column of the pixel array, all bits of the second display data are coupled to the first digit to the analog converter, and the The first analog signal is to the second operational amplifier. The method of claim 12, further comprising: providing a third digit to analog converter for converting a N-bit digital code into a third analog signal; and providing a fourth digit to analogy a converter for converting a K-bit digital code into a fourth analog signal; wherein the first and the second digital-to-analog converters limit the first and second analog signals when performing a positive polarity display a first voltage range; and the third and fourth digit to analog converters limit the third and fourth analog signals to a second voltage range when performing the negative polarity display. The method of claim 13, further comprising: scanning a third time interval of one of the second columns of the pixel array, coupling all bits of the first display data to the third digit to an analogy a converter, coupled with the K most important bits of the second display data to the fourth digit to the analog converter, connecting the third analog signal to the first operational amplifier, and connecting the fourth analog signal to the first a second operational amplifier; and after the third time interval, and in scanning a fourth time interval of the second column of the pixel array, coupling all bits of the second display data Transmitting the third digit to the analog converter and connecting the third analog signal to the second operational amplifier.