TWI418142B - Operational Amplifier - Google Patents

Description

Operational Amplifier

The present invention relates to analog circuits and, more particularly, to operational amplifiers.

Operational amplifiers are widely used in many analog circuits. In many applications, op amps are required to have a wide bandwidth, a high slew rate, and rail-to-rail operation over an operating voltage range of approximately 1.8 volts to 8 volts. Rail-to-rail op amps extend the dynamic range compared to general op amps, maximizing the overall performance of the amplifier. Rail-to-rail op amps have a wide input common-mode voltage range and output swing at low supply voltages and single supply voltages. The rail-to-rail input provides zero crossover distortion and is suitable for driving the ADC without differential linear attenuation for high precision applications.

It is an object of the present invention to provide a rail-to-rail operational amplifier that can have a wider bandwidth and a higher slew rate.

The object of the present invention is achieved by the following technical solution: an operational amplifier comprising: a power supply terminal; a ground terminal; an input stage, the input stage enables the operational amplifier to perform rail-to-rail operation; An intermediate stage is coupled to the input stage; and an output stage coupled to the intermediate stage.

The input stage includes: a first input port and a second input port; a first output port and a second output port; a first input NPN transistor, the first input NPN transistor including a base, a collector, and An emitter and the base connected to the first input port, the collector being connected to the power terminal; a first input PNP transistor, the first input PNP transistor comprising a base, a collector, and a shot And the base is connected to the first input port, the collector is connected to the second output port; the second input NPN transistor, the second input NPN transistor includes a base, a collector, and An emitter and the base connected to the second input port, the collector being coupled to the power terminal; and a second input PNP transistor, the second input PNP transistor including a base, a collector, and An emitter and the base are coupled to the second input port, the collector being coupled to the first output port.

The intermediate stage includes: a first intermediate stage input NPN transistor, the first intermediate stage input NPN transistor includes a base, a collector and an emitter, and the emitter is connected to the first output port; a second intermediate stage input NPN transistor, the second intermediate stage input NPN transistor includes a base, a collector and an emitter, and the base is connected to a base of the first intermediate stage input NPN transistor, Connecting the emitter to the second output port; a first node, a second node, and a third node; a first class AB buffer, the first class AB buffer inputting the first intermediate stage into an NPN transistor a collector connected to the first node; a second class AB buffer, the second class AB buffer connecting the collector of the second intermediate stage input NPN transistor to the second node; a resistor, the first resistor having a first turn and a second turn and the first turn connected to the first node, the second turn connected to the third node; and a second resistor, The second resistor has a first turn and a second turn and the first turn is connected to the second pass A second port connected to said third node.

Wherein, the output stage comprises: an output 埠; an output stage PNP driving a transistor, the output stage PNP driving transistor comprises a base, a collector and an emitter, and the emitter is connected to the power terminal, the base a pole connected to a collector of a first NPN transistor of the first class AB buffer, the collector being coupled to the output port; an output stage NPN driving a transistor, the output stage NPN driving transistor comprising a base a collector and an emitter connected to the ground, the base being coupled to a collector of a second PNP transistor of the first class AB buffer, the collector being coupled to the a first output stage PNP transistor, the first output stage PNP transistor comprising a base, a collector and an emitter, the emitter being coupled to the power supply terminal, the collector being coupled to the first a collector of a first NPN transistor of a class AB buffer; a second output stage PNP transistor, the second output stage PNP transistor comprising a base, a collector and an emitter and the emitter is coupled to the a collector of a first NPN transistor of the first class AB buffer, the collector being coupled to the first class AB buffer a collector of a second PNP transistor; a first output stage NPN transistor, the first output stage NPN transistor comprising a base, a collector, and an emitter, and the emitter is coupled to the ground, a collector connected to a collector of a second PNP transistor of the first class AB buffer; and a second output stage NPN transistor, the second output stage NPN transistor including a base, a collector, and an emitter And the emitter is coupled to a collector of a second PNP transistor of the first class AB buffer, the collector being coupled to a collector of a first NPN transistor of the first class AB buffer.

The present invention adopts the above structure, and improves the dynamic working range and bandwidth of the operational amplifier, as well as the conversion rate, so that the application range is wider.

Specific examples of preferred embodiments of the invention will be described herein with reference to the accompanying drawings. While the invention has been described in terms of the preferred embodiments, it is understood that the invention On the contrary, the invention is intended to cover alternatives, modifications and equivalents In addition, numerous specific details are set forth in the Detailed Description of the Detailed Description Of course, it will be apparent to those skilled in the art that the present invention may be practiced without departing from the specific details. In addition, the methods, the processes, the components, and the circuits well known in the art are not specifically described in order to clarify the subject matter of the present invention.

1, 2 and 3 illustrate circuit diagrams of rail-to-rail operational amplifiers in accordance with one embodiment of the present invention. Among them, 埠102 and 104 in Fig. 1 are input 埠 of the operational amplifier, and 埠106 in Fig. 3 is the output 埠 of the operational amplifier. One of the ports 102 and 104 is designated as the in-phase input port, and the other is designated as the inverting input port. In the particular embodiment illustrated in Figures 1, 2, and 3, input port 102 is an in-phase input port and input port 104 is an inverting input port.

1, 2 and 3 respectively show a portion of a particular embodiment which together form an embodiment. The electrical connection relationship is indicated by the letters "A", "B", "C" and "D" between Fig. 1, Fig. 2 and Fig. 3. The node "A" in Fig. 1 is connected to the "A" point in Fig. 2, the "B" in Fig. 1 is connected to the "B" point in Fig. 2, and so on.

The circuit shown in Figure 1 can be considered as an input stage or part of an input stage of an operational amplifier. This circuit acts as a rail-to-rail transconductance amplifier that converts the differential voltage between input 埠102 and 104 into a differential current between node A and node B.

The circuit of FIG. 1 includes differential pair transistors 108 and 110 and differential pair transistors 112 and 114. The input port 102 is coupled to the bases of the NPN transistor 108 and the PNP transistor 114, and the input port 104 is coupled to the bases of the NPN transistor 110 and the PNP transistor 112. The collectors of NPN transistors 108 and 110 are each coupled to a power supply terminal 116 (V _CC ) which forms a voltage follower such that the emitter voltages of transistors 108 and 110 follow the voltages at input ports 102 and 104, respectively.

The transistors 118 and 120 are used for impedance transformation to make the impedance seen from the collector of the PNP transistor 118 greater than the impedance seen from the emitter of the NPN transistor 108, respectively, and from the collector of the PNP transistor 120. The impedance that enters is greater than the impedance seen from the emitter of the NPN transistor 110. Thus, differential pair transistors 108 and 110 and transistors 118 and 120 do not introduce resistors at nodes 122 and 124, and can function to isolate the front and rear stages.

The base of transistor 118 is biased together by PNP transistor 126 and current source 130, while the base of transistor 120 is biased together by PNP transistor 128 and current source 130. In the embodiment shown in FIG. 1, current source 130 is a current sink that sinks current from the bases of transistors 126 and 128. The transistors 126 and 128 are connected like a diode, their bases are interconnected, their collectors are also interconnected, and their base and collector are connected to a current source 130. The emitters of transistors 126 and 128 are coupled to the emitters of transistors 118 and 120, respectively. Thus, the bases of transistors 118 and 120 are biased, and the large signal collector currents of transistors 118 and 120 are controlled by the device specifications of transistors 126, 128, respectively, relative to transistors 118 and 120, as well as by current source 130. Size control.

The emitters of PNP transistors 112 and 114 are biased by current sources 132 and 134, respectively. For the embodiment shown in Figure 1, current sources 132 and 134 provide equal amounts of current. The collectors of transistors 112 and 114 are coupled to nodes 122 and 124, respectively. Thus, the current at node 122 is the sum of the collector currents of transistors 112 and 118, and the current at node 124 is the sum of the collector currents of transistors 114 and 120.

The input-output transconductance relationship of the circuit shown in Figure 1 can be represented in a variety of forms. One form is to consider variations in the input and output signals with respect to their respective common mode signals. The common mode signal of a pair of signals is the arithmetic mean of the pair of signals, and the differential mode signal is the difference of the pair of signals. Thus, if respectively and Δ v _in V _in represents the input voltage differential mode and common mode input voltage between input nodes 102 and 104, the voltage at node 102 is input The voltage at the input node 104 is ; If I and Δ i respectively represent an output current of differential-mode and common mode output current between nodes 122 and 124, the current flowing into node 122 is The current flowing into node 124 is . The magnitude of the common mode output current I is determined by the transistor, the current source, and the common mode input voltage V _{in in} FIG.

The relationship between the differential mode output current Δ i and the differential mode input voltage Δ v _in can be expressed by a linear relationship Δ i = g _{m 1} Δ v _in , where g _{m 1} is the transconductance gain, the value of which depends on Figure 1 Characteristic parameters of the transistor pair in the circuit shown. This equation assumes that the transistors in each pair of transistors are perfectly matched. That is, the transistors 108 and 110 match each other and they have the same transconductance. Similarly, transistors 112 and 114, transistors 118 and 120, and transistors 126 and 128 also match each other. It should be understood that, in theory, the input-output relationship is not completely linear, but in practical applications, the above linear relationship has been well able to reflect the input-output relationship in this embodiment.

The circuit of Figure 1 is capable of rail-to-rail operation by employing differential pair transistors 108 and 110 as complementary transistors for differential pair transistors 112 and 114. If the input ports 102 and 104 between the common-mode input voltage V _in the ground near the end of the ground voltage 137, to the differential pair transistors 108 and 110, there is no sufficient margin to make it work, the differential pair transistors 112 and 114 can still work; the other hand, if the input ports 102 and 104 between the common-mode input voltage V _in close voltage (V _CC) at a supply terminal 116 for the differential pair transistors 112 and 114, there is no sufficient The margins allow it to work properly, while the differential pair transistors 108 and 110 still function properly. It can be seen that the rail-to-rail input stage circuit proposed by the present invention enables the operational amplifier to operate within the ground terminal voltage and the power supply terminal voltage range, thereby improving its dynamic operating range.

Referring to Fig. 2, the symbols "A" and "B" in Figs. 1 and 2 indicate that the emitter of the transistor 138 and the resistor 139 are both connected to the node 122, and the emitter of the transistor 140 and the resistor 141 are connected to the node. 124.

With I _o represents the current provided by the current source 142. For the particular embodiment illustrated in Figure 2, transistors 138 and 140 are matched to each other, resistors 139 and 141 are identical, and load resistors 144 and 146 are also identical. Thus, due to the symmetry of the circuit, the current flowing through resistors 139 and 141 is substantially equal, both I + The current flowing through the resistor 144 is - Δ i , the direction is the direction of flow to node 148; the current flowing through resistor 146 is +Δ i , the direction of which is the direction of flow to node 150. That is, the small signal current -Δ i flows through the resistor 144 toward the node 148, and the small signal current Δ i flows through the resistor 146 toward the node 150.

R _L represents the resistance values of load resistors 144 and 146, Δ v represents the differential mode voltage between nodes 148 and 150, and the small signal voltages at nodes 148 and 150 are respectively with . Using the above small signal current Δ i to represent the differential mode voltage Δ v , there are:

Δ v =2Δ iR _L =2 g _{m 1} R _L Δ v _in (1)

The circuit shown in Figure 2 can be viewed as an intermediate stage of the operational amplifier with inputs 埠 "A" and "B" and outputs 埠 nodes 204 and 206, labeled "C" and "D", respectively. The input signals input to 埠 "A" and "B" are the aforementioned differential mode output current Δ i , and the output signals of outputs 埠 "C" and "D" are current signals. The operational amplifier intermediate stage circuit shown in Figure 2 is a current amplifier whose current gain is expressed as g _I . The calculation of the current gain g _I is as follows.

Two class AB buffers B ₁ and B _2, respectively 150 and 148 are coupled to node 156 and node 172. Class AB buffer B ₁ includes transistors 152, 154, 186, 188, 160, and 200 and current sources 158 and 190. Where current source 158 provides a bias current to transistor 152 and transistor 160 provides a bias current to transistor 154. Current source 190 provides a bias current to transistor 186, which provides a bias current to transistor 188. Class AB buffer B ₂ includes transistors 164, 168, 192, 194, 162, and 202 and current sources 170 and 202. Where current source 170 provides a bias current to transistor 164 and transistor 162 provides a bias current to transistor 168. Current source 196 provides a bias current to transistor 192 and transistor 202 provides a bias current to transistor 194. Additionally, as shown, transistors 160 and 162 form a current mirror, and transistors 200 and 202 form a lower current mirror.

Class AB above two buffers B ₁ and B ₂ of the operational amplifier such that when the rail-to-rail operation, the voltage at nodes 156 and 172 and 148 are equal to the voltage at the node 150. Thus, the voltage difference between nodes 172 and 156 is equal to the voltage difference between nodes 148 and 150. Because node 150 is coupled to the base of transistor 152, the emitter of transistor 152 is coupled to the base of transistor 154, and the emitter of transistor 154 is coupled to node 156 such that it is incident from node 150 to transistor 152. The increased voltage across the poles is offset by the reduced voltage from the base of transistor 154 to node 156, such that node 150 and node 156 have the same voltage. Likewise, nodes 148 and 172 also have the same voltage.

In the intermediate stage circuit shown in Figure 2, resistors 182 and 184 are identical, and current sources 174 and 176 are matched to each other such that the current flowing through resistors 182 and 184 is the same, expressed as Δ i ^t . In the steady state, i.e., when the differential mode voltage at nodes 148 and 150 is zero, the differential mode voltage between nodes 172 and 156 is also zero, such that the current Δ i ^t flowing through resistors 182 and 184 is also zero. And because the two Class AB buffers B ₁ and B ₂ have symmetry, their upper and lower portions provide an equal amount of current. When the differential mode voltage between nodes 148 and 150 is not zero, the differential mode voltage between nodes 172 and 156 is also not zero, and the upper and lower portions of the class AB buffer provide more current than the current provided at steady state. Or to be small, such that the current flowing through resistors 182 and 184 is not Δ i ^t nor zero. Since the differential mode voltage between nodes 172 and 156 is equal to the differential mode voltage between nodes 148 and 150, it satisfies:

Δ v =2Δ i ^t R _E (2)

Where R _E is the resistance value of resistors 182 and 184.

The joint relationship (1) and (2), the current gain of the intermediate stage circuit shown in Figure 2 can be expressed as:

or

Visible by relations (3) and (4), by choosing large Increases current gain. Connecting the input stage circuit shown in Figure 1 to the intermediate stage circuit shown in Figure 2, the input-output relationship between the inputs 埠 "A" and "B" and the outputs 埠 "C" and "D" can be expressed as:

Δ i ^t = g _{m 1} g _I Δ v _in = g _m Δ v _in (5)

Where g _m = g _{m 1} g _I = The total gain of the cascade of the circuits shown in Figures 1 and 2.

The two class AB buffers B ₁ and B ₂ effectively convert the differential mode voltage Δ v between nodes 148 and 150 into a differential mode current Δ i ^t between nodes 172 and 156, which is composed of transistors 160 and 162 The upper current mirror and the lower current mirror mirror composed of transistors 200 and 202. Therefore, the voltage at points C and D will decrease or increase depending on the positive and negative of Δ v .

When Δ v is positive, the voltage at node 172 increases, the voltage of the node 156 decreases, the current 182 and 184 156, so that a larger via the resistor from node 172 to node 200 to provide the current transistors. This current is mirrored by a lower current mirror consisting of transistors 200 and 202. Therefore, the current supplied by transistor 202 is also greater, and the current flows from the output stage into output 埠D, 206 at which the voltage is reduced. Similarly, the current flows from the output stage into the output 埠C, and the voltage of 204 decreases.

When Δ v is negative, the voltage of the node 172 decreases, the voltage at node 156 rises, current and 184,172, so that a larger via the resistor 182 from node 156 to node 160 provides the current transistors. This current is mirrored by the upper current mirror consisting of transistors 160 and 162. Therefore, the current supplied by transistor 162 is also greater, current flows from output 埠C to the output stage, and the voltage at 204 rises. Similarly, current flows from output 埠D to the output stage, and the voltage at 206 rises.

To ensure proper operation of the op amp, for example, to make the performance of the op amp essentially independent of process variations, the common-mode voltage between nodes 148 and 150 cannot swing much, for a constant common-mode output current I , node 148 and The common mode voltage of 150 should be kept substantially constant. The bases of transistors 138 and 140 are biased to maintain the common mode voltage at nodes 148 and 150 within an effective range to ensure that equation (1) is fundamental to the rail-to-rail mode of operation of the operational amplifier. Established. This performance can be achieved through a negative feedback loop.

Next, a negative feedback loop for setting the common mode voltage between nodes 148 and 150 will be described. Current sources 174 and 176 are matched to each other to provide a bias current for Schottky diode 178. Since the current fed to node 180 by current source 174 is equal to the amount of current flowing from node 180 into current source 176, the amount of current flowing through resistors 182 and 184 is also equal, depending on the voltage difference between nodes 156 and 172. Thus, the voltage at node 180 is the arithmetic mean of the voltages at nodes 156 and 172, that is, the common mode voltages of nodes 150 and 148, denoted by V. The potential at the ground terminal 137 is set to zero, and the voltage drop across the resistor 141, the base emitter voltage of the transistor 140, and the voltage drop when the Schottky diode 178 is positively biased are added to obtain the following relationship:

Where R is the resistor value of resistor 141, V _BE is the base emitter voltage of transistor 140 and V _SC is the forward voltage drop across Schottky diode 178.

It can be seen from the relation (5) that the common mode voltage V between the nodes 148 and 150 is a constant value for the constant common mode current I supplied from the input stage circuit shown in Fig. 1 to the intermediate stage circuit shown in Fig. 2. The feedback loop described above can be thought of as a path from node 180 to nodes 148 and 150 that pass through Schottky diode 178 to the bases of transistors 138 and 140. It should be noted that transistors 186 and 188 and current source 190 together form a buffer such that the voltage at node 156 follows the voltage at node 150. Similarly, transistors 192 and 194 and current source 196 together form a buffer such that the voltage at node 172 follows the voltage at node 148. These buffers are also part of the feedback loop.

To determine that the feedback loop is a negative feedback loop, a positive perturbation is applied to the voltages at nodes 148 and 150, respectively, to add a positive perturbation to the common mode voltage V. This will cause the voltage at nodes 156 and 172 to increase, thus causing the voltage at node 180 to also increase. Thus, the base voltages of transistors 138 and 140 will increase, causing the voltages on nodes 148 and 150 to decrease, thereby attenuating the aforementioned positive perturbations. The above analysis shows that the feedback loop is a negative feedback loop. It can be seen from the above analysis that the intermediate stage circuit shown in FIG. 2 improves the circuit gain of the operational amplifier and, at the same time, increases the conversion rate.

In some embodiments, the current mirror formed by transistors 160 and 162 and the current mirror formed by transistors 200 and 202 are matched. Similarly, current sources 158, 170, 190, and 196 are also matched in pairs.

3 is an output driver stage in accordance with one embodiment of the present invention. To facilitate the description of the output driver stage circuit shown in Figure 3, the operational amplifier is considered to be operating in a static mode. In this mode, the voltage at input 埠 102 is equal to the voltage at input 埠 104, and thus the intermediate stage circuit shown in Figure 2 neither supplies current to the driver stage circuit shown in Figure 3 nor sinks current from the driver stage circuit.

Referring to FIG. 3, current source 302 biases transistor 304, the bases of transistors 304 and 306 are interconnected to form a current mirror, and the base currents of transistors 304 and 306 flow through transistor 308. The transistor 310 and current source 312 form a voltage follower such that the voltage at node 314 follows the voltage at node 316. To simplify the description of the output driver stage circuit shown in Figure 3, assume that all of the transistors in Figure 3 have the same forward voltage drop V _F , ie the base emitter voltage V _{BE of} all NPN transistors is equal to V _F , all The base emitter voltage V _{BE of the} PNP transistor is equal to - V _F . It should be noted that the voltage at node 314 is equal to the voltage at node 316 minus V _F , and likewise, since the base of transistor 308 is connected to node 314, the voltage at node 318 is equal to the voltage at node 314 plus V _F . Thus, the voltage at node 318 is equal to the voltage at node 316. The voltage at node 314 biases the base of transistor 320 such that the voltage at node 322 is equal to the voltage at nodes 316 and 318.

The voltage at power terminal 324 is represented by V _CC . In the static mode of operation, the voltages at nodes 316, 318, and 322 are all equal to V _CC - V _F , and the base voltage of transistor 320 is equal to V _CC -2 V _F .

The lower part of the circuit in Fig. 3 is the dual circuit of the upper part of the circuit, that is, the two parts of the circuit are similar in structure, and the type of the transistor included is opposite. Current source 326 biases transistor 328, and the bases of transistors 328 and 330 are interconnected to form a current mirror. Current source 331 and transistor 332 form a voltage follower. Transistor 334 provides bias current to transistors 328 and 330. The voltage at node 336 biases the base of transistor 338. Let the voltage at the ground terminal 340 be 0; still, for the sake of simplicity, the forward voltage drop of all the transistors in the lower part of the circuit shown in FIG. 3 is considered to be V _F , so that the voltages at the nodes 342, 344 and 346 Also for V _F , the base voltage of transistor 338 is equal to 2 V _F .

The circuit in Fig. 3 has symmetry, and the upper part of the circuit and the lower part of the circuit have the same specification parameters. In practice, the size parameter of transistor 306 may be larger than the size parameter of transistor 304 to provide greater current to transistor 304. Likewise, in practical applications, the size parameter of transistor 330 may be larger than the size parameter of transistor 328 to provide greater current to transistor 328.

Current supplied by transistor 306 flows into transistors 320, 334, and 338. Similarly, the current provided by transistor 330 flows into transistors 338, 308, and 320. The transistors 308 and 334 provide only the base current, the value of which is small relative to the current provided by the transistors 320 and 338, so the current provided by the transistors 308 and 334 is negligible in the discussion that follows. . In some embodiments, due to the symmetry of the circuit, half of the current provided by transistor 306 flows into transistor 338 and the other half flows into transistor 320. Similarly, half of the current provided by transistor 330 flows into transistor 338 and the other half flows into transistor 320. Thus, the currents flowing through transistors 320 and 306 are equal to the magnitudes of the currents flowing through transistors 338 and 330, respectively. The voltages at nodes 322 and 346 bias transistors 348 and 350, and thus, transistors 348 and 350 are both conducting.

The above description is based on the static mode of operation of the driver stage shown in FIG. Now, consider the case where the voltage at input 埠 102 is greater than the voltage at input 埠 104. At this point, the voltage at node 148 is greater than the voltage at node 150 such that the intermediate stage circuit shown in FIG. 2 will sink current Δi ' from node "C" of the circuit shown in FIG. Thus, the voltage at node 322 will decrease. Since the voltage at node 322 is equal to the emitter voltage of transistor 320, the voltage reduction at node 322 will cause transistor 320 to turn off, thereby no longer providing current to node 346. However, transistor 330 will continue to supply current. As a result, transistor 330 will continue to sink current from the base of transistor 350 and transistor 338, while transistor 338 draws current from the base of transistor 348. Similarly, the intermediate stage circuit shown in Figure 2 will also sink current Δi ' from node "D" to the node 206. Thus, the voltage at node 206 will decrease. Thus, the base voltage drop of transistors 348 and 350 is rapidly reduced, which will cause transistor 350 to be turned off and transistor 348 to be forced to conduct. As a result, the driver stage circuit will output the appropriate current to the output port 106. As can be seen from the above analysis, the circuit shown in Figure 3 provides a rail-to-rail output for the operational amplifier, effectively controlling the quiescent current while also increasing the slew rate of the operational amplifier. In some applications, the output 埠 106 is connected to a capacitive load, and since the driver stage circuit drives the bypass transistor to regulate the load, the capacitive load at the output 埠 106 will be quickly charged.

For the case where the voltage at the input port 102 is less than the voltage at the input port 104, the discussion of the driver stage circuit shown in FIG. 3 is similar to the above discussion, but at this time, the intermediate stage circuit shown in FIG. 2 provides the current Δi ' , Crystal 350 is forcibly turned on and transistor 348 is turned off quickly. Thus, the driver stage circuit sinks the appropriate current from the output port 106 to ground. Therefore, the capacitive load at the output 埠 106 will be quickly discharged.

With regard to the above, it will be apparent that many other modifications and variations of the invention are possible. It is to be understood that the invention may be practiced with a technique not specifically described herein within the scope of the protection covered by the appended claims. Of course, it is to be understood that the invention is intended to be limited by the scope of the invention and the scope of the invention. As the disclosure is only a preferred embodiment, those skilled in the art can devise different modifications without departing from the spirit and scope of the invention as defined by the appended claims. For example, the input stage, intermediate stage, and output stage shown in Figures 1, 2, and 3 can operate independently of each other.

It should be understood that the term "A to B" as used herein means that A and B are interconnected to each other to have their potentials equal, wherein A and B may be node or device terminals and the like. For example, A and B can be connected by interconnect lines, such as transmission lines. In integrated circuit technology, the interconnects can be so short that they can be compared to the size parameters of the device itself. For example, the bases of the two transistors can be connected by polysilicon or copper interconnects, wherein the length of the polysilicon or copper interconnect can be compared to the spatial dimension of the base. For another example, A and B may be connected by a switch such as a transmission gate such that when the switch is turned on, the potentials of A and B are equal. It should also be understood that A and B herein and in the following description are different from 埠 "A" and "B" or nodes "A" and "B" in the specific embodiment of the present invention.

It should be understood that the term "A coupled to B" as used in the present invention may mean that A and B are interconnected with each other to make their potentials equal, and it may also mean that A and B are not interconnected to each other to make their potentials equal, but A and B is connected by a device or a circuit. The apparatus or circuit herein may comprise an active circuit element or a passive circuit element, wherein the passive circuit element may be a distributed parameter element or a lumped parameter element. For example, A can be connected to a circuit component that is also connected to B.

It should be understood that the term "current source" as used herein may mean a current source or a current sink. Similarly, the term "providing current" as used in the present invention may mean current flow or current flow.

It should also be understood that various circuit devices or modules, such as current mirrors, amplifiers, etc., in the present invention may be part of a larger circuit, and that each circuit device or module may include a switch such that the circuit device or mode Groups are enabled or disabled in larger circuits. At this point, the circuit device or module is still considered to be connected to the larger circuit.

102. . . Input 埠

104. . . Input 埠

108. . . NPN transistor

110. . . NPN transistor

112. . . PNP transistor

114. . . PNP transistor

116. . . Power terminal

118. . . PNP transistor

120. . . PNP transistor

122. . . node

124. . . node

126. . . PNP transistor

128. . . PNP transistor

130. . . Battery

132. . . Battery

134. . . Battery

106. . . Output埠

137. . . Ground terminal

138. . . Transistor

139. . . Resistor

140. . . Transistor

141. . . Resistor

142. . . Battery

144. . . Load resistor

146. . . Load resistor

148. . . node

150. . . node

152. . . Transistor

154. . . Transistor

156. . . node

158. . . Battery

160. . . Transistor

162. . . Transistor

164. . . Transistor

168. . . Transistor

170. . . Battery

172. . . node

174. . . Battery

176. . . Battery

178. . . Schottky diode

180. . . node

182. . . resistance

184. . . resistance

186. . . Transistor

188. . . Transistor

190. . . Battery

192. . . Transistor

194. . . Transistor

196. . . Battery

200. . . Transistor

202. . . Transistor

204. . . node

206. . . node

302. . . Battery

304. . . Transistor

306. . . Transistor

308. . . Transistor

310. . . Transistor

312. . . Battery

314. . . node

316. . . node

318. . . node

320. . . Transistor

322. . . node

324. . . Power terminal

326. . . Battery

328. . . Transistor

330. . . Transistor

332. . . Transistor

334. . . Transistor

336. . . node

338. . . Transistor

340. . . Ground terminal

342. . . node

344. . . node

346. . . node

348. . . Transistor

350. . . Transistor

331. . . Battery

1 is a schematic diagram of an error amplifier input stage or a partial input stage, in accordance with one embodiment of the present invention.

2 is a schematic diagram of an intermediate stage of an error amplifier in accordance with one embodiment of the present invention.

3 is a schematic diagram of an error amplifier drive stage in accordance with one embodiment of the present invention.

102. . . Input 埠

104. . . Input 埠

108. . . NPN transistor

110. . . NPN transistor

112. . . PNP transistor

114. . . PNP transistor

116. . . Power terminal

118. . . PNP transistor

120. . . PNP transistor

122. . . node

124. . . node

126. . . PNP transistor

128. . . PNP transistor

130. . . Battery

132. . . Battery

134. . . Battery

137. . . Ground terminal

Claims (19)

An operational amplifier comprising: a power supply terminal; a ground terminal; an input stage that causes the operational amplifier to perform rail-to-rail operation; an intermediate stage, the intermediate stage is connected to the input stage; and an output stage connected to the output stage An intermediate stage; wherein the input stage comprises: a first input 埠 and a second input 埠; a first output 埠 and a second output 埠; a first input NPN transistor, the first input NPN transistor comprising a base, a collector And an emitter connected to the first input port, the collector being connected to the power terminal; a first input PNP transistor, the first input PNP transistor comprising a base, a collector and an emitter and the base a pole connected to the first input port, the collector being connected to the second output port; a second input NPN transistor, the second input NPN transistor comprising a base, a collector and an emitter and the base is connected to the a second input port, the collector is connected to the power terminal; a second input PNP transistor, the second input PNP transistor includes a base, a collector and an emitter, and the base is connected to the second input port, The collector is connected to the first output port; PNP transistor, the PNP transistor includes a first base, collector and emitter and the emitter is connected to the exit of the NPN transistor of a first input electrode, The collector is coupled to the first output port; the second PNP transistor, the second PNP transistor includes a base, a collector, and an emitter, and the emitter is coupled to an emitter of the second input NPN transistor, a collector connected to the second output port, the base being coupled to a base of the first PNP transistor; a third PNP transistor including a base, a collector, and an emitter and the emitter Connected to an emitter of the first input NPN transistor, the collector is coupled to a base of the third PNP transistor, the base is coupled to a base of the first PNP transistor; a fourth PNP transistor, the The fourth PNP transistor includes a base, a collector and an emitter connected to an emitter of the second input NPN transistor, the collector being coupled to a collector of the third PNP transistor, the base connected a base of the first PNP transistor; and a first current source coupled to the collectors of the third PNP transistor and the fourth PNP transistor. The operational amplifier of claim 1, wherein the input stage further comprises: a second current source connected to an emitter of the second input PNP transistor; and a third current source, The third current source is coupled to the emitter of the first input PNP transistor. The operational amplifier according to any one of claims 1 to 2, wherein the intermediate stage comprises: a first intermediate stage input NPN transistor, the first intermediate stage input The NPN transistor includes a base, a collector, and an emitter connected to the first output port; a second intermediate stage inputting an NPN transistor, the second intermediate input NPN transistor including a base, a collector, and a shot a pole connected to a base of the first intermediate stage input NPN transistor, the emitter being coupled to the second output port; a first node, a second node, and a third node; a first class AB buffer, The first class AB buffer connects the collector of the first intermediate stage input NPN transistor to the first node; the second class AB buffer, the second class AB buffer inputs the second intermediate stage to the NPN a collector of the crystal is coupled to the second node; a first resistor having a first turn and a second turn and the first turn connected to the first node, the second turn connected to the third a node; and a second resistor having a first turn and a second turn and the first turn connected to the second node, the second turn connected to the third node. The operational amplifier of claim 3, wherein the intermediate stage further comprises: a first intermediate stage current source connected to the third node; a diode, the diode An anode and a cathode connected to the third node, the cathode being coupled to a base of the first intermediate stage input NPN transistor; and a second intermediate stage current source coupled to the second The cathode of the polar body. The operational amplifier of claim 4, wherein the first class AB buffer comprises: a first PNP transistor, the first PNP transistor comprising a base, a collector and an emitter and the base is connected a collector of the first intermediate stage input NPN transistor; a first NPN transistor, the first NPN transistor including a base, a collector and an emitter and the base is connected to the first class AB buffer a PNP transistor, the emitter is connected to the first node; a second NPN transistor, the second NPN transistor includes a base, a collector and an emitter and the base is connected to the first intermediate stage input NPN a collector of the crystal; and a second PNP transistor including a base, a collector, and an emitter, the base being coupled to an emitter of the second NPN transistor of the first class AB buffer, The emitter is coupled to the first node; and the second class AB buffer includes: a first PNP transistor, the first PNP transistor including a base, a collector, and an emitter, and the base is coupled to the second The intermediate stage inputs the collector of the NPN transistor; the first NPN transistor, the first NPN transistor includes a base, a set And a first PNP transistor having an emitter connected to the second class AB buffer, the emitter being coupled to the second node; a second NPN transistor, the second NPN transistor including a base, a set a pole and an emitter connected to the second intermediate stage input NPN transistor a collector of the body; and a second PNP transistor comprising a base, a collector and an emitter and the base is coupled to an emitter of the second NPN transistor of the second class AB buffer, The emitter is coupled to the second node. The operational amplifier of claim 3, wherein the output stage comprises: an output 埠; an output stage PNP driving a transistor, the output stage PNP driving transistor comprising a base, a collector and an emitter and the emitter Connected to the power supply terminal, the base is connected to the collector of the first NPN transistor of the first class AB buffer, the collector is connected to the output port; the output stage NPN drives the transistor, and the output stage NPN drives the battery The crystal includes a base, a collector and an emitter connected to the ground, the base being coupled to a collector of a second PNP transistor of the first class AB buffer, the collector being coupled to the output a first output stage PNP transistor, the first output stage PNP transistor comprising a base, a collector and an emitter, the emitter being connected to the power terminal, the collector being connected to the first class AB buffer a collector of an NPN transistor; a second output stage PNP transistor, the second output stage PNP transistor comprising a base, a collector and an emitter and the emitter is coupled to the first NPN of the first class AB buffer a collector of the transistor, the collector being coupled to the second PNP of the first class AB buffer Collector electrode body; a first output stage NPN transistors, the first output stage comprises a NPN transistor base, emitter and collector and the emitter connected to the ground terminal, the set a collector connected to the second PNP transistor of the first class AB buffer; and a second output stage NPN transistor, the second output stage NPN transistor including a base, a collector and an emitter and the emitter A collector connected to the second PNP transistor of the first class AB buffer, the collector being coupled to the collector of the first NPN transistor of the first class AB buffer. The operational amplifier of claim 6, wherein the output stage comprises: a third output stage PNP transistor, the third output stage PNP transistor comprising a base, a collector and an emitter and the emitter is connected To the power supply end, the base is connected to the base of the first output stage PNP transistor; the fourth output stage PNP transistor, the fourth output stage PNP transistor includes a base, a collector and an emitter and the shot a pole connected to a base of the first output stage PNP transistor, the base being coupled to a base of the second output stage PNP transistor, the collector being coupled to the second PNP transistor of the first class AB buffer a first voltage follower connected to the third output stage PNP transistor and the fourth output stage PNP transistor, the collector of the third output stage PNP transistor having a collector voltage, The base of the fourth output stage PNP transistor has a base voltage, the base voltage of the fourth output stage PNP transistor follows the collector voltage of the third output stage PNP transistor; the third output stage NPN transistor, The third output stage NPN transistor includes a base, a collector, and an emitter and the Is connected to the ground terminal, the base connected to the first output stage NPN transistor base; a fourth output stage NPN transistor, the fourth output stage NPN transistor includes a base, a collector and an emitter, and the emitter is connected to a base of the first output stage NPN transistor, the base is connected to the first a base of a two output stage NPN transistor, the collector being coupled to a collector of a first NPN transistor of the first class AB buffer; and a second voltage follower coupled to the third output a stage NPN transistor and a fourth output stage NPN transistor, the collector of the third output stage NPN transistor has a collector voltage, and the base of the fourth output stage NPN transistor has a base voltage, the fourth output stage The base voltage of the NPN transistor follows the collector voltage of the third output stage NPN transistor. An operational amplifier input stage circuit comprising: a power supply terminal; a first input port and a second input port; a first output port and a second output port; a first input NPN transistor, the first input NPN transistor including a base, a collector and an emitter connected to the first input port, the collector being coupled to the power terminal; a first input PNP transistor, the first input PNP transistor comprising a base, a collector, and an emitter The base is connected to the first input port, the collector is connected to the second output port; the second input NPN transistor, the second input NPN transistor comprises a base, a collector and an emitter and the base is connected To the second input port, the collector is connected to the power terminal; the second input PNP transistor, the second input PNP transistor includes a base, a collector, and an emitter connected to the second input port, the collector being coupled to the first output port; a first PNP transistor, the first PNP transistor including a base, a collector, and An emitter and an emitter connected to an emitter of the first input NPN transistor, the collector being coupled to the first output port; a second PNP transistor including a base, a collector, and a shot a pole connected to an emitter of the second input NPN transistor, the collector being coupled to the second output port, the base being coupled to a base of the first PNP transistor; a third PNP transistor, The third PNP transistor includes a base, a collector and an emitter connected to an emitter of the first input NPN transistor, the collector being coupled to a base of the third PNP transistor, the base Connected to a base of the first PNP transistor; a fourth PNP transistor, the fourth PNP transistor including a base, a collector, and an emitter connected to an emitter of the second input NPN transistor, The collector is coupled to a collector of the third PNP transistor, the base being coupled to a base of the first PNP transistor; and a first current The first current source is connected to the collector of the third PNP transistor and the PNP transistor of the fourth electrode. The operational amplifier input stage circuit of claim 8, wherein the operational amplifier input stage circuit further comprises: a second current source connected to the emitter of the second input PNP transistor; And a third current source connected to the first input PNP The emitter of the crystal. An operational amplifier intermediate stage circuit comprising: a first input 埠 and a second input 埠; a first input NPN transistor, the first input NPN transistor comprising a base, a collector and an emitter, and the emitter is connected to the first An input NMOS; a second input NPN transistor, the second input NPN transistor comprising a base, a collector and an emitter connected to the base of the first input NPN transistor, the emitter being coupled to the a second input port; a first node, a second node, and a third node; a first class AB buffer, the first class AB buffer connecting the collector of the first input NPN transistor to the first node; a second class AB buffer, the second class AB buffer connecting the collector of the second input NPN transistor to the second node; a first resistor, the first resistor comprising a first 埠 and a second 埠The first turn is connected to the first node, the second turn is connected to the third node; and a second resistor, the second resistor includes a first turn and a second turn and the first turn is connected to the first A second node, the second node connected to the third node. The operational amplifier intermediate stage circuit of claim 10, wherein the operational amplifier intermediate stage circuit further comprises: a first current source connected to the third node; a diode, the second The pole body has an anode and a cathode and the anode is connected to the third node, the cathode being connected to a base of the first input NPN transistor; A second current source coupled to the cathode of the diode. The operational amplifier intermediate stage circuit of claim 10, wherein the first class AB buffer comprises: a first PNP transistor, the first PNP transistor comprising a base, a collector and an emitter and the a base connected to the collector of the first input NPN transistor; a first NPN transistor, the first NPN transistor comprising a base, a collector and an emitter and the base is coupled to the first class AB buffer a first PNP transistor, the emitter is coupled to the first node; a second NPN transistor, the second NPN transistor includes a base, a collector, and an emitter connected to the first input NPN transistor And a second PNP transistor comprising a base, a collector and an emitter and the base is coupled to an emitter of the second NPN transistor of the first class AB buffer, An emitter is coupled to the first node; and the second class AB buffer includes: a first PNP transistor, the first PNP transistor including a base, a collector, and an emitter, and the base is coupled to the second input a collector of a NPN transistor; a first NPN transistor, the first NPN transistor including a base, a collector, and a shot And the base is connected to the first PNP transistor of the second class AB buffer, the emitter is connected to the second node; the second NPN transistor, the second NPN transistor comprises a base, a set a pole and an emitter connected to the collector of the second input NPN transistor; and a second PNP transistor including a base, a collector and an emitter and the base connected to the An emitter of a second NPN transistor of the second class AB buffer, the emitter being coupled to the second node. The operational amplifier intermediate stage circuit of claim 12, wherein the operational amplifier intermediate stage circuit further comprises: a first current source connected to the third node; a diode, the second The pole body has an anode and a cathode and the anode is connected to the third node, the cathode is connected to a base of the first input NPN transistor; and a second current source is connected to the cathode of the diode . The operational amplifier intermediate stage circuit of claim 13, wherein the operational amplifier intermediate stage circuit further comprises: a third current source; and a third resistor connecting the third current source to the first a collector of the input NPN transistor; and a fourth resistor connecting the third current source to the collector of the second input NPN transistor. The operational amplifier intermediate stage circuit of claim 14, wherein the operational amplifier intermediate stage circuit further comprises: a first current mirror, the first current mirror comprising a first PNP transistor and a second PNP transistor, Wherein the first PNP transistor comprises a base, a collector and an emitter and the collector is connected to the first of the first class AB buffer a collector of the NPN transistor; the second PNP transistor includes a base, a collector, and an emitter, and the collector is coupled to a collector of the first NPN transistor of the second class AB buffer, the base being coupled to a base of a first PNP transistor of the first current mirror and a collector of a second PNP transistor of the first current mirror; and a second current mirror comprising a first NPN transistor and a second An NPN transistor, wherein the first NPN transistor includes a base, a collector, and an emitter, and the collector is connected to a collector of the second PNP transistor of the first class AB buffer; the second NPN transistor a collector comprising a base, a collector and an emitter connected to the second PNP transistor of the second class AB buffer, the base being coupled to a base of the first NPN transistor of the second current mirror And a collector of the second NPN transistor of the second current mirror. The operational amplifier intermediate stage circuit of claim 12, wherein the operational amplifier intermediate stage circuit further comprises: a first current mirror, the first current mirror comprising a first PNP transistor and a second PNP transistor, Wherein the first PNP transistor comprises a base, a collector and an emitter and the collector is connected to a collector of the first NPN transistor of the first class AB buffer; the second PNP transistor comprises a base, a collector and an emitter connected to the collector of the first NPN transistor of the second class AB buffer, the base being coupled to a base of the first PNP transistor of the first current mirror and the first a collector of a second PNP transistor of a current mirror; and a second current mirror comprising a first NPN transistor and a second NPN transistor, wherein the first NPN transistor includes a base, a collector, and an emitter, and the collector is coupled to a collector of the second PNP transistor of the first class AB buffer; the second NPN The transistor includes a base, a collector, and an emitter, and the collector is coupled to a collector of the second PNP transistor of the second class AB buffer, the base being coupled to the first NPN transistor of the second current mirror a base and a collector of the second NPN transistor of the second current mirror. An operational amplifier output stage circuit comprising: a first input 埠 and a second input 埠; an output 埠; a power supply terminal and a ground terminal; and a PNP driving transistor, the PNP driving transistor including a base, a collector, and an emitter, and the emitter a pole connected to the power terminal, the base is connected to the first input port, the collector is connected to the output port; the NPN driving the transistor, the NPN driving transistor comprises a base, a collector and an emitter, and the emitter Connected to the ground terminal, the base is connected to the second input port, the collector is connected to the output port; the first PNP transistor, the first PNP transistor comprises a base, a collector and an emitter and the shot The pole is connected to the power terminal, the collector is connected to the first input port; the second PNP transistor, the second PNP transistor comprises a base, a collector and an emitter, and the emitter is connected to the first input port The collector is coupled to the second input port; a first NPN transistor, the first NPN transistor including a base, a set a pole and an emitter connected to the ground, the collector being coupled to the second input port; a second NPN transistor, the second NPN transistor including a base, a collector, and an emitter and the emitter Connected to the second input port, the collector is connected to the first input port; a third PNP transistor, the third PNP transistor includes a base, a collector and an emitter, and the emitter is connected to the power terminal, The base is connected to a base of the first PNP transistor; a fourth PNP transistor, the fourth PNP transistor includes a base, a collector and an emitter, and the emitter is connected to a base of the first PNP transistor The base is coupled to a base of the second PNP transistor, the collector being coupled to the second input port; a first voltage follower coupled to the third PNP transistor and the fourth PNP a crystal, a collector of the third PNP transistor has a collector voltage, a base of the fourth PNP transistor has a base voltage, and a base voltage of the fourth PNP transistor follows a collector of the third PNP transistor a third NPN transistor, the third NPN transistor including a base, a collector, and an emitter, and the emitter is coupled to a ground terminal, the base is connected to a base of the first NPN transistor; a fourth NPN transistor, the fourth NPN transistor includes a base, a collector and an emitter, and the emitter is connected to the first NPN a base of the crystal, the base being coupled to a base of the second NPN transistor, the collector being coupled to the first input port; a second voltage follower connected to the third NPN transistor and the fourth NPN transistor, the collector of the third NPN transistor having a collector voltage, the base of the fourth NPN transistor having The base voltage, the base voltage of the fourth NPN transistor follows the collector voltage of the third NPN transistor. The operational amplifier output stage circuit of claim 17, wherein the first voltage follower comprises an NPN transistor, wherein the NPN transistor comprises a base, a collector and an emitter, and the emitter is connected To a base of the fourth PNP transistor, the base is coupled to a collector of the third PNP transistor, the collector is coupled to the power supply terminal; and the second voltage follower includes a PNP transistor, wherein The PNP transistor includes a base, a collector and an emitter connected to a base of the fourth NPN transistor, the base being coupled to a collector of the third NPN transistor, the collector being coupled to the Ground terminal. The operational amplifier output stage circuit of claim 18, wherein the first voltage follower comprises a first current source and a second current source, wherein the first current source is coupled to the third PNP transistor a collector, the second current source is coupled to a base of the fourth PNP transistor; and the second voltage follower includes a first current source and a second current source, wherein the first current source is coupled to the first A collector of a three NPN transistor, the second current source being coupled to a base of the fourth NPN transistor.