TWI415315B - Racetrack nonvolatile memory manufacturing method and structure thereof - Google Patents

Abstract

A racetrack nonvolatile memory manufacturing method is disclosed. The method includes the following steps: Using a photo resist and the related lithography technology to define a racetrack memory on spin valve. Using the lift-off technology to make a reading terminal at the middle section of the racetrack memory. Using the lift-off technology to make a magnetic domain-wall driving terminal at one end of the racetrack memory. Electrically connecting a first nanosecond current pulse source to the magnetic domain-wall driving terminal. Electrically connecting a first matching impedance to the other end of the racetrack memory. Producing an isolation layer between the reading terminal and the magnetic domain-wall driving terminal. Using the lift-off technology to make a writing electrode above the isolation layer. Electrically connecting a second nanosecond current pulse source to one end of the writing electrode. Electrically connecting a second matching impedance to the other end of the writing electrode.

Description

Orbital competition type non-volatile memory manufacturing method and structure thereof

The present invention relates to an orbital competitive non-volatile memory, and more particularly to a method of manufacturing an orbital non-volatile memory.

[Prior Art] Mr. Stuart Parkin of IBM Labs in the United States proposed an orbital non-volatile memory theory based on spintronics technology, which enables non-volatile memory to simultaneously have semiconductor memory. The advantages of high access performance and robustness, as well as the low cost and large capacity of the general hard disk.

However, Mr. Parkin's orbital non-volatile memory is a long strip of magnetic recording elements; moreover, this orbital non-volatile memory requires an additional tunneling magnetoresistive sensor (Tunnel magnetoresistance). Sensor, TMR sensor) to read the signal smoothly.

One aspect of the present invention provides a method for manufacturing a track-competitive non-volatile memory to manufacture a track-competitive non-volatile memory.

According to one aspect of the present invention, a method for manufacturing a track-competitive non-volatile memory is provided, which includes the steps of: defining a track-competitive recording element on a spin valve by a lithography technique using a resist . A signal reading end is produced in the center of the track-competitive recording element by using one technique. A magnetic wall push end is fabricated on one end of the orbital competition recording element by using the lifting technique. Electrically connected to a first nanosecond short pulse current source from the magnetic wall push end. A first matching resistor is electrically connected to the other end of the track-competitive recording element. An insulating layer is formed between the signal reading end and the magnetic wall pushing end. A write electrode is fabricated on the insulating layer using lift-off techniques. Electrically connecting a second nanosecond short pulse current source from one end of the write electrode. And electrically connecting a second matching resistor to the other end of the write electrode. Thereby, the method can manufacture a track-competitive non-volatile memory.

Another technical aspect of the present invention is to provide a track-competitive non-volatile memory structure, and the signal reading end of the structure can be realized only by using an external electrode.

According to another aspect of the present invention, a track-competitive non-volatile memory structure includes a base, a spin valve, a track-competitive recording element, a signal reading end, and a magnetic wall pushing end. a first nanosecond short pulse current source, a first matching resistor, an insulating layer, a write electrode, a second nanosecond short pulse current source, and a second matching resistor. The spin valve is located on the substrate, the spin valve includes a pinned sublayer and a free sublayer, the free sublayer is on the pinning sublayer, and the pinned sublayer contacts the substrate. The orbital competition recording element is generated by using a lithography technique to define a spin valve. The signal reading end is located in the center of the orbital competition recording element, and the magnetic wall pushing end is located at one end of the orbital competition recording element, and the first nanosecond short pulse current source is electrically connected to the magnetic wall pushing end, and the first matching resistance is electrically connected. The sex is connected to the other end of the orbital competition record element. The insulating layer is located on the spin valve and is located between the signal reading end and the magnetic wall pushing end; the writing electrode is formed on the insulating layer. The second nanosecond short pulse current source is electrically connected to one end of the write electrode, and the second matching resistor is electrically connected to the other end of the write electrode.

Therefore, the track-competitive non-volatile memory structure of the present invention can read the signal smoothly only by applying an electrode to the signal reading end. In other words, the spin valve can be a multi-layer spin valve or a multi-layer magnetic tunnel junction (MTJ) to generate a large magnetoresistance. If the spin valve adopts a multi-layer structure spin valve, the external electrode of the signal reading end can directly apply two electrodes on the surface of the spin valve and the left and right sides of the signal reading end. If the spin valve uses a multilayer structure magnetic tunneling junction, the applied electrode must be attached to the surface of the multilayer structure magnetic tunneling junction and its bottom layer.

Please refer to FIG. 1 , which is a method for manufacturing a track-competitive non-volatile memory according to an embodiment of the present invention. This embodiment includes the following steps: First, as shown in step 110, a track-type recording element is defined on a spin valve by a lithography technique using a resist. The resist is generally a negative photoresist, and the corresponding lithography technology is a photolithography technique. However, in order to pursue lightness and shortness, the resist may also be a negative electron resistive, and the corresponding lithography technique is an electron beam lithography technique. Next, as shown in step 120, a signal reading end is created in the center of the track-competitive recording element using a lift-off technique. It is worth noting that the negative electron resist and the corresponding lift technology are used here to realize the signal reading end of the track-competition recording element. In other words, if optical lithography is used, the signal reading end is likely to be too large to work properly.

Next, as shown in step 130, a magnetic wall push end is fabricated on one end of the track-competitive recording element using the lift-off technique. Then, as shown in step 140, a first nanosecond short pulse current is electrically connected to the magnetic wall push end. Next, as shown in step 150, a first matching resistor is electrically connected to the other end of the track-competitive recording element. This first matching resistor is typically 50 ohms. Then, as shown in step 160, an insulating layer is formed between the signal reading end and the magnetic wall pushing end; and, as shown in step 170, a writing electrode is formed on the insulating layer by lift-off technique.

Finally, as shown in step 180, a second nanosecond short pulse current is electrically connected to one end of the write electrode; and, as shown in step 190, a second matching resistor is electrically connected to the write electrode. One end. Among them, the second matching resistor is generally also 50 ohms.

It should be noted that the orbital recording element of this embodiment is built on a spin valve, and the spin valve can be a multi-layer spin valve or a multi-layer magnetic tunneling junction (Magnetic). Tunnel Junction, MTJ), to generate a large magnetic reluctance.

In another embodiment of the present invention, an orbital non-volatile memory structure is proposed. This is achieved by the above-described orbital non-volatile memory manufacturing method. The steps and their corresponding orbital non-volatile memory processing semi-finished structures are detailed as follows: Please refer to Figures 2A and 2B. In this embodiment, a substrate 100 is first selected, and a spin valve 200 is laid on the substrate. As is clear from the cross-sectional view shown in FIG. 2B, the spin valve 200 includes a pinned sub-layer 210 and a free sub-layer. 220.

Please refer to Figures 3A and 3B. In this embodiment, a negative resist layer 300 is laid on the spin valve 200. Of course, this embodiment can also use a positive resist, and only need to change the corresponding mask.

Please refer to Figures 4A and 4B. In this embodiment, a desired pattern, that is, an etched pattern 310, is defined on the negative resist layer 300 by lithography.

Please refer to Figures 5A and 5B. In this embodiment, the region that is not protected by the photoresist of the etched pattern 310 is etched to define the track-competitive recording element 400.

Please refer to Figures 6A and 6B. In this embodiment, an electronic resist 500 is laid on the above semi-finished product. The electronic resist 500 is selected here to cooperate with the electron beam lithography technology to process an appropriately sized signal reading end.

Please refer to Figures 7A and 7B. In the embodiment, the signal reading area 600, the first lifting area 610 and the second lifting area 620 are generated on the electronic resist 500 by electron beam lithography and lifting technology.

Please refer to Figures 8A and 8B. In this embodiment, the conductive material is filled in the signal reading area 600, the first lifting area 610, and the second lifting area 620, and then the electronic resist 500 is removed. In this way, the signal reading end 601, the magnetic wall pushing end 611 and the resistance matching end 621 can be formed.

Please refer to Figures 9A and 9B. In this embodiment, an insulating layer 700 is disposed between the signal reading end 601 and the magnetic wall pushing end 611. The insulating layer 700 may be made of a cerium oxide (SiO ₂ ) insulating layer or other high dielectric material.

Please refer to Figures 10A and 10B. In this embodiment, an electrode is laid on the insulating layer 700, which can be used as the write electrode 710.

Please refer to Figures 11A and 11B. In this embodiment, a first nanosecond short pulse current source 810 is connected to the magnetic wall pushing end 611, a first matching resistor 820 is connected to the resistance matching end 621, and a second nanosecond level is respectively connected to the two ends of the writing electrode 710. A short pulse current source 830 and a second matching resistor 840. The first matching resistor 820 and the second matching resistor 840 are generally 50 ohms.

Therefore, the track-competitive non-volatile memory structure of the embodiment includes a substrate 100, a spin valve 200, a track-competitive recording element 400, a signal reading end 601, a magnetic wall pushing end 611, and a first The nanosecond short pulse current source 810, a first matching resistor 820, an insulating layer 700, a write electrode 710, a second nanosecond short pulse current source 830, and a second matching resistor 840. The spin valve 200 is located on the substrate 100. The spin valve 200 includes a pinning sub-layer 210 and a free sub-layer 220. The free sub-layer 220 is located on the pinning sub-layer 210, and the pinning sub-layer 210 contacts the substrate 100. The track-racing recording element 400 is produced by defining a spin valve 200 using a lithography technique. The signal reading end 601 is located at the center of the track-competitive recording element 400, and the magnetic wall pushing end 611 is located at one end of the orbital competition recording element 400. The first nanosecond short pulse current source 810 is electrically connected to the magnetic wall pushing end 611. The first matching resistor 820 is electrically connected to the other end of the track-competitive recording element 400. The insulating layer 700 is located on the spin valve 200 and is located between the signal reading end 601 and the magnetic wall pushing end 611; the writing electrode 710 is formed on the insulating layer 700. The second nanosecond short pulse current source 830 is electrically connected to one end of the write electrode 710, and the second matching resistor 840 is electrically connected to the other end of the write electrode 710. Therefore, the track-competitive non-volatile memory structure of the present invention only needs to add the electrode 900 to the signal reading end 601, so that the signal can be read smoothly.

It should be noted that the spin valve 200 can be a multi-layer spin valve or a multi-layer magnetic tunnel junction (MTJ) to generate a large magnetoresistance. If the spin valve 200 is a multi-layer structure spin valve, the external electrode 900 of the signal reading end 601 can directly apply two electrodes to the surface of the spin valve, and the left and right sides of the signal reading end 601. If the spin valve 200 selects a multilayer structure magnetic tunneling junction, the additional electrode 900 must be attached to the surface of the multilayer structure magnetic tunneling junction and its bottom layer.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100. . . Base

110~190. . . step

200. . . Spin valve

210. . . Pinning sublayer

220. . . Free sublayer

300. . . Negative resist layer

310. . . Etched graphics

400. . . Orbital competition record element

500. . . Electronic resist

600. . . Signal reading area

601. . . Signal reader

610. . . First lift

611. . . Magnetic wall push end

620. . . Second lift

621. . . Resistance matching end

700. . . Insulation

710. . . Write electrode

810. . . First nanosecond short pulse current source

820. . . First matching resistor

840. . . Second matching resistor

830. . . Second nanosecond short pulse current source

900. . . Read electrode

1 is a flow chart showing the steps of a method for manufacturing a track-competitive non-volatile memory according to an embodiment of the present invention.

2A to 11B are schematic views showing the structure of a track-competitive non-volatile memory structure according to an embodiment of the present invention.

110~190. . . step

Claims (12)

A method for manufacturing a non-volatile memory of orbital competition, comprising the steps of: defining a track-competition recording element on a spin valve by using a lithography technique by using a resisting agent; using the one-off technique to record the orbital competition a signal reading end is produced by the central unit; a magnetic wall pushing end is formed on one end of the orbiting competition recording element by using the lifting technique; and a first nanosecond short pulse current is electrically connected to the magnetic wall pushing end; Connecting a first matching resistor to the other end of the track-competitive recording element; forming an insulating layer between the signal reading end and the magnetic wall pushing end; using the lifting technique to form a writing electrode on the insulating layer Electrically connecting a second nanosecond short pulse current from one end of the write electrode; and electrically connecting a second matching resistor to the other end of the write electrode. The orbital non-volatile memory manufacturing method according to claim 1, wherein the resist is a negative electron resist, and the lithography is an electron beam lithography. The orbital non-volatile memory manufacturing method according to claim 1, wherein the resist is a negative photoresist, and the lithography technology is a photolithography technique. The orbital non-volatile memory manufacturing method according to claim 1, wherein the spin valve is a multi-layer structure spin valve. The orbital non-volatile memory manufacturing method according to claim 1, wherein the spin valve is a multilayer structure magnetic tunneling junction. The method of manufacturing a track-competitive non-volatile memory according to claim 1, wherein the first matching resistance is 50 ohms. The method of manufacturing a track-competitive non-volatile memory according to claim 1, wherein the second matching resistor is 50 ohms. An orbital non-volatile memory structure comprising: a substrate; a spin valve on the substrate, the spin valve comprising a pinning sublayer and a free sublayer, the free sublayer being located in the pinning a sub-layer, and the pinning sub-layer contacts the substrate; a track-competitive recording element is generated by using a lithography technique to define the spin valve; a signal reading end is located in the orbital competition recording element a magnetic wall pushing end is located at one end of the orbiting competition recording element; a first nanosecond short pulse current source is electrically connected to the magnetic wall pushing end; a first matching resistor is electrically The other end of the track-competitive recording element; an insulating layer is located on the spin valve and located between the signal reading end and the magnetic wall pushing end; a writing electrode is formed on the insulating layer; The second nanosecond short pulse current source is electrically connected to one end of the write electrode; and a second matching resistor is electrically connected to the other end of the write electrode. The orbital non-volatile memory structure of claim 8, wherein the spin valve is a multi-layer structure spin valve. The orbital non-volatile memory structure of claim 8, wherein the spin valve is a multilayer structure magnetic tunneling junction. The track-competitive non-volatile memory structure of claim 8, wherein the first matching resistance is 50 ohms. The orbital non-volatile memory structure of claim 8, wherein the second matching resistance is 50 ohms.