TWI414791B - Test arrangement, pogo-pin and method for testing a device under test - Google Patents

Abstract

A test arrangement (400) comprises an interface (401) for a device under test (404), the interface (401) comprising an impedance matching circuit (402) comprising a resistance (R) and an inductance (L) connected in parallel.

Description

Test configuration device, spring pin and method for testing the device under test

Embodiments of the invention relate to a configuration device, a spring pin, and a method for testing a component under test.

In the set state of the wafer testing technique, an input/pin of a device under test (DUT) is connected to the test circuit through a pin of a test head of the tester. Sometimes, the device under test is used to route signals from the device under test to the pins of the test head or to the pins of the test head to the device under test. Further, corresponding inputs of a plurality of DUTs can be connected to a common pin of the test head. All of these configuration devices introduce problems in the test design because reflections from one impedance domain to another are reflected, a problem that becomes more severe at higher test signal rates. These reflections then hinder the performance of reliable testing.

According to an embodiment of the present invention, a test configuration apparatus is specifically provided, comprising: an interface for a device under test, the interface comprising an impedance matching circuit, the impedance matching circuit comprising a resistor (R) connected in parallel An inductance (L).

Simple illustration

The invention may be described with reference to the accompanying drawings: Figure 1 shows a beam diagram in which light is reflected by an optical material or through an optical material, depending on an optical anti-reflective coating of the optical material, to illustrate One of the main ideas underlying the embodiments of the present invention; Figure 2a shows a schematic diagram of the scenario of Figure 1, in which light is transmitted through an optical medium having a different index of reflection than the ambient air. 2b is a schematic diagram showing an electrical transmission line connected to a device under test according to the optical arrangement device shown in FIG. 2a, the device under test having an impedance different from the impedance of the transmission line; FIG. 3a shows An equivalent circuit diagram of the input impedance of a device under test, including a resistive "terminal built into the chip" and a capacitive input capacitor; and Figure 3b shows a representation of the input impedance in Figure 3a.奎斯特图; Figure 4a shows an equivalent circuit diagram of an input impedance of a device under test, the input impedance comprising a resistive specific resistance and inductance value built into the wafer Terminal and one pole and one ESD (electrostatic discharge) capacitor; Figure 4b shows a Nyquist diagram illustrating the input impedance in Figure 4a; Figure 5 illustratively shows the input of a GDDR5 memory a TDR (Time Domain Reflected) map of impedance; Figure 6 shows a cross-sectional view of a circuit spring pin according to a comparative embodiment; Figure 7a shows the internal components of a spring pin of another comparative embodiment and for internal use A top view of the spring in which the member and the outer sleeve are separated from each other; FIG. 7b is a plan view showing a device in a compressed state in FIG. 7a; and FIG. 8 is a view showing a spring pin shown in FIGS. 7a and 7b. a top view of one of the outer sleeves; and Fig. 9 shows a time domain reflection measured by an input pin of a shorted test element (DUT) through the spring pins of Figs. 7a to 8 (TDR) map; Figure 10 shows a histogram illustrating the repeatability of a spring pin measurement using the spring pin shown in Figures 7a through 8; Figure 11 shows a TDR map, the TDR map is a comparative test configuration device for measuring a device under test (DUT) Measured; Figure 12 shows an eye diagram of a signal received at a TDR receiver in a test configuration device for measuring an impedance mismatched test component; Figure 13a shows an SMA (super A small sub-miniature-A adapter cable is schematically illustrated as an end view of an ODT load simulation; and Figure 13b shows a terminal built into the wafer as shown in Figure 13a ( The ODT) load terminal is an equivalent circuit diagram of the SMA adapter cable of the terminal; FIG. 14 shows one of the SMA adapter cables with the ODT load terminal as the terminal as shown in FIG. 13a A pole map of the input impedance; Figure 15 shows a TDR diagram measured by a component-free daisy chain test configuration device; Figure 16 shows a daisy chain test configuration device that has loaded DDR2 components at all locations. a TDR diagram; Figure 17 shows a circuit diagram for connecting a test pin to a branch on two elements under test, the branch comprising a common line and two lines connected by a branch node; The figure shows a circuit diagram of the branch as shown in Fig. 17, wherein the branch lines The impedance and the input impedance of the DUTs are specific values; Figure 19 shows a conventional branch circuit diagram as shown in Figure 17, which indicates the reflections that occur; Figure 20a shows the results for a common test. A circuit diagram of the daisy chain test configuration device for measuring the DUT in the channel; a 20D diagram showing a TDR map measured using the test configuration device shown in FIG. 20a; and a 21a diagram showing the application to a daisy chain configuration device One of the test signals is a step response timing diagram; Figure 21b shows an eye diagram of the test signal as shown in Figure 21a; and Figure 22a shows a transmission through the optical medium as shown in Figure 2a when the optical The medium comprises a wave pattern of an optical film made of an anti-reflective coating material; and Figure 22b shows a signal diagram similar to that of Figure 22a. According to an embodiment of the invention, the signal pattern is Figure 2b. The electric transmission line has an anti-reflection circuit (impedance matching circuit) connected between the transmission line and the impedance of the terminal; FIG. 23a shows a schematic diagram of a test configuration device according to an embodiment of the present invention; this invention Another embodiment shows a schematic diagram of a test configuration apparatus; FIG. 23c shows an equivalent circuit diagram of a test configuration apparatus according to an embodiment of the present invention; and FIG. 23d shows an implementation according to one embodiment of the present invention. A schematic diagram of a test configuration device including a device tester, a test interface, and a plurality of interfaces for a plurality of devices under test; and FIG. 23e shows a test configuration as illustrated in FIG. 23a Theoretically a Nyquist plot of the input impedance of the device; Figure 24a shows an equivalent circuit diagram of the test configuration device corresponding to one of the illustrative examples of the GDDR5 memory component shown in Figure 4a, with a basis An embodiment of the present invention, an impedance matching circuit connected between the transmission line and the device under test; Figure 24b shows a theoretical Nyquist diagram of the test configuration device as shown in Fig. 24a; Figure 25 shows a theoretical TDR diagram measured using the test configuration device as shown in Figure 24a; Figure 26 shows the voltage at the device under test as shown in Figure 24a. A step response timing diagram comparing the voltages at the input impedance of the device under test generated in the case of FIG. 4a; FIG. 27 shows an exemplary schematic of a spring pin in accordance with an embodiment of the present invention. FIG. 28 is a schematic cross-sectional view showing a spring pin according to another embodiment of the present invention; and FIG. 29a is a perspective view showing a spring pin according to an embodiment of the present invention; Figure 29b shows a space view of a spring pin in accordance with another embodiment of the present invention; Figure 29c shows a top view of a test configuration device in accordance with an embodiment of the present invention; An embodiment of the invention shows an equivalent circuit diagram of a test configuration device comprising an impedance matching circuit, a TDR transmitter and a TDR receiver; and FIG. 31 shows the use as shown in FIG. The test configuration device measures a TDR map; FIG. 32 shows an equivalent circuit diagram of a test configuration device including an impedance matching circuit and a TDR transmitter according to an embodiment of the present invention. a microstrip line and a measuring probe; Fig. 33 shows an eye diagram of a signal received by the TDR receiver of the test configuration device as shown in Fig. 32; Fig. 34a is an embodiment of the present invention, A schematic cross-sectional view of a test configuration apparatus is shown, the test configuration apparatus including an SMA adapter cable that is terminated by an ODT load simulation and a series of impedance matching circuits; Figure 34b shows a 34a Figure 1 is an equivalent circuit diagram of the test configuration device; Figure 35 shows a Smith chart of a reflection coefficient measurement of the test configuration device as shown in Figure 34a; Figure 36 is implemented in accordance with one of the present invention For example, an equivalent circuit diagram of a test configuration device is shown. The test configuration device includes two impedance matching circuits, each impedance matching circuit and a device under test, a length mismatched Y-branch cable, and a TDR transmission. The device is associated with a measurement probe; Figure 37 shows a signal diagram measured using the test configuration device as shown in Figure 36; and Figure 38 shows a test configuration in accordance with an embodiment of the present invention. One of the devices is equivalent The test configuration device includes two impedance matching circuits, each impedance matching circuit being associated with a device under test, a length mismatched Y-branch cable, a test signal transmitter, and a test signal receiver; Figure 39 shows an eye diagram measured using the test configuration device as shown in Figure 38; Figure 40 shows a circuit diagram of a test configuration device according to an embodiment of the present invention, the test configuration device comprising 17 the branch shown, and an impedance matching circuit connected between respective output lines and respective impedances of the device under test; FIG. 41 shows a test configuration device, etc. according to an embodiment of the present invention The circuit diagram, the test configuration device includes two components to be tested; and FIG. 42 shows a simulated eye diagram of a first input signal of the simulation of the test configuration device as shown in FIG. 41; An embodiment of the invention shows an equivalent circuit diagram of a test configuration device comprising four components under test; and FIG. 44 shows a model of a test configuration device as shown in FIG. a signal diagram of the four input signals; FIG. 45 shows an eye diagram of the simulated first input signal of the test configuration device as shown in FIG. 44; and FIG. 46 shows a schematic diagram of a test configuration device, The test configuration device includes an impedance matching circuit coupled to a first device under test through a first transmission line and coupled to a second device under test via a second transmission line, the first transmission line having a ratio a length of a quarter wavelength of a carrier of the test signal and the second transmission line having a length greater than a quarter wavelength of the carrier of the test signal; and FIG. 47 is shown in FIG. A timing diagram of the signal measured by the first device under test and measured by the second device under test.

In the following, a main idea existing in the present invention is explained. Through the reflection problem in the reference optics, the occurrence of a problem caused by a similar problem is shown. In the electrical measurement test configuration device, the pair reflection in the optical is introduced. The countermeasures of the problem and then, these countermeasures are converted into the electrical measurement test configuration device in the form of a majority of embodiments of the present invention.

Figure 1 shows a beam diagram in which light is reflected by an optical material or passed through an optical material. As shown in Figure 1, the ratio between reflection and transmission depends on the presence or absence of a conventional anti-reflective coating of the optical material. The upper portion 10 of the optical material is not coated with an anti-reflective coating, while the lower portion 12 of the optical material is coated with an anti-reflective coating. The optical material can be a lens 14 and an anti-reflective coating can be applied to the outer surface of the lens 14 remote from the viewer (not shown) to reduce reflection of incoming light. This reflected light may interfere with the observer. For example, this reflection reduces the amount of transmission. Further, the reflected light may reach an area where light is not desired to be sensitive to light. In complex systems such as a telescope, for example, the drop in reflection can increase the contrast of the image by eliminating stray light. In other applications, such as, for example, applying an anti-reflective coating to an eyeglass lens, the primary benefit is to eliminate its own reflections, thus resulting in a better vision and a brighter view.

In Fig. 1, for example, the optical material 14 does not include an upper portion of the anti-reflective coating, a beam of light 16 is mostly reflected back by the lens 14, and only a portion of the upper portion 16 that has been strongly attenuated passes through the lens 14. In the lower portion of the optical material 14 coated with an anti-reflective coating, a beam of light 18 passes mostly through the lens 14. When the optical material 14 comprises an appropriately sized anti-reflective coating, up to 99% of the beam 18 in Figure 1 passes through the optical material 14.

Figure 2a shows a conventional optical medium in which light is transmitted through a reflection index having a different index of reflection than ambient air. The beam 20 is moved by an optical medium such as air into another optical medium glass 22, such as glass, wherein the glass 22 has a reflection index n ₁ greater than the reflection index n _{0 of} air, where n ₀ =1, i.e., n ₁ > n ₀ . A portion r of the beam 20 is reflected by the surface of the glass 22, and another portion b of the beam 20 passes through the glass 22. The intensity of this reflection depends on the reflection indices n ₀ and n _{1 of the} two media and the angle of the surface with the beam 20 . The exact value can be calculated using Fresnel equations.

The simplest form of anti-reflective coating was discovered by Lord Rayleigh in 1886. A thin film anti-reflective coating (ARC) on the surface of the glass 22 reduces reflection. A film having a material having a refractive index n _ARC between the air having a refractive index n ₀ and the glass having a refractive index n ₁ may cause the beam to be reflected twice, that is, from the interface of air and the thin ARC layer, And reflecting from the interface of the thin ARC layer and the glass.

Figure 2b shows a signal diagram of a conventional electrical transmission line terminated by a terminal impedance formed by a device under test that is different in impedance from the transmission line. An electrical signal 24 passes through the transmission line labeled "trace" in Figure 2b. The transmission line has an impedance Z ₀ . The transmission line under test DUT terminal element, having a sensing element DUT then impedance Z _in the subject. If the impedance Z _{in of the} DUT under test does not match the impedance Z _{0 of} the transmission line, then a portion r of the electrical wave 24 is reflected by the DDU under test and another portion b of the electrical wave 24 is transmitted to the DDU under test. "Match" in the case if the device under test DUT impedance Z _in of the transmission line equal to the impedance i.e. Z _in = Z ₀ Z ₀ can occur, for example 50 ohms. In this matched state, the radio wave 24 is all transmitted to the device under test DUT. The reflected portion r of the electric wave 24 will reach 0%, and the transmitting portion b of the electric wave 24 will reach 100%.

2a and 2b, therefore, the similarity of the electric wave and the optical wave is explained, wherein the impedance of the electric wire or the element corresponds to the refractive index of the optical material.

Figure 3a shows an equivalent circuit diagram of a conventional input impedance of a DUT under test, which includes a resistive "on-die termination" R _ODT and a capacitive input. Capacitor C _{IN is} connected in parallel. In the case of Fig. 3a, the parallel connection of the R _ODT and C _IN is between the terminal for connecting the transmission line and the potential Vddq applied to the DUT from the outside. The device under test DUT may correspond to the device under test DUT as described in Figure 2b. Sensing element receiving an input impedance of the DUT under test element of Figure 3a corresponds to the Z of FIG 2b in the input impedance Z _in. The input impedance Z is formed by a parallel connection of a capacitor C _IN and a resistor R _ODT . When the device under test DUT includes a wafer, the resistor R _ODT can be formed by a termination resistor built into the wafer implemented on the wafer of the DUT. The capacitor C _IN may be formed by a gate capacitor or an ESD protection circuit of the DUT, such as an integrated circuit ESD pin circuit, if the device under test DUT includes an integrated circuit.

Figure 3b shows a Nyquist diagram illustrating the input impedance Z in Figure 3a. The Nyquist plot shows the impedance Z of the device under test DUT for different frequencies. The impedance Z(f) for different frequencies is plotted in a coordinate system having a horizontal axis of Re(Z) and a vertical axis of Im(Z) along which the real part of the input impedance Z is plotted along the The imaginary part of the input impedance Z is plotted on the vertical axis. For zero frequency or DC conditions, the input impedance Z is equal to R _ODT , which can be 120 Ohm. For the case where the frequency is close to infinity, the input impedance Z is close to 0 Ohm due to the capacitance Cin. For the case where the frequency is between zero frequency and infinity, Z(f) describes a curve passing, for a frequency f1, the imaginary part of the impedance Z is equal to the real part.

Figure 4a shows an equivalent circuit diagram of an input impedance of a device under test DUT comprising a resistive terminal ODT built into the chip and a gate and ESD circuit forming capacitor C. The device under test DUT is formed by a parallel connection of the gate resistor and the ESD circuit forming a capacitor C of 1.5 p, which is represented by a resistor R of 60 Ohm. The device under test DUT is connected to a transmission line which illustratively has an impedance Z _{0 of} 60 Ohm. Therefore, the input impedance Z _in corresponds to the impedance Z as described in FIG. 3a, wherein the terminal resistor R built into the wafer and the gate and ESD capacitor have discrete values in FIG. 4a.

Figure 4b shows a Nyquist plot illustrating the input impedance as shown in Figure 4a. r represents the reflection coefficient and b represents the refractive index. At the DC frequency, the impedances Z ₀ and Z _in match, i.e., r = 0% and b = 100%. In other words, at the DC frequency, the input impedance Z _{in the} DUT of the device under test is equal to 60 Ohm, matching the impedance of the transmission line to 60 Ohm. For higher frequencies, the input impedance Z _in is increased the magnitude of the imaginary part. For example, for a frequency between 1 GHz and 2 GHz, the input impedance corresponds to Z _in = (30-30j) Ohm. For frequencies close to infinity, a wave is completely reflected by the DUT under test, ie r = 100% and b = 0%. For frequencies close to infinity, the capacitor C acts as the same masking circuit to completely reflect the energy of the waves flowing through the transmission line.

Similar to the case of optics described above, such electrical reflections can cause problems. This will be outlined below.

For example, Figure 5 illustrates that an impedance mismatch interface between a transmission line and a DUT causes the power in the transmitted signal to reach the transmission source (like an echo) again. In particular, Figure 5 shows a time domain reflectance (TDR) plot of the input impedance measured using a GDDR5 memory component. GDDR5 (Graphic Double Data Rate, Version 5) is a high speed dynamic random access memory designed for applications requiring high bandwidth. Time Domain Reflectometry (TDR) is a program used to determine and analyze the duration and reflection characteristics of electromagnetic and electromagnetic signals. In the TDR test, a pulse generator produces a series of very short signal transitions (steps) with a rise time of, for example, 20 nanoseconds, which follow such a time interval to make the next transition. At the beginning, the echoes of the previous transitions were completely settled. An oscilloscope can be used to measure these step responses. The transitions are applied to the device under test, and the device under test reflects the pulses in accordance with its input impedance. If the input impedance of the device under test matches the impedance of the transmission line, then no pulses are reflected and no echo can be observed by the oscilloscope.

Figure 5 illustrates a mismatch. The TDR map includes an amplitude axis A and a time axis t. The figure shows an amplitude A of a reflected signal transition (step) plotted at time t. t=0s represents the time at which a transition state begins. Between t = 0 s and 100 ps (picoseconds), a transient occurs in relation to the rise time of the square wave signal pulses. Between 100 ps and 400 ps, the TDR map represents a constant amplitude of one of the received signals, indicating that a portion of the signal pulse directly reaches the TDR receiver/oscilloscope connected to the same end of the transmission line as the pulse generator. After 400 ps, the reflection of the signal pulse reaches the receiver, whereby the energy of the received signal is initially reduced. In Figure 5, the reduction is illustratively from 500 millivolts to 345 millivolts. Thereafter, the received voltage rises again between 500 ps and 750 ps, rising from 345 millivolts to a full amplitude of 550 millivolts. The negative effect of the reflection terminates after 750 ps, which is a time indicating the transit time of the device under test connected to the impedance line and is a characteristic value of the DUT. Figure 5 shows that a test measurement using the GDDR5 memory component for Figure 5 should wait at least 750 ps before deciding a test signal result to ensure that there are no unwanted distortions that have a negative impact on the quality of the measurement.

Until now, the above discussion has focused only on the input impedance of the DUT, adapting the impedance to the line impedance of the transmission. However, in the case of a test head, the pins used to electrically contact the pins of the DUT also pose a problem of impedance matching in the design of the test configuration device.

Figure 6 shows a cross-sectional view of a possible spring pin that can be used as one of a BGA (ball grid array) pad 34 and a DUT (device under test) 38 on a socket board. The interface between a ball 36 in a grid array. A spring pin is used in a device in an electronic circuit for establishing a relationship between two electronic devices, such as between printed circuit boards (PCBs) or between a PCB and an IC or the like Temporary connection.

Spring pins can be used in test systems. A test system includes a test head, a pin-electronic module and a corresponding driver located in the test head. The pin-electronic module is connected to a spring-connector via a cable, and the spring-connector is arranged on the upper side of the test head. An interface is mated to the test head whereby the spring pin contacts the interface through the low side. The interface includes a contact pad adapted to contact the spring pins, wherein the contact pads are connected to the interface through an interface cable. These interface cables end on the upper side of the interface to connect the socket boards. The socket boards can be (small) PCBs (printed circuit boards) and also contain contact areas for connecting the DUT sockets 32. The DUT sockets 32 can be screwed to (or connected to) the contact areas of the socket boards. The DUT sockets 32 contain (small) spring pins 30 as shown in FIG. They have a length of approximately 2-3 mm. The DUTs 38 are pressed into the DUT sockets 32 whereby the balls 36 of the ball grid array package 38 are contacted by the spring pins 30. Such a contact provides a complete signal path connection between the DUT and the test driver or DUT and test receiver, respectively. The spring pin 30 shown in Fig. 6 can have a relatively short length of about 2-3 mm, and the cable disposed on the interface has a length of about 40 cm.

The spring pin shown in Fig. 6 comprises two tubes or casings 40 and 42 of electrically conductive material, one of which is inserted in the other 42 so that they are slidably opposed along their common axis For mobile. Some interlocking devices (not shown in the sixth figure) may be provided to prevent the outer casing 40 from falling out of the outer casing 42. A spring 44 is placed in the inner region enclosed by the outer casings 40 and 42 to carry the outer casings 40 and 42 from the inner spring to separate the outer casings 40 and 42. Compressing the spring pin along a longitudinal axis of the spring pin, such as between two electrical circuits, causes the spring 44 to push the housings 40 and 42 relative to the electrical circuit by a force that depends on the degree of compression. Thereby a safe electrical contact is established between the two circuits. The spring pin of Figure 6 can be placed on a dense array with other spring pins to connect the individual pins of the electrical circuits. In Fig. 6, one electrical circuit is a DUT 38 and the other is, for example, a circuit board for interconnecting the DUT with a test head. In the latter case, the spring pin of Figure 6 can electrically interconnect one of the pin arrays or balls 36 of one of the arrays of DUTs 38 with the respective pads of the circuit board or socket board. The electrical contact between the pins 36 and 34 is not solely due to a resistive electrical path formed by the two outer casings 40 and 42. Furthermore, the spring can be made of a conductive material such as metal. In this case, the spring produces an inductive element that is electrically connected between pins 34 and 36, which is not required in the first example. However, the following description of some embodiments of the invention will show that this inductance has a positive effect in forming a portion of the impedance matching or anti-reflection circuit.

For the sake of completeness, Figure 6 is further described below. In particular, Figure 6 shows the spring pin 30 contained by a DUT socket 32. That is, the spring pin is supported by the socket 32 such that the outer casing 40 projects from one side of the socket 32 and the other outer casing 42 projects from the other side of the socket 32. Although not shown in Figure 6, more than one spring pin can be combined in this manner to obtain a lateral array of spring pins. The spring pin 30 is used to electrically connect a pad 34 on a circuit board to a ball 36 of a ball grid array (BGA) of a device under test package 38. As described above, the spring pin 30 includes the inner tube 40, the outer tube 42 and the spring 44.

Figure 7a shows an inner tube of a spring pin and a spring in contact with the inner tube in a released state. The spring 50 can be mechanically attached to the inner tube 52. Alternatively, the spring 50 only abuts against the inner surface of the barrel 52. The inner tube 52 includes a contact portion 56 for abutting a spacer of a device under test. The spring pin further includes a piston portion 54 for inserting an outer tube not shown in this figure. In the released state as shown in Fig. 7a, the piston portion protrudes out of the outer tube. In the compressed state as shown in Figure 7b, portion 54 is inside the outer tube. At an opposite end of the piston portion opposite the contact portion, the spring pin includes a spring retaining portion 58 that projects radially outwardly relative to the piston portion to disengage the spring tube from the outer tube The portions interfere with each other to define a hole through which the piston portion extends to prevent the inner tube 52 from disengaging from the outer tube. The spring retaining portion 58 is also used to form a fixed surface against which the spring 50 compresses. The spring 50 is stabilized within the inner tube 52 in its radial position by an inner portion 60 of the inner tube 52, the inner portion 60 extending inwardly from the spring retaining portion 58 and having a portion 58 Small radial extension. In other words, the spring 50 is fitted over the inner portion 60. At the end of the spring 50 opposite the fixed end of the spring fixing portion, the spring may have a reduced diameter to be inserted into the outer tube and serve as a contact for the inner portion in the compressed state Point as described later.

The spring fixing portion 58 of the spring pin corresponds to the fixing point as shown in Fig. 6, wherein the spring 44 contacts the inner tube 40.

The outer tube sleeved over the inner tube 52 is not shown in Figure 7a but an example is shown in Figure 8, which shows an outer tube and the inner tube.

The inner portion extends longitudinally in such a manner that, in the compressed state shown in Fig. 7b, an end portion 64 facing away from the spring fixing portion 58 contacts the small diameter portion of the spring 50, and by the small diameter portion Electrically contacting the outer tube. As shown in Fig. 7a, when the spring 50 is in the released state shown in Fig. 7a, the inner tube 52 can have a length of 3.7 mm.

It is to be noted that the spring 50 can be biased even in the state where the separation of the tubes shown in Figure 7a is maximized. To this extent, the term "released" is to be interpreted broadly to mean that the spring is compressed/biased in a compressed state that minimizes the distance between the tubes shown in Figure 7b. The pressure is small.

Fig. 7b shows the inner tube 52 of the spring pin in Fig. 7a and the spring 50 of the spring pin in the compressed state. In this state, the inner tube 52 is maximally received into the outer tube and the spring 50 is under maximum compression. The length of the spring 50 is reduced, for example, from 3.7 mm to 3.4 mm, in which case the spring pin has a variable length with a variable amount of 0.3 mm. This length is referred to as the contact stroke 62. The end 64 of the inner portion 60 is in mechanical contact with the small diameter portion of the spring 50 when the spring 50 is maximally compressed thereby forming an electrical contact between the inner barrel 52, the spring 50 and the outer barrel. Thus, the inner portion 60 also acts as an interlocking mechanism to prevent the portion of the inner tube 52 from entering the outer tube beyond the contact stroke 62.

Figure 8 shows a possible outer sleeve 66 of the spring pin of Figures 7a and 7b and the inner tube. The outer tube 66 can have dimensions as indicated in the figures. The outer sleeve or tube 66 includes a small diameter hollow portion 74 adapted to one of the small diameter portions of the spring 50 and the hollow portion 74 serves as an external contact portion for mechanically and electrically contacting a gasket, the gasket being The gasket contacting the contact portion 56 of the inner tube 52 contacts. Further, the sleeve 66 includes a large diameter portion 72 to accommodate the large diameter portion of the spring 50, not shown in Fig. 8. At the end of the large diameter portion 72 opposite the small diameter portion 74, the sleeve 66 includes a bore through which the piston portion of the inner tube extends. At the aperture, the large diameter portion 72 includes a ring (not shown) projecting inwardly in the radial direction to engage the spring retaining portion of the inner barrel 52 to prevent the inner tube from exiting the outer tube.

It can be clearly seen from the discussion of the above-mentioned 7a, 7b and 8 that there are three possible electrical paths through which the ends of the spring pin are electrically connected through the spring pin: a path through the spring 50, a path through the inner portion of the inner sleeve, and a path through the mechanical contact between the piston and the cylindrical portion via the sleeve itself. In accordance with some of the following embodiments, a spring pin having a similar configuration is designed to form at least a portion of a matching circuit whereby the number of electrical paths can be varied as described below. In any case, the spring-passed path results in a high impedance that must be considered in the test. Further, the point of contact between the spring and the end 64 of the inner portion 60 is determined to be rather inaccurate, resulting in a continuous test using the spring pins shown in Figures 7a, 7b, and 8. The resulting impedance will vary, or at least, a change in impedance between a set of identically configured spring pins.

Figure 9 shows a time domain reflectance (TDR) pattern measured using a spring pin of a device under test that is in contact with a short circuit, as shown in Figures 7a, 7b, and 8. The unwanted inductance of the spring pin mentioned above produces a delay due to the measurement performed by the spring pin. Figure 9 illustrates this delay. A TDR pulse is transmitted by a signal generator to the shorted device via the spring pin. The pulse is then reflected by the shorted device and received by a signal receiver such as, for example, an oscilloscope. The signal received by the oscilloscope is depicted in Figure 9. In the event of a short circuit, the signal transmitted to the device should be received in reverse polarity after being reflected. The pulses sent to the device have an amplitude of approximately 70 millivolts, which can be observed between 0 and 100 ps of the time axis. The pulse is reflected by the shorted test element after about 1.4 ns +/- 400 ps and is received in reverse polarity. Depending on the details of the short circuit, such as the resistance of the inductive nature portion of the path, a different delay can be observed.

To calibrate the test fixture, an appliance delay calibration (FXDL cal) is performed prior to testing the DUT to account for the signal propagation process between the test head and the DUT balls. For this purpose, a shorting device (such as a gold plated metal sheet) is inserted instead of a real DUT. When the shorting device is inserted, it creates a shorting to the ground pin. If a step signal is sent by the tester (like using a TDR), the propagation delay of the echo (in the reverse step) reveals the length of the electrical path. However, if the path is not an ideal transmission line having a real impedance of, for example, 50 ohms but an inductor such as the "harmful" socket spring pin, the impedance becomes complex and a parasitic delay is added. This feature is shown in Figure 9.

A first curve 81 illustrates the measurement using a first shorting device and a second curve 82 illustrates the measurement using a second shorting device. A delay between the first curve 81 and the second curve 82 reaches approximately 100 ps, which can be observed by the first curve 81 and two points at which the two curve 82 intersects the time axis t. The delay is approximately 650 ps for the first curve 81 and approximately 750 ps for the second curve 82.

Figure 10 shows a histogram illustrating the repeatability of one of the testers using spring pins as shown in Figures 7a, 7b and 8. The figure illustrates the result of the difference between two consecutive FXDL measurements performed on a DDR2 memory component. The time difference between the two consecutive FXDL measurements is plotted on a time axis t and a sampling axis. The sampling axis represents the pin number of the pin of the DDR2 device measured by the FXDL measurement. The difference measurement shows the difference time of 0, 80, -40 or -80 ps. This measurement shows a very good repeatability, which is 0 seconds for most times, but sometimes a 40 or 80 ps error occurs. This measurement can be used for the purpose of calibrating the test device.

The problem shown in Figure 10 above shows that there may be an unwanted portion of the inductor in the pin and can be used for purposes such as an anti-reflection circuit.

The problem of the impedance mismatch between the DUT and the transmission line is further illustrated by the short display of the spring pin for providing the connection interface between the DUT and the test head, which increases the complexity of the matching problem. Will be explained.

Figure 11 shows a time domain reflectometry (TDR) map measured at one of the components under test for a planar ODT (terminal built into the wafer). A pulse is transmitted through the transmission line to the device under test and is then reflected by the ODT load of the device under test. The TDR map illustrates that the reflection starts at 2 ns and lasts until approximately 3.5 ns.

Figure 12 shows an eye diagram of a signal received by a test configuration device measuring one of the components under test at 500 Mbps. The digital signal from the TDR receiver corresponds to the signal measured using the test configuration device as shown in FIG. However, the digital signal is oversampled and applied to the vertical axis input of an oscilloscope such that the signal represents amplitude and the one-bit clock signal is used to trigger horizontal scanning of the oscilloscope. The resulting oscilloscope output is referred to as an eye diagram as shown in FIG. It can be seen that the reflection as shown in Fig. 11 observed by the TDR measurement causes the closure or contraction of the eye pattern. During time interval 90, the reflection corresponds to the distortion of the eye pattern, wherein the duration of a data bit is represented by time interval 91. The duration of the reflection 90 corresponds to the duration of the reflection shown in Figure 11 and ranges from about 1.7 ns to about 2.3 ns. This is long enough for the eye diagram to be severely disturbed for a duration of approximately 2 ns. In order to perform an accurate measurement using the test configuration device, a shorter sampling time is required, for example 250 Mbps may be required, and is no longer relevant to the application.

Figure 13a shows a schematic cross-sectional view of a conventional SMA adapter 100 with a terminal built into the wafer (ODT) load simulation 101 as a terminal. The terminal load emulation 101 built into the chip includes a capacitor 102 connected in parallel with a resistor 103. The value of the capacitor 102 in this example is 11 pF and is achieved by a 10 pF first capacitor 104 and a 1 pF second capacitor 105 in parallel. The resistor 103 is implemented by connecting two 100 Ω resistors 106 in parallel. The resistors 106 and the capacitors 104, 105 are discrete devices such as, for example, SMD components. The terminal 101 built into the wafer is attached to the SMA adapter 100 by, for example, soldering.

Figure 13b shows an equivalent circuit diagram of the SMA adapter cable 100 terminated with the end-of-wafer terminal (ODT) load terminal 101 as shown in Figure 13a. The equivalent circuit diagram includes an 11pF capacitor 102 in parallel with a 50Ω resistor 103. The SMA adapter cable 100 with ODT load emulation can be used for illustrative purposes to illustrate the result of a resistive built-in termination of the wafer in parallel with a parasitic capacitance as a result of termination of the device under test. The terminal load emulation 101 built into the wafer is used to display the same electrical characteristics as, for example, a memory element terminated by an integrated terminal built into the wafer.

Figure 14 shows a pole diagram of a reflection factor of the SMA adapter cable 100 with the ODT load terminal as the terminal as shown in Figure 13a. The pole map illustrates the reflection factor r with the absolute value of the S parameter S11. The S parameter is a characteristic that describes the electrical behavior of a linear electrical network as it undergoes various small signal steady state excitations. Many of the electrical characteristics of the network or component can be represented by S-parameters, such as the reflection coefficient r corresponding to the S-parameter S11. S-parameters are mostly used in networks operating at RF and microwave frequencies, where the power and energy of the signal are easier to quantify than current and voltage. Since the S-parameter varies with the measurement frequency, for any of the S-parameter measurements, in addition to the characteristic impedance or system impedance, the measurement frequency must also be included. The four S parameters can be measured using a network analyzer. S11 is the voltage reflection coefficient of the input ,, S12 is the reverse voltage gain, S21 is the forward voltage gain, and S22 is the voltage reflection coefficient of the output 埠. In the pole diagram according to Fig. 14, the S parameter S11 is displayed in accordance with the measurement frequency. Starting with a direct current (DC) frequency, the S11 parameter corresponds to a reflection parameter of zero, which indicates that the SMA adapter cable 100 as shown in Fig. 13a matches the ODT load as shown in Fig. 13b. For DC frequencies, the impedance of the SMA adapter cable 100 is 50 ohms, corresponding to a DC impedance of 50 ohms for the ODT load. For higher frequencies up to 1 GHz, the reflection parameter increases, corresponding to the effect of capacitor 102 in the ODT load as shown in Figure 13b. For non-zero frequency cases, such reflections from the ODT load may not be ignored. Multiple joint points are connected to the common line, and the joint points

The following example illustrates when more than one DUT is connected to a test head channel or a test head pin competes for one or more joints, such as a DUT connected to the shared transmission line along a joint point distributed along a common transmission line as a terminal. The measurement problem caused by an increase in impedance mismatch when a daisy chain is obtained

Figure 15 shows a TDR diagram measured by a daisy chain test configuration device for memory components without component loading. The TDR map is measured on an address line shared by four DUTs. A number of echoes between 1 ns and 3 ns are seen which are generated by the received reflections from the unloaded ends of the branches connected to the address lines of the individual memory element interfaces. These echoes can interfere with an accurate measurement.

Figure 16 shows a TDR plot measured using a daisy chain test configuration device that has loaded DDR2 memory elements at all sites of the daisy chain. Compared to the example of the no-memory component load shown in Fig. 15, the pattern shown in Fig. 16 shows a higher degree of reflection due to the DDR2 memory components due to the additional capacitive load. . Reflection occurs between 1 ns and about 4.5 ns.

Figure 17 shows a portion of a test configuration device that includes a plurality of DUTs and a circuit board 120 that commonly connects the DUTs to a common test pin pin through a branch node. In particular, the board 120 includes a branch node 121 to which the first and second conductors 122 and 123 are coupled, each of the conductors 122 and 123 being coupled to the other of the devices under test 124 and 125. And the board 120 includes a common (signal fed) transmission line 127 that extends to the interface of a device tester or to the test head of a device tester. The common transmission line 127 typically has a different impedance than the conductors 122 and 123. The transmission line 127 contains, for example, an impedance Z ₁ equal to 50 Ω. The first and second devices under test 124 and 125 can have a 60 Ω ODT terminal in parallel with a capacitance of, for example, 1.5 pF. As described, the circuit board 120 provides a test interface 126 for a device tester. Due to the 60 Ω of the elements under test, even if the impedance of the output lines 122, 123 is Z ₂ = 60 Ω, the elimination requirement is no longer satisfied. The devices under test 124 and 125 are, for example, GDDR5 memory elements having a 60 Ω real impedance.

The problem of how to set the impedance values of the wires 122 and 123 is solved in Fig. 18. Fig. 18 is a circuit diagram of the circuit board as shown in Fig. 17, having a symmetrical structure. The first wire 122 and the second wire 123 comprise an impedance Z ₂ =100 Ω. The first device under test 131 includes, for example, a 120 Ω resistor in parallel with 1.5 pF. The second device under test 132 also includes a 120 ohm resistor in parallel with 1.5 pF. Due to the symmetry condition, the branch node 121 terminates with the two wires 122, 123 each having a 100 Ω impedance, which is equivalent to the equivalent terminal of the 50 Ω branch node 121. The branch node 121 faces 50-50 of the side of the tester and the side facing the DUT is matched by 50 Ω, whereby the branch node 121 does not reflect. The reflections will only occur from the measured elements 131 and 132 having an impedance different from the impedance of the branches 122 and 123 by 100 Ω, whereby reflections from the two elements under test 131, 132 are transmitted to the branch node 121. However, this reflection of a DUT, such as 131, is cancelled by the reflected signal of another DUT, such as 132, refracting into the branch 122 at node 121. This erasing effect is the reason why the configuration device does not have multiple reflections. It generally requires twice the value of ₂ Z ₁ Z value. Due to the symmetrical structure of the circuit board 120 and the impedance matching between the transmission line 127 and the test interface 126, only one reflection occurs and it is eliminated in both branches without generating multiple reflected echoes. Thus, the board 120 allows for high measurement accuracy measurements of GDDR5 memory components.

However, the elimination of reflection is not easy to achieve. Fig. 19 shows a circuit diagram of a circuit board 120 as shown in Fig. 17, which illustrates the conditions of reflection erasure. Multiple reflections occur when a wire having a characteristic impedance is connected to another wire having another characteristic impedance. The first branch line 122 has a characteristic impedance Z ₂ coupled to a first device under test 133 having a characteristic impedance Z. If the characteristic impedance Z _{2 is} not equal to the characteristic impedance Z, a reflection r _X1 occurs between the first branch line 122 and the first device under test 133. If the second impedance line 123 having the characteristic impedance Z _{2 is} connected to a second device under test 134 having a characteristic impedance Z, wherein the characteristic impedance Z is not equal to the characteristic impedance Z ₂ , at the second branch line 123 and the first A reflection r _Y1 occurs between the two elements under test 134. If the characteristic impedance Z _{1 of the} signal transmission line 127 is different from the characteristic impedance Z ₂ , reflection also occurs at the branch node 121. For example, a wave is sent by the tester to transmission line 127 where an equal portion is refracted into the branch lines 122 and 123 and another portion is reflected back to the tester. Assuming that the tester matches the impedance Z1, the reflected portion is completely absorbed by the tester. However, the refracting portion propagates along the branches 122 and 123 toward the DUTs 133 and 134. Since the input impedances Z of the DUTs 133 and 134 are hardly matched to the branch lines 122 and 123, the reflections of the coefficients rx1 and ry1 occur, respectively. Reflected waves from the DUTs propagate toward the branch or bifurcation node 121. The impedance here does not match the branch line impedance. Thus, for the case of branch line 122, a portion of the signal rx2 is again reflected toward the DUT 133 and another portion is refracted into the feed line 127 and another branch line 123. However, the same situation occurs on the branch line 123. Here the portion by2 is refracted into another branch line and the portion by2 is refracted into the feed line 127. It can be shown that if the value of Z2 is twice the value of Z1, then rx2 has the same magnitude as by1 but has different signs and therefore cancels each other. This means that no more reflections will occur. However, this requires two branches to be perfectly symmetric in terms of impedance and length.

Figure 20a shows a circuit diagram of one of the daisy chain test configuration devices already mentioned above. The device uses a daisy chain sharing topology to measure the component under test. This daisy chain sharing topology is particularly suitable for testing high speed memory, such as for measuring a plurality of memory elements in the same test step.

A component tester 140 is coupled through a test interface 141 to a transmission line xy1 having a characteristic impedance Z (e.g., 50 ohms). This transmission line is terminated with its end so that no reflection occurs. The terminal is implemented by a matching resistor xy2 and a terminal power supply xy3 of a ground 155. The transmission line now performs joint measurement at points xy4, xy5, xy6, and xy7. The devices under test having a characteristic input capacitance 143 are connected to the connectors via stubs (short transmission lines, such as vias) and thereby distort the desired signal transmission on the transmission line xy1. Reflection occurs at each joint because the input capacitance and the capacitive behavior of the short lines each produce a short-circuiting effect at a first time or a very high frequency, respectively.

A reflection pattern 156 illustrates the reflections from the respective branch nodes 145, 146, 148, 150 from the short lines 152 and the parasitic input capacitances 143 from the respective device under test DUT1-DUT4. At each of the tested components, a reflection occurs, resulting in a distortion of the signal experienced by the previous DUT. (The tester is not used to evaluate this signal, it is used for driving.)

Figure 20b shows a TDR map measured using the conventional test configuration device as shown in Figure 20a. The TDR diagram illustrates the signal experienced by the first device under test DUT1. This signal contains three reflections, a first reflection 160 corresponding to a reflection from the second device under test DUT2, a second reflection 161 corresponding to a reflection from the third device under test DUT3 and a third reflection 162 corresponding to The reflection from the fourth device under test DUT4. The input impedance of the tester 140 and the termination impedance 153 are suitably matched to 50 Ω of the input lines, so no reflection occurs.

Figure 21a shows a timing diagram of the test signal. Four test signals v(10), v(11), v(12), v(13) are received at a test configuration device that uses a daisy chain sharing topology to use a sampling frequency of 2.5 Gbps. A pseudo-random binary sequence (PRBS) is used to test DDR memory components. The daisy chain sharing topology is a By-4 shared topology comprising four devices under test, each of the devices under test having a load impedance of 1.5 pF and a stub of 30 ps. Due to the reflection of the test signal originally transmitted by the component tester 140 shown in Fig. 20a, it can be seen in the timing diagram of Fig. 21a that the signals received at the respective devices under test contain a lot of signals from adjacent ones. Measure the reflection of the component. The received signals v(10), v(11), v(12), v(13) contain reflections from adjacent test elements in the originally transmitted test signal due to reflections from adjacent test elements. Signal component. This results in distortion experienced at the input of the DUTs. The signals experienced by the DUTs display a ringing that decays to a target planning value of 0.8V.

Figure 21b shows an eye diagram corresponding to a test signal which is the basis of Figure 21a. The eye diagram illustrates the test signal v(10) received at the first device under test DUT1 in accordance with the test configuration device as shown in Fig. 20a. The eye in the eye is almost closed due to the distortion of the received test signal v(10) caused by the reflection of the adjacent device under test. The overshoot and undershoot of the received test signal v(10) causes the eye to be distorted causing the eye to close.

As can be seen from the above graph, measuring the measured component including the specific parasitic capacitance and resistance that determines the input impedance of the device under test may cause problems due to reflection and reduce the sensitivity of the measurement. The reflections may be due to a missing-adjustment of the input impedance of the device under test to the transmission line connected to the component tester. In the case where more than one of the devices under test is connected to one of the test channels or one of the test interfaces (such as, for example, a daisy-chain topology), the reflections may also occur from reflections of adjacent test elements. . Especially for higher sampling frequencies required for new generation memory components such as, for example, GDDR5 memory components, accurate measurement becomes almost impossible. A solution is needed to eliminate unwanted reflections to make high precision measurements of the device under test easier.

Some embodiments of the present invention address the above mentioned problems by providing a test configuration apparatus including an interface for a device under test, the interface including an impedance matching circuit and the impedance matching circuit including A resistor is connected in parallel with an inductor.

Further, some embodiments of the present invention provide a spring pin comprising a first sleeve of a conductive material, a second sleeve of a conductive material, a tube of a resistive material, and a spring of a conductive material . The tube of the resistive material, the first sleeve and the second sleeve are slidably attached to each other along a common axis, wherein the tube is disposed between the first and second sleeves. The spring is used to separate the first and second tubes outwardly. The spring pin forms an inductance formed primarily by the spring in parallel with one of the resistors formed primarily by the barrel.

Some embodiments of the present invention comprise a spring pin comprising a first sleeve of electrically conductive material, a second sleeve of electrically conductive material, a tube of insulating material, a spring of electrically conductive material, and an elastic Resistive component. The first sleeve, the second sleeve, and the barrel are slidably attached to each other along a common shaft, wherein the tube is disposed between the first and second sleeves. The spring is used to separate the first and second tubes outward. The resilient element includes a resistive material attached between the first and second sleeves along the common axis. The spring pin forms a parallel connection of an inductor formed primarily by the spring to produce an inductor and a resistor formed primarily by the elastomeric component.

A further embodiment of the invention includes a spring pin comprising an elastomer body having a main longitudinal axis; and a conductive material embedded in the elastomer body for the elastomer A line extending between the top surface and the bottom surface of the body along the main longitudinal axis. The spring pin is assembled to form a parallel connection of an inductor formed by the lines to a capacitor.

A general idea of some embodiments of the present invention is to construct a test configuration device including a spring pin such that the input impedance matches the line impedance when the spring pin is coupled between the DUT and the connection transmission line. In such a case, no reflection occurs. Since the input impedance of a device under test is generally capacitive, an embodiment of the present invention provides an impedance matching circuit including a resistor in parallel with an inductor to match the normally capacitive input impedance of the device under test. . Thus, in accordance with these embodiments, the characteristics of the spring pins that are generally considered to be detrimental become advantages and are utilized. More specifically, a spring pin comprising a spring provides an inductive spring coil. Usually, it is interpreted as a parasitic element. However, in accordance with these embodiments, this inductance is used to form part of an impedance matching circuit. The spring pin is thus used to form an inductor and an ohmic resistor to provide an impedance matching circuit that can be placed in close proximity to the DUT.

Some embodiments of the present invention are based on the idea that an impedance matching circuit having improved matching performance can be obtained when the impedance matching circuit has a resistance equal to the resistance value of the input impedance of the device under test, for example, ±10 Within the tolerance of %, and an inductance equal to the square of the resistance value of the input impedance of the device under test multiplied by the capacitance of the input impedance of the device under test, such as, for example, within a tolerance of ±10%.

Figure 22a shows a wave diagram of light transmitted through an optical medium as shown in Figure 2a, however, wherein the optical medium has an optical film of an anti-reflective coating material thereon. The optical medium is, for example, a highly reflective glass. This coating material minimizes reflection.

One of the general ideas of some embodiments of the present invention is to transfer this idea from the field of optics to the field of electricity. When, as shown in FIG 22a of the transmission 20 via a lightwave optical media such as, e.g., glass having n ₁ refractive index of air with a different refractive index n _0, where n _1> n ₀ and the glass having an anti-reflective coating When the thin layer 21 of the layer material is used, the reflectance of the glass can be lowered. Passing through the thin layer 21 of the anti-reflective coating material, wherein the thin layer 21 of the anti-reflective coating material has a refractive index between the air refractive index n ₀ and the glass refractive index n ₁ , the light beam 20 reflects Twice: that is, one reflection from the surface between the air and the ARC layer 21, and one at a time from the interface of the ARC layer 21 to the glass 22. It can be shown that when the refractive index of the ARC layer 21 is a specific optimum value, the transmittances of the two interfaces are equal, and this corresponds to the maximum total transmittance of the glass. This optimal value is given by the geometric mean of the two surrounding indices:

For example, glass has a refractive index of approximately And the air has a refractive index n ₀ =1, and this optimal refractive index is about . An intermediate dielectric coating (anti-reflective coating, ARC) between air and glass reduces reflection losses.

The idea of transferring an optical anti-reflective coating to the field of electricity is shown in Figure 22b. Figure 22b shows a signal diagram of the electrical transmission line Z ₀ with the terminal impedance Z _in of the DDU under test as the terminal, Z _in and the impedance Z _{0 of} the transmission line being unequal, according to an embodiment of the invention An anti-reflection circuit (impedance matching circuit) 200 is connected between the transmission line 201 and the device under test 202. The ARC circuit 200 is an analog component between the two electrical media, that is, the transmission line and the terminal impedance of the device under test, and is analogous to the anti-reflective coating between the two optical media, that is, the air and the glass in FIG. 22a. A thin layer 21 of material. The anti-reflective coating circuit 200 can be designed to include a reflectance index between the reflectance index of the transmission line 201 and the reflectance index of the terminal impedance 202 of the device under test. The ARC circuit 200 can be designed to pass the reflection of the suppressed electric wave 203 such that the electric wave 203 flows through the transmission line 201 to the terminal impedance 202. An appropriately adjusted ARC circuit 200 suppresses the reflection of the electric wave 203 by about 99% whereby the energy of the electric wave 203 is transmitted to the terminal impedance 202 of the device under test.

Figure 23a shows a schematic diagram of a test configuration device 400 in accordance with an embodiment of the present invention. The test configuration device 400 includes an interface 401 for a device under test 404. The interface 401 includes an impedance matching circuit 402. The impedance matching circuit 402 includes a resistor R and an inductor L connected in parallel. The interface 402 includes a spring pin 403 that forms the impedance matching circuit 403. This is illustrated by the schematic representation 403b of the spring pin 403, which illustrates a circuit diagram of the parallel connection of the resistor R and the inductor L. The resistor R and the inductance L in the impedance matching circuit 402 can be formed by discrete electronic components that are arranged inside or (closer to) the spring pin 403. The embodiment of the spring pin 403 is depicted in Figures 27, 28, 29a and 29b.

The test configuration device 400 further includes a signal generator 405 for applying a test signal.

The test configuration device further includes the device under test 404 that includes an input impedance. The interface 401 is used to provide electrical coupling between the impedance matching circuit 402 and the input impedance of the device under test 404. The resistor R of the impedance matching circuit 402 and the inductor L are combined such that one of the impedance matching circuits 402 impedance matches the input impedance of the device under test 404.

Figure 23b shows a schematic diagram of a test configuration device 400 in accordance with another embodiment of the present invention, the embodiment being identical to the embodiment shown in Figure 23a except that the implementation of the impedance matching circuit 402 is different. The impedance matching circuit 402 includes a series connection of the spring pin 403 and an external electrical component 420. The external electrical component 420 includes a discrete resistor R and a discrete inductor L. The discrete resistor R and the discrete inductor L of the external electrical component 420 are assembled such that an impedance of the impedance matching circuit 402 (including the impedance of the spring pin 403 and the impedance of the external electrical component 420) matches An input impedance of the device under test 404.

The test configuration device 400 further includes a signal generator 405 for applying a test signal. For example, the test signal can have a mean frequency that is lower than the maximum frequency of the interface 401. The outer electrical component 420 is arranged against the spring pin 403, for example, less than a quarter of the electrical wavelength corresponding to the maximum frequency. The close distance produces better matching performance of the impedance matching circuit 402.

Figure 23c shows an equivalent circuit diagram of one of the test configuration devices in accordance with an embodiment of the present invention. The test configuration device includes a device under test DUT having an input impedance Z _in formed by a resistor R and a capacitor C connected in parallel. The test configuration device further includes an impedance matching circuit ARC (anti-reflective coating) having an impedance formed by the parallel connection of the resistor R and the inductor L. The impedance matching anti-reflection circuit ARC is connected in series with the device under test DUT, whereby the series connection of the impedance matching circuit ARC and the device under test DUT has an input impedance Z.

a calculation result of the input impedance Z

A resistor A of the input impedance Z _in of the device under test corresponds to a resistor R of the impedance Z _ARC of the impedance matching circuit ARC. If the condition L = R ² C is satisfied, the result of the impedance Z of the circuit is

Due to the elimination of the pole and the zero point in the equation shown above, the impedance Z of the circuit including the DUT connected in series to the impedance matching circuit is changed to correspond to the resistance R of the impedance matching circuit ARC and the device under test DUT. Real value. Thereby, the frequency dependence of the impedance Z is eliminated by the following matching conditions.

L=R ² C

Of course, the matching condition does not need to be 100% satisfied to provide a configuration that is advantageous over the mismatch. For example, the inductance L of the impedance matching circuit can be equal to the square of the resistance R of the input impedance multiplied by the capacitance C of the input impedance, within a tolerance of +/- 10%. Additionally, the impedance of the impedance matching circuit can be equal to the resistance of the input impedance, within a tolerance of +/- 10%.

If the resistance R is equal to the impedance Z ₀ of the transmission line connected to the circuit, then no reflection occurs at all. The impedance Z _{in of the} device under test DUT can be realized by a terminal ODT built in the chip and/or by a capacitor C _in (for example, a parasitic capacitance) built in the chip and an external resistor R.

Figure 23d shows a schematic diagram of a test configuration device 400 that includes a component tester, a test interface, and a plurality of interfaces for a plurality of devices under test, in accordance with an embodiment of the present invention.

Spring pin 403 can be applied to test system or test configuration device 400, respectively. In this embodiment, the test configuration device 400 includes a test head 407 or a component tester in which a pin-electronic module 410 and a corresponding tester driver 405 are located. The pin-electronic module 410 is connected by a cable 412 to a spring-connector 417 that is arranged on top of the test head 407. A test interface 406 is mated to the test head 407 to contact the spring connectors 417 to the test interface 406, such as the bottom edge of the test interface 406 or any other possible contact point. This mating can be implemented using a mechanical lock mechanism 416. The test interface 406 includes contact pads 413 that can be adapted to contact the spring connectors 413, wherein the contact pads 413 are coupled to the test interface 406 through a test interface cable 418. These test interface cables 418 terminate above the test interface 406 to connect a plurality of socket boards (or circuit boards) 408, 408b. The socket boards 408, 408b can be (small) PCBs (printed circuit boards), and also include (respectively) connecting the interfaces 401, 401b associated with the socket boards 408, 408b (or components under test) Contact area 414 of the socket). The interface 401 for the device under test 404 is associated with the socket plate 408, and the second interface 401b for the second device under test 404b is associated with the socket plate 408b. The interfaces (device sockets under test) 401, 401b can be screwed (or connected by a mechanical arrangement) to the contact area 414 of the socket plates 408, 408b using screws 415. The interfaces (device under test sockets) 401, 401b include (small) spring pin 403 which is small with respect to the spring-connector 417 of the test head 407. The spring pin 403 can have a length of, for example, about 2-3 mm. The test elements 404, 404b can be pushed into the interfaces (device sockets under test) 401, 401b, whereby the ball 419 of the ball grid array package (the test elements 404, 404b) is replaced by the spring pins 403 contact. Such contact provides a complete signal path connection between the device under test 404, 404b and a tester drive 405 or tester receiver 411, respectively. The spring pin 403 shown in Figure 23d can have a relatively short length of about 2-3 mm, and the cable 418 disposed within the test interface 406 has a length of about 40 cm.

A branch node 120 is formed by an input line 127, a first output line 122, and a second output line 123. The input line 127 is electrically connected between the test interface 406 and a branch node 121. The first output line 122 is electrically connected between the branch node 121 and the interface 401 for the device under test 404, and the second output line 123 is electrically connected to the branch node 121 and for the second device under test. Between the second interface 401b of 404b. The branch node 121 can be implemented on one of the (PCB) circuit boards 408, 408b or the test interface 406.

The input line 127, the first output line 122, and the second output line 123 may be a transmission line, a waveguide, a microstrip line, a strip conductor of a printed circuit board, a via hole, a connection (micro) strip line, and a high frequency microwave. Implemented with cables, connectors, interconnects or components, SMA adapters or coaxial cables. The lengths of the first 122 and second 123 output lines may be different. Output lines 122 and 123 can each be implemented on different layers of the boards 408, 408b.

Figure 23e shows a Nyquist plot of the input impedance Z of the test configuration device as shown in Figure 23c. The Nyquist diagram shows the frequency dependence of the input impedance through the representation of the real part Re(Z) and its imaginary part Im(Z). The test configuration device has an input impedance Z that is constant and is a real amount and is perfectly matched to the line impedance. Therefore, no frequency dependent reflections occur. The set value corresponds to the resistance R of the device under test DUT and the impedance matching circuit ARC.

Figure 24a shows an equivalent circuit diagram corresponding to a test configuration device including a GDDR5 memory device as shown in Figure 5, having an embodiment connected to the device under test and the transmission line in accordance with an embodiment of the present invention. Inter-impedance matching circuit ARC. The structure of this circuit corresponds to the structure as described in Fig. 23a. Corresponding to the GDDR5 memory component, a 60 Ω resistor and a 1.5 pF capacitor form a parallel connection of the input impedance of the DDU under test. The equal 60 ohm resistor is connected in parallel with an inductance of L = R ² C = 5.4 nH to form the impedance matching circuit ARC, whereby the impedance Z of the test configuration device becomes Z = R. A transmission line having an impedance Z ₀ = 60 Ω is connected to the other terminal of the impedance matching circuit. The impedance matching circuit of the impedance Z ARC achieved under test _in the DUT element matches impedance Z ₀ of the transmission line, whereby the reflection is suppressed.

Figure 24b shows a Nyquist plot of the test configuration device as shown in Figure 24a. Due to the impedance matching circuit ARC, the input impedance Z of the test configuration device is matched to R, whereby no reflection occurs for all frequencies from DC to almost infinite. This match point = R is the same point for all frequencies. A large reflection of about 0% r and a transmission of about 100% of b can be obtained.

Figure 25 shows a GDDR time domain reflectance of an input impedance Z measured using the test configuration device as shown in Figure 24a. The signal V(2) corresponds to a measured signal at a TDR receiver. Due to the matching condition, the energy of the signal is completely absorbed in the series connection of the impedance matching circuit ARC and the device under test DUT whereby no reflection is reflected to the TDR receiver and the received signal V(2) shows no reflection. Or echo. The transition between 0 and 100 ns is used to indicate the non-ideal rise time of the tester driver.

Figure 26 shows a comparison of the voltage at the DUT of the test configuration device as shown in Figure 24a with the voltage at the input impedance of the conventional device under test shown in Figure 4a. Sequence diagram. The voltage V(40) at the DUT under test has a rise time that is greater than the voltage V(4) at a DUT of a test device that does not have an impedance matching circuit ARC. Generally, the step response of a configuration device having and without a matching circuit ARC can be roughly described using an exponential function f(t) = alpha * (1-exp(-t/tau)). The introduction of the matching circuit ARC increases the time constant by a factor of roughly 1 + R / Z0. This voltage V(40) reaches 95% of the transition voltage of 550 mV after about 500 ps, and this voltage V(4) reaches 95% of the transition voltage voltage of 550 mV after about 450 ps. Considering that a transition state of the voltage starts at a time of about 200 ps, the voltage V(40) at the device under test including the impedance matching circuit requires about 400 ps to transition, and the impedance matching circuit does not include the impedance matching circuit. The voltage V(4) at the device under test requires approximately 250 ps to transition. This difference of 150 ps is a result of the transmission of the matching circuit ARC due to signal transmission through the electrical circuit.

There are different alternative ways to implement the ARC circuit between the DUT and the transmission line within the test set as outlined above. Some embodiments are described below.

Figure 27 shows a cross-sectional view of a spring pin for connecting a device under test 210 to a interface 214 of a test head in a test configuration device in accordance with one embodiment of the present invention. In particular, the test configuration device includes a device under test package 210 having a connection ball 211 that is coupled to a BGA on a circuit board via a spring pin 212 in a socket 213 under test. (Pellet array) pad 214, which is specifically designed for the device under test and is itself connected to a tester or a portion thereof. The spring pin 212 is used to contact the package ball 211 of the device under test 210 to the BGA pad 214 of the device under test. A retractable spring 215 belonging to and within the spring pin 212 produces the force required to securely contact the ball 211 and pad 214, respectively.

The spring pin 212 includes a first sleeve 216 of electrically conductive material, a second sleeve 217 of electrically conductive material, a tube 218 of a resistive material, and the spring 215. The spring 215 is made of a conductive material and is used to separate the first sleeve 216 and the second sleeve 217. The first sleeve 216, the second sleeve 217 and the tube 218 are slidably attached to each other along a common shaft 219 of the tube 218, wherein the resistive tube 218 is positioned in the first sleeve Between the barrel 216 and the second sleeve 217. The first sleeve 216 and the second sleeve 217 may have the same diameter as compared with the spring pin shown in FIG. 6, whereby one of the sleeves does not slide into the other sleeve. In contrast to the spring pins shown in Figures 6 and 8, the inner tube 40 slides into the outer tube 42 in the spring pins shown in Figures 6 and 8.

The adaptability of the longitudinal extent of the spring pin is achieved by the tube 218 which slides into the first sleeve 216 and the second sleeve 217. The spring 215 is attached to the tube 218 at a contact field 220. The spring 215 can be placed over the first sleeve 216 and the second sleeve 217, for example in accordance with the mechanisms shown in Figures 7a and 7b. The spring pin 212 forms a parallel connection of an inductance formed primarily by the spring 215 with a resistor formed primarily by the barrel 218. This parallel connection corresponds to the impedance matching circuit ARC as shown in Figs. 23a and 24a.

The spring pin 212 can be obtained by making the resistance formed by the tube 218 correspond to a resistance of the device under test and the inductance formed by the spring 215 is corresponding to the square of the resistance multiplied by the capacitance of the device under test. To manufacture. The spring pin 212 can be fabricated for such particular needs of a particular device under test, for example, for a GDDR5 memory component. A new generation of memory components may require a new spring pin 212 with components suitable for the new memory component.

It should be noted that the spring pin of Fig. 27 can also be designed such that the spring coil 215 contacts the sleeve only at a position that maintains contact with the spring at all possible degrees of compression of the spring pin. a cartridge and/or the resistive tube. By appropriately selecting the size and material, the ARC circuit as described above can be implemented by using a spring pin shown in Fig. 27a.

Figure 28 is a cross-sectional view showing a test configuration device in accordance with another embodiment of the present invention. The test configuration device corresponds to the test configuration device as shown in Fig. 27, except that another spring pin 222 is used. The spring pin 222 includes a first sleeve 226 of a conductive material, a second sleeve 227 of a conductive material, and a spring 225 of a conductive material for separating the first sleeve 226 and the second sleeve 227. A tube 228 of insulating material and an elastic member 223. The first sleeve 226, the second sleeve 227 and the tube 228 are slidably attached to each other along a common shaft 229, corresponding to the spring pin 212 as shown in Fig. 27, except for the tube 228. Made of insulating material instead of conductive material. Further, the spring pin 222 includes a resilient member 223 that includes a resistive material such as, for example, a resistive elastomer, attached between the first sleeve 226 and the second sleeve 227 along a common axis 229. . The elastomer is laterally insulated and resistive in the machine direction. This can be accomplished with thin wires extending longitudinally and laterally through the elastomeric member 223, thus electrically coupling the sleeves 226 and 227 from the interior.

The spring pin 222 forms an inductance formed primarily by the spring 225 in parallel with one of the resistors formed primarily by the elastomeric member 223. Since the insulating barrel 228 can be made of a material such as, for example, PTFE (Teflon), an electrical circuit is transmitted from the first sleeve 226 through the spring 225 and the elastic member 223 to the second sleeve. The barrel 227 is formed. The electrical circuit is not formed by the tube 228. This feature distinguishes the spring pin 222 shown in Fig. 28 from the spring pin 212 shown in Fig. 27.

However, other embodiments of the present invention may include a spring pin 222 having a tube 228 of a resistive material and a resilient member 223 of a resistive material whereby an electrical circuit is utilized by the spring 225 and The resistance of element 223 is formed in parallel with the resistance of barrel 228.

As described above, the elastic member 228 can include an elastomer having a main longitudinal axis corresponding to the common shaft 229 and embedded in the elastomer body to extend along a major longitudinal axis of a top surface of the elastomer to A line of electrically conductive material extending between a bottom surface. The wires of the electrically conductive material may be, for example, carbon or gold wires. The resilient member 228 can be coated with a coating of insulating material to prevent shorting between the inductance formed by the spring 225 and the resistance formed primarily by the elastomeric member 223. Alternatively, the spring 225 can have an insulating coating. The spring 225 can be a helical spring or any different kind of spring to separate the first sleeve 226 and the second sleeve 227.

Figure 29a shows a top view of a test configuration device in accordance with an embodiment of the present invention. The test configuration device includes a spring pin 232 that includes an elastomer body 233 having a main longitudinal axis 234. The spring pin 232 further includes a wire 235 of electrically conductive material embedded in the elastomer body 233 to extend along the main longitudinal axis 234 between the top surface 236 and the bottom surface 237 of the elastomer body 233. The spring pin 232 forms a parallel connection of an inductor and a resistor, both formed by a wire 235. A magnetic field of, for example, 5 nH corresponding to the inductance of the spring pin 232 is formed by the lines 235. The lines 235 are embedded in the body 233 in such a manner that the lines 235 are electrically interrupted between each other in the body 233. The top surface 236 and the bottom surface 237 can include a conductive material to electrically contact the spring pin 232 to a device under test 210 and a device under test. The line 235 can be a carbon line resulting in a total resistance of 50 ohms. The spring pin 232 can be used as a common pin. In this embodiment of the invention, the body 233 is a cylindrical body. However, in other embodiments, the body 233 can have another form and another cross section such as, for example, a cube shape.

Figure 29b shows a top view of a test configuration device in accordance with another embodiment of the present invention. The test configuration device includes a spring pin 242 that is similar in construction to the spring pin 232 as shown in Figure 29a, except that the wire 245 is made of gold to obtain a 1Ω resistor. The low resistance gold wires 245 provide a low inductance of the spring pin 242 whereby the spring pin 242 can be used as a power source or a non-share pin. The spring pin 242 is primarily assembled for contact purposes and is not intended for matching purposes as compared to the spring pin 242, which is primarily assembled for matching purposes as shown in Figure 29a. The spring pin 232 as shown in Fig. 29a can also be used for the elastic member 225 as shown in Fig. 28. Likewise, the spring pin 242 as shown in Fig. 29b can be used for the resilient member 225.

A main idea of the design of the spring pin as shown in Figures 29a and 29b is to adjust the cylindrical spring pin by increasing or decreasing the diameter of the cylindrical body by the relationship between the diameter and the inductance of the cylindrical object. The inductance of the pins 232, 242. The inductance of a cylinder is a function of its diameter. A thin cylinder has a higher inductance than a thick cylinder. The gold wires 245 are assembled to increase the electrical conductivity of the spring pin 242. The spring pin 242 includes the gold wires arranged along the overall diameter of the elastomer, and the spring pin 232 includes the wire 235 disposed only within the inner portion (core) of the diameter of the elastomer. Thus, the spring pin 242 as shown in Fig. 29b, such as the spring pin 232 shown in Fig. 29a, has a low inductance.

Figure 29c shows an array of spring pin pins of the spring pins 232 and 242 as shown in Figure 29a/b. The spring pins 232, 242 have a bottom surface 237 that is coupled to a common electrode 246. The test device can be used to form a pressure sensitive conductive rubber (PCR) socket. The socket can be used to connect a printed circuit board or other high performance logic components. Large processors, controllers, and other integrated circuits (ICs) require a specific outlet. These sockets can be PCR sockets that provide less force per pin, higher current delivery capacity, and electrical performance up to 20 GHz. The pitch can be as low as 0.25 mm, an alternating current (AC) performance of 20 GHz and a life cycle of 200,000 times. The PCR socket is designed to be compatible with existing spring pins or stamped contacts and implemented to increase yield and system up time. The PCR elastomeric junction provides a high performance and virtually invisible component footprint. Spring pins as illustrated in Figures 29a and 29b can be used in PCR sockets. Depending on the need, some spring pins 242 can be used for both the power supply and the non-common pins, while other spring pins 232 can be used as contact pins for the impedance matching circuit and an anti-reflection socket spring pin. The role.

Figure 30 shows an equivalent circuit diagram of a test configuration apparatus including an impedance matching circuit 250, a TDR transmitter 251, and a TDR receiver 252, in accordance with an embodiment of the present invention. The TDR transmitter 251 and the TDR receiver 252 are connected to a circuit through a coaxial cable 253. The circuit includes the impedance matching circuit 250 pre-connected to the DUT under test. The DUT has an 11pF capacitor. And a 50 Ω resistor connected in parallel to form an impedance Z _in . The coaxial cable 253 can have a length of 20 cm and a diameter of 5 mm. The impedance matching circuit 250 by a system for avoiding the impedance of the coaxial cable 253 and the reflective element under test DUT impedance Z _in the resulting mismatch.

Figure 31 shows a TDR map measured using the test configuration device as shown in Figure 30, the test configuration device including the impedance matching circuit 250. Compared with a measurement shown in FIG. 11 that does not include the impedance matching circuit 250, the TDR pattern shown in FIG. 31 shows almost no reflection except by the impedance matching circuit 250 after about 2.1 ns. A small reflection caused by a parasitic equivalent series inductance (ESL) of the series resistor R. However, the reflection caused by the parasitic ESL is negligible compared to a circuit that does not include an impedance matching circuit 250. A lower value for the inductance of the impedance matching circuit 250 compensates for the parasitic ESL of the resistance R of the impedance matching circuit 250. Due to the small distortion of the TDR signal, the test configuration device including impedance matching circuit 250 allows for measurements with higher sampling frequencies and, in turn, high accuracy measurements for fast memory components, such as GDDR5 memory components.

Figure 32 is a diagram showing an equivalent circuit diagram of a test configuration device including an impedance matching circuit 250 corresponding to the test configuration device shown in Figure 30, and a test configuration corresponding to that shown in Figure 30. A TDR transmitter 251 and a TDR receiver 254 of the device. An RTL (rise time limit) circuit is coupled between the TDR transmitter 251 and the surface microstrip transmission line 255 to limit the rise time of the signal generated at the TDR transmitter 251 to a value of 250 ps. The surface microstrip transmission line 255 is coupled to the impedance matching circuit 250 _in series with the device under test DUT having the input impedance Zin formed by an 11 pF capacitor and a 50 Ω resistor in parallel.

The configuration device is configured to apply the slow TDR measurement (30 ps rise time) as shown in FIG. 30 and the slower TDR measurement (250 ps rise time) as shown in FIG. The performance of the impedance matching circuit 250 and the DUT under test is tested, and the rise time of the slower TDR measurement is more suitable for the rise time of the tester (about 200 ps).

Figure 33 shows an eye diagram of a signal received by the TDR receiver 254 of the test configuration device as shown in Figure 32. The eye diagram shows an almost open eye that is only minimally disturbed by the small reflection 260 due to the parasitic ESL of the impedance R of the impedance matching circuit 250. The distortion in the eye diagram including an impedance matching circuit 250 as shown in Fig. 33 is substantially smaller as compared with the eye diagram of the test configuration device having no impedance matching circuit 250 as shown in Fig. 12. . A test configuration device comprising an impedance matching circuit 250 or an anti-reflection circuit respectively allows for an accurate measurement with accuracy, even at high sampling rates. The test configuration device as shown in Figure 32 is well suited for measuring high rate sampling devices, such as GDDR5 memory components.

Figure 34a shows a schematic cross-sectional view of a test configuration apparatus including an SMA adapter 300 in series with an impedance matching circuit 301 in accordance with an embodiment of the present invention. The coaxial cable (not shown) is terminated. The impedance matching circuit 301 includes a 27nH inductor 303 in parallel with a 50Ω resistor 304. The 50Ω resistor is implemented in parallel with one of two 100Ω resistors to reduce the parasitic ESL.

The ODT load simulation 302 is implemented by a parallel connection of an 11 pF capacitor 305 and a 50 Ω resistor 306. The capacitor 305 of the ODT load simulation 302 is implemented by a parallel connection of a 10 pF capacitor and a 1 pF capacitor. The resistor 306 is implemented in a parallel connection of two standard 100 ohm resistors. The circuit of the impedance matching circuit 303 and the ODT load simulation 302 are coupled between a core 307 and a ground connection 308 of the SMA adapter cable 300. The electronic components are discrete components such as, for example, SMD components.

Figure 34b shows an equivalent circuit diagram of the test configuration device as shown in Figure 34a. The impedance matching circuit 301 is in series with the ODT load simulation 302 of the device under test. The inductor 303 is 27 nH, both resistors 304, 306 are 50 Ω and the capacitor 305 is 11 pF. The impedance matching circuit 301 is sized such that the resistance 304 of the impedance matching circuit 301 corresponds to the resistance 306 of the ODT load simulation and the inductance 303 of the impedance matching circuit 301 corresponds to the square of the resistance 306 of the ODT load simulation 302. The ODT load simulates the capacitance 305 of 302. This matching condition guarantees suppression of unwanted reflections. Due to the tolerance-effect properties of the electrical components, the components 303, 304 of the impedance matching circuit 301 can be varied within an allowable region, for example, optimally determined by the matching conditions shown above. The value is around 10%.

Figure 35 shows a Smith chart of a reflection coefficient measurement of the test configuration device as shown in Figure 34a. Compared to the Smith chart of the reflection coefficient of the SMA adapter cable that does not include the impedance matching circuit, the Smith chart of the reflection coefficient of the test configuration device including the impedance matching circuit 301 shown in Fig. 35 shows that for almost Matching characteristics for all frequencies. This measurement is performed from a DC frequency up to a frequency of approximately 1 GHz. Even at a frequency of about 1 GHz, the reflection coefficient r has only a very small complex amplitude as compared with the reflection coefficient r as shown in Fig. 14. The remaining offset from zero may be produced by an equivalent series inductance of the resistor 304 of the impedance matching circuit 301 corresponding to the measurements as shown in FIGS. 31 and 33.

Figure 36 shows an equivalent circuit diagram of a test configuration device comprising two impedance matching circuits 320, each impedance matching circuit and a device under test 321, a TDR transmitter 322 and a respective TDR receiver. 323 is associated. The test configuration device further includes a Y-cable 324 to connect the TDR transmitter 322 to the two devices under test 321 . The TDR transmitter 322 includes an RTL circuit for limiting the rise time of the signal generated by the TDR transmitter to 250 ps. The Y-branch cable has a Y structure including a transmission line 325, a first conductor 326, and a second conductor 327. The wire 325 is connected to the first wire 326 and the second wire 327 through a via hole. The transmission line 325 has a 50 ohm impedance and can be implemented with a Gom cable having a length of 1 m and a diameter of 5 mm. The first and second conductors 326, 327 have an impedance of 50 ohms and can be implemented with a Rosenberger cable having a length of 20 cm and a diameter of 5 mm. The Y-branch cable further includes an SMA adapter cable 327 coupled between the first conductor 326 and an output of the Y-branch cable to produce a desired length lost pair. The SMA adapter cable has a length of 3 cm. The output of the SMA adapter cable 327 is coupled to the impedance matching circuit 320 of the first device under test and the output of the second output cable 327 is coupled to the impedance matching circuit 320 of the second device under test. Through the asymmetric structure of the Y-branch cable 324, the results due to the asymmetrical line length can be measured.

Figure 37 shows a TDR map measured using the test configuration device shown in Figure 36. The TDR measurement shows that although the Y-branch cable 324 has an asymmetrical configuration, no reflection occurs at the measurement point at which the TDR receiver 323 measures the received signal at the device under test 321 . Due to the impedance matching circuit 320 matching the impedance of the device under test 321, the reflection is eliminated in the circuit including the impedance matching circuit 320 and the device under test 321 . The reflections returned from the Y-branch cable to the TDR transmitter 322 are eliminated in the TDR transmitter 322, whereby they do not affect the measurement at the device under test 321 .

Figure 38 shows an equivalent circuit diagram of a test configuration device comprising two impedance matching circuits 320, each impedance matching circuit and a device under test 321, a length mismatched Y-branch cable 324 A test signal transmitter 330 and a test signal receiver 331 are associated. The Y-branch cable 324, the impedance matching circuit 320, and the device under test 321 correspond to the circuits as shown in FIG. The test configuration device differs in the type of measurement, such as the test configuration device shown in FIG. 36 for a time domain reflectometry, and the test configuration device as shown in FIG. 38 for signal measurement such as For example, it is used to measure an eye diagram at the device under test 321 . The test signal transmitter 330 can be a one bit error rate tester (BERT) or a pseudo random binary sequence (PRBS) generator.

Figure 39 shows an eye diagram measured using the test configuration device as shown in Figure 38. This eye diagram shows no distortion due to reflection. However, the rise time is reduced compared to the test configuration device having a signal transmission line as shown in Fig. 32. A rise time of approximately 800 ps is measurable between the 20% transition point and the 80% transition point. This eye diagram shows that a symmetrical Y-branch cable is not required for measuring the component under reflection without reflection. The elimination condition Z ₂ = 2‧Z _{1 is} no longer needed, where Z ₂ describes the respective impedances of wires 326 and 327 and Z ₁ describes the impedance of the transmission line 325 in the Y-branch cable. Therefore, due to the matching of the impedance matching circuit 320, the cable length need not be considered. The Y-branch shared cable can be sized as needed for the component under test without regard to symmetrical conditions. A shorter cable will increase the rise time and a droop compensation will give an additional boost to these rise times.

This then means that a test configuration device in accordance with the present invention requires fewer design constraints, particularly for branch nodes. The input line, the first output line and the second output line may comprise a transmission line, a waveguide, a microstrip line, a strip conductor of a printed circuit board, a via hole, a connection (micro) strip line, a high frequency microwave cable, a connector, an interconnect or component, an SMA adapter, a coaxial cable, and the output line can be offset from a symmetrical condition, ie, for example, the impedance of the first output line deviates from the impedance of the second output line by more than 5% Or the impedance of the impedance of the first output line in parallel with the impedance of the second output line is offset from the impedance of the input line by more than 5%. Alternatively or additionally, the lengths of the output lines/branch may be offset by more than 1%, the impedances of the tested elements may be offset from each other by more than 1%, and/or the first output line is on the circuit board Formed on another layer different from the second output line, the three lines are connected to the common input line through the via holes and thus are asymmetrical.

Figure 40 is a circuit diagram showing a test configuration device including the branch circuit board 120 as shown in Figure 17 and connected to respective output lines 122, 123 and the present invention, in accordance with an embodiment of the present invention An impedance matching circuit 340 between the respective impedances of the devices DUT1 and DUT2 to be tested. Through the impedance matching circuit 340, no reflection occurs at the branch end, whereby an erasing condition (Z ₂ = 2Z ₁ ) becomes unnecessary. When the impedance Z ₁ of the input line is 60 Ω, an impedance Z _{2 of the} output lines may be 60 Ω. Symmetry is no longer required, for example, length matching is no longer required. These rise times are significantly faster because the line impedance is significantly lower. For example, by the impedance Z ₂ =60 Ω of the output lines, an equivalent line impedance of 30 Ω can be achieved to increase the rise time. The DUTs 1 and DUT2 can be GDDR5 memory elements.

Figure 41 shows an equivalent circuit diagram of a test configuration device comprising two devices under test DUT1, DUT2, in accordance with an embodiment of the present invention. For the Y-branch 120, the DUTs 1, DUT2, and the impedance matching circuit ARC, the test configuration device corresponds to the test configuration device as shown in FIG. The impedance matching circuit 340 is represented by a parallel connection of a 5.4 nH inductor and a 60 Ω resistor. The components of the impedance matching circuit 340 are sized according to the matching conditions: an equal resistance of the impedance matching circuit 340 and the impedance of the device under test and an inductance of the capacitance of the device under test multiplied by the square of the resistance. A signal generator 350 is coupled to the test interface 126 and is used to generate test signals for testing the DUTs 1, DUT2.

Figure 42 shows a simulated eye diagram of a first input signal v(10) of the test configuration device as shown in Figure 41. This sampling time is 2.5 Gbps. The signal generator 350 produces a ²⁷ pseudorandom binary sequence (PRBS). Using a rising time t _R as shown in Figure 39 and as shown in FIG. 38 of the test device configured amount measured 800ps rise time compared to a value reduced to about 130ps. The increase in rise time t _R is the result of the impedance matching circuit required to avoid such reflections.

Figure 43 shows an equivalent circuit diagram of a test configuration apparatus comprising four components DUT1, DUT2, DUT3, DUT4, in accordance with an embodiment of the present invention. The test configuration apparatus includes a microstrip line 360 coupled between a test interface 126 for a device tester 350 and a series connection of the impedance matching circuit ARC and the device under test DUT1-DUT4. The microstrip line 360 includes four branch nodes 361, 362, 363, and 364, whereby the impedance of the microstrip line 360 between the test interface 126 and the first branch node 361 is 25 Ω, at the first The impedance of the microstrip line 360 between the branch node 361 and the second branch node 362 is 33 Ω, and the impedance of the microstrip line 360 between the second branch node 362 and the third branch node 363 is 50 Ω and The impedance of the microstrip line 360 between the third branch node 363 and the fourth branch node 364 is 100 Ω. The microstrip line 360 can be sized such that the impedance of the output line between the respective branch nodes 361-364 and the impedance matching circuits ARC connecting the respective devices under test DUT1-DUT4 is approximately 100 Ω. The branch nodes 361-364 are arranged on the microstrip line 360 and between the test interfaces 126 thereby forming a resistive line element 365, wherein each resistive line element 364 has a resistance of 100 ohms. The microstrip line 360 includes four resistive line elements 365 connected in parallel between the test interface 126 and the first branch node 361 for a total of 25 ohms. The three resistive line elements 365 are connected in parallel between the first branch node 361 and the second branch node 362, and have a total resistance of 33 Ω. The two resistive line elements 365 are connected in parallel between the second branch node 362 and the third branch node 363, and have a total resistance of 50 Ω. A resistive line element 365 is connected between the third branch node 363 and the fourth branch node 364 for a total of 100 Ω.

Figure 44 shows a signal diagram of the four input signals of the test configuration device as shown in Figure 43. The signals v(10), v(11), v(12), and v(13) are measured at the respective device under test DUT1-DUT4. Although the microstrip line 360 exhibits a highly asymmetrical structure, the signals v(10)-v(13) are cancelled due to the pre-connected impedance matching circuits ARC that cancel the reflections from the devices DUT1-DUT4. There is no reflection.

It is to be noted that the reflection that would occur when there is no impedance matching circuit ARC is generated by the inputs of the devices DUT1-DUT4 rather than by the asymmetric microstrip line 360. This bus-like structure (asymmetric microstrip line 360) requires an impedance matching circuit ARC for a desired function. Thus, in contrast to a Y-structure (such as the Y-branch 120 shown in Figure 41), no elimination conditions are defined for the bus-like bus structure (asymmetric microstrip line 360).

Figure 45 shows an eye diagram of the first input signal v(10) of the test configuration device as shown in Figure 43. This eye diagram is not distorted by reflection. However, a rise time of approximately 200 ps affects the eye pattern such that the eye is not fully opened. Compared with the measurement without the impedance matching circuit ARC as shown in Fig. 22b, the eye pattern as shown in Fig. 45 is opened wider, thereby measuring with higher accuracy in, for example, GDDR5 memory. Components are possible. The distortions visible in the eye diagram as shown in Fig. 21b are eliminated in the eye diagram as shown in Fig. 45.

Figure 46 shows a schematic diagram of a test configuration device that includes an impedance matching circuit ARC. In particular, Figure 46 will show a circuit board having an array of pads 371 for electrically connecting to the pads of a DUT. To this end, the lateral distribution of the spacers 371 can follow the footprint of the DUT and the distribution of the pads. Although each of the pins 371 can have an ARC, Figure 46 shows only one ARC of a representative shim 372. The ARC is coupled to the contact pad 372 via a first transmission line 381. The first transmission line 381 is implemented, for example, as a signal trace embedded in the circuit board and connected by a via 382 to an outside of the circuit board. The contact pad 372 is formed on the surface. The distance between the ARC and the spacer 372 is long via the first transmission line 381 and the via 382 can have a smaller than a quarter of the average wavelength λ of a test signal used to test the DUT via the pad 372. length. The contact pads 371, 372 can be arranged in a symmetrical configuration to form a ball array (BGA).

The impedance matching circuit ARC includes a parallel connection such as an inductor (such as a line art inductor having, for example, L = 6.2 nH) and a discrete element of a resistor (for example, 60 Ω). The inductor and the resistor element can be stacked one on another as shown in Fig. 46. Both can be arranged on top of the outer surface of the circuit board forming the spacers 371. For example, the ARC circuit is formed by an SMD portion. A via 383 can connect the ARC to the transmission line 381. At the other end of the ARC, it can also be connected to a wire, which is then connected to a tester or test head. For example, a via 384 and a trace 385 can be connected to the ARC such that the ARC is connected in series between the traces 385 and 381. Trace 385 can be connected to a bifurcation node that is formed on the circuit board as described in the foregoing embodiments. Alternatively, the non-forked node may appear between the ARC and one of the tester signal generators.

Figure 47 shows the signals measured by the discrete component ARC impedance matching circuit as shown in Fig. 46 and the signal measured by a spring pin ARC impedance matching circuit as shown in Fig. 42. Compare one of the timing diagrams. The spring pin ARC measurement signal V(8) has a slightly faster rise time than the discrete component ARC measurement signal V(80). Since the length of the transmission line 381 contacting the contact pad of the device under test to the ARC impedance matching circuit is less than a quarter wavelength of the wavelength of the test signal, the mismatch condition is no longer valid. The inductance L of the impedance matching circuit ARC should be matched to an input impedance of the device under test having a transmission line having a length less than a quarter of a wavelength of the test signal. A value of 6.2 nH was found to adjust the impedance matching circuit ARC almost optimally to suit the new input impedance of the device under test. The impedance matching circuit ARC produces a function as a moderate and benign low pass filter. A drop compensation circuit in the tester pin electronic card will be able to compensate for this low pass characteristic. Thereby an obvious eye opening can be obtained. Since the input capacitance C of the sensing element by the limitations _in rise time for that, it is the future due to the memory element _in the new generation of lead C will increase proportionally reduced by the rise time. The embodiments of the present invention comprising an impedance matching circuit ARC are scalable and the reflection does not limit the speed.

10. . . Upper part of optical material

12. . . Lower part of optical material

14. . . lens

16/18. . . Light

20. . . beam

twenty one. . . Thin layer/ARC layer of anti-reflective coating material

twenty two. . . glass

twenty four. . . electric signal

30. . . Spring pin

32. . . Device socket under test

34. . . Gasket/pin

36. . . ball

38. . . Tested component package

40. . . Housing/inner tube

42. . . Shell/outer tube

44/50. . . spring

52. . . Inner tube

54. . . Piston part

56. . . Contact part

58. . . Spring fixed part

60. . . Internal part

62. . . Contact stroke

64. . . End

66. . . Outer sleeve

72. . . Large diameter part

74. . . Small diameter hollow part

81. . . Measurement curve

82. . . Measurement curve

90. . . Time interval of reflection that causes eye distortion

91. . . Time interval of data bits

100. . . SMA adapter

101. . . Signal terminal load simulation

102. . . capacitance

103. . . resistance

104, 105. . . Capacitor

106. . . Resistor

120. . . Circuit board

121. . . Branch node

122. . . First wire / first output line

123. . . Second wire / second output line

124, 125. . . Measured component

126. . . Test interface

127. . . Transmission line

131~134. . . Measured component

140. . . Device tester

141. . . Test interface

143. . . Parasitic input capacitance

145,146,147,148,150. . . Branch node

152. . . Short line

153. . . Terminal impedance

155. . . Ground terminal

156. . . Reflection map

160. . . Reflection from DUT2

161. . . Reflection from DUT3

162. . . Reflection from DUT4

200. . . Impedance matching circuit

201. . . Transmission line

202. . . Terminal impedance of the device under test / device under test

203. . . Radio wave

210. . . Tested component package

211. . . ball

212. . . Spring pin

213. . . Device socket under test

214. . . Ball grid array pad on the socket board

215. . . spring

216. . . First sleeve

217. . . Second sleeve

218. . . Tube

219. . . Shared axis

220. . . Contact domain

222. . . Spring pin

223. . . Elastic component

225. . . spring

226. . . First sleeve

227. . . Second sleeve

228. . . Tube

229. . . Shared axis

232. . . Spring pin

233. . . Elastomer body

234. . . Main longitudinal axis

235. . . Carbon wire

236. . . Top surface

237. . . Bottom surface

247. . . Kernel

242. . . Spring pin

245. . . Gold Line

246. . . electrode

250. . . Impedance matching circuit

251. . . TDR transmitter

252. . . TDR receiver

253. . . Coaxial cable

254. . . TDR transmitter

255. . . Surface microstrip transmission line

260. . . Small reflection

300. . . SMA adapter

301. . . Impedance matching circuit

302. . . ODT load simulation

303. . . inductance

304. . . resistance

305. . . capacitance

306. . . resistance

307. . . Kernel

308. . . Ground connection

320. . . Impedance matching circuit

321. . . Measured component

322. . . TDR transmitter

323. . . TDR receiver

324. . . Y-branch cable

325. . . Coaxial cable/transmission line

326. . . Coaxial cable / first wire

327‧‧‧Second wire/SMA adapter cable/second output cable

330‧‧‧Bit rate tester/pseudo-random binary sequence/signal source

331‧‧‧Test signal receiver

340‧‧‧ impedance matching circuit

350‧‧‧Signal Generator

360‧‧‧Microstrip line

361/362/363/364‧‧‧ branch node

365‧‧‧Resistive line components

371‧‧‧Sand Array

372‧‧‧shims

381‧‧‧First transmission line

382~384‧‧‧Through hole

385‧‧‧ signal line

400‧‧‧Test configuration device

401‧‧‧ interface

402‧‧‧ impedance matching circuit

403‧‧ ‧ spring pin

403b‧‧‧Schematic representation of the spring pin

404‧‧‧Measured components

405‧‧‧Signal Generator

420‧‧‧External electrical components

401b‧‧ interface

404b‧‧‧Measured components

406‧‧‧Test interface

407‧‧‧Test head

408/408b‧‧‧ socket board

410‧‧‧ pin-electronic module

411‧‧‧Tester Receiver

412‧‧‧ cable

413‧‧‧Contact pads

414‧‧‧Contact area

415‧‧‧ screws

416‧‧‧Mechanical lock mechanism

417‧‧‧Spring connector

418‧‧‧Test interface cable

419‧‧ ‧ ball

R/R _ODT ‧‧‧resistance

C/C _IN ‧‧‧ capacitor

L‧‧‧Inductance

Z/Z _IN /Z _ARC /Z ₁ /Z ₂ ‧‧‧ Impedance

F1‧‧‧ frequency

R‧‧·reflection coefficient

B‧‧‧refractive index

n ₀ /n ₁ /n _ARC ‧‧‧Reflection index

S11/S12/S21/S22‧‧‧S parameters

t _R ‧‧‧ rise time

Figure 1 shows a beam diagram in which light is reflected by an optical material or through an optical material, depending on an optical anti-reflective coating of the optical material, to illustrate the embodiments of the invention described below. One of the main ideas of the foundation;

Figure 2a shows a schematic view of the scene of Figure 1, that is, the optical transmission of an optical medium having a different reflection index than the reflection index of the surrounding air;

2b is a schematic diagram showing an electrical transmission line connected to a device under test according to the optical arrangement device shown in FIG. 2a, the device under test having an impedance different from the impedance of the transmission line;

Figure 3a shows an equivalent circuit diagram of the input impedance of a device under test, including a resistive "terminal built into the chip" and a capacitive input capacitor;

Figure 3b shows a Nyquist diagram representing the input impedance in Figure 3a;

Figure 4a shows an equivalent circuit diagram of an input impedance of a device under test, the input impedance comprising an illustrative specific resistance and inductance value, a resistive built-in terminal and a gate of the wafer, and an ESD (electrostatic Discharge) capacitor

Figure 4b shows a Nyquist diagram illustrating the input impedance in Figure 4a;

Figure 5 illustratively shows a TDR (Time Domain Reflected) map of the input impedance of a GDDR5 memory;

Figure 6 is a cross-sectional view showing a circuit spring pin according to a comparative embodiment;

Figure 7a is a plan view showing the inner member of the spring pin of another comparative embodiment and a spring for separating the inner member and the outer sleeve from each other in a released state;

Figure 7b is a plan view showing one of the devices in a compressed state in Figure 7a;

Figure 8 is a plan view showing an outer sleeve of the spring pin shown in Figures 7a and 7b;

Figure 9 is a time-domain reflectance (TDR) diagram of an input pin of a shorted test element (DUT) through a spring pin of Figures 7a through 8;

Figure 10 shows a histogram illustrating the repeatability of a spring pin measurement using the spring pins shown in Figures 7a through 8;

Figure 11 shows a TDR map measured by a comparative test configuration device for measuring a DUT.

Figure 12 is a diagram showing an eye pattern of a signal received at a TDR receiver in a test configuration device for measuring an impedance mismatched test component;

Figure 13a shows a schematic cross-sectional view of an SMA (sub-miniature-A) adapter cable terminated by an ODT load simulation;

Figure 13b shows an equivalent circuit diagram of the SMA adapter cable terminated by the end terminal (ODT) loaded terminal of the wafer as shown in Fig. 13a;

Figure 14 shows a pole diagram of an input impedance of the SMA adapter cable with the ODT load terminal as the terminal as shown in Figure 13a;

Figure 15 shows a TDR diagram measured by a daisy-chain test configuration device without component loading;

Figure 16 shows a TDR diagram measured using a daisy chain test configuration device that has loaded DDR2 components at all locations;

Figure 17 shows a circuit diagram for connecting a test pin to a branch on two elements under test, the branch comprising a common line and two lines connected by a branch node;

Figure 18 is a circuit diagram of the branch as shown in Figure 17, wherein the impedance of the branch lines and the input impedance of the DUTs are specific values;

Figure 19 shows a conventional branch circuit diagram as shown in Figure 17, which indicates the reflection that occurs;

Figure 20a shows a circuit diagram of a daisy chain test configuration device for measuring a DUT in a shared test channel;

Figure 20b shows a TDR diagram obtained by measuring using the test configuration device shown in Figure 20a;

Figure 21a shows a step response timing diagram of a test signal applied to a daisy chain configuration device;

Figure 21b shows an eye diagram of the test signal as shown in Figure 21a;

Figure 22a shows a wave diagram of light transmitted through an optical medium as shown in Figure 2a when the optical medium comprises an optical film made of an anti-reflective coating material;

Figure 22b shows a signal diagram similar to Figure 22a. According to an embodiment of the invention, the signal diagram is an electrical transmission line of Figure 2b and has an anti-reflection circuit coupled between the transmission line and the impedance of the terminal. (impedance matching circuit);

Figure 23a shows a schematic diagram of a test configuration device in accordance with an embodiment of the present invention;

Figure 23b shows a schematic diagram of a test configuration device in accordance with another embodiment of the present invention;

Figure 23c shows an equivalent circuit diagram of a test configuration device in accordance with an embodiment of the present invention;

Figure 23d is a schematic diagram showing a test configuration apparatus including a device tester, a test interface, and a plurality of interfaces for a plurality of devices under test, in accordance with an embodiment of the present invention;

Figure 23e shows a theoretical Nyquist diagram illustrating the input impedance of the test configuration device as shown in Figure 23a;

Figure 24a shows an equivalent circuit diagram of a test configuration device corresponding to an illustrative example of a GDDR5 memory device shown in Figure 4a, having an embodiment of the present invention coupled to the transmission line and the device under test. Impedance matching circuit between;

Figure 24b shows a theoretical Nyquist diagram of the test configuration device as shown in Figure 24a;

Figure 25 shows a theoretical TDR map measured using the test configuration device as shown in Figure 24a;

Figure 26 shows the step response timing of the voltage at the device under test as measured by the test configuration device as shown in Figure 24a compared to the voltage at the input impedance of the device under test generated in Figure 4a. Figure

Figure 27 is a schematic cross-sectional view showing a spring pin according to an embodiment of the present invention;

Figure 28 is a schematic cross-sectional view showing a spring pin according to another embodiment of the present invention;

Figure 29a shows a space view of a spring pin in accordance with an embodiment of the present invention;

Figure 29b shows a space view of a spring pin in accordance with another embodiment of the present invention;

Figure 29c is a top plan view of a test configuration device in accordance with an embodiment of the present invention;

Figure 30 is a diagram showing an equivalent circuit diagram of a test configuration apparatus according to an embodiment of the present invention, the test configuration apparatus comprising an impedance matching circuit, a TDR transmitter and a TDR receiver;

Figure 31 shows a TDR diagram measured using the test configuration device as shown in Figure 30;

32 is an equivalent circuit diagram of a test configuration apparatus according to an embodiment of the present invention, the test configuration apparatus includes an impedance matching circuit, a TDR transmitter, a microstrip line and a measurement probe;

Figure 33 shows an eye diagram of a signal received by the TDR receiver of the test configuration device as shown in Figure 32;

Figure 34a shows a schematic cross-sectional view of a test configuration apparatus including an SMA adapter cable emulating with an ODT load and a series of impedance matching circuits, in accordance with an embodiment of the present invention. As a terminal;

Figure 34b shows an equivalent circuit diagram of the test configuration device as shown in Figure 34a;

Figure 35 shows a Smith chart of a reflection coefficient measurement of the test configuration device as shown in Figure 34a;

Figure 36 is a diagram showing an equivalent circuit diagram of a test configuration device according to an embodiment of the present invention, the test configuration device comprising two impedance matching circuits, each impedance matching circuit and a device under test, a length mismatch a Y-branch cable, a TDR transmitter, and a measurement probe are associated;

Figure 37 shows a signal diagram measured using the test configuration device as shown in Figure 36;

Figure 38 is a diagram showing an equivalent circuit diagram of a test configuration apparatus according to an embodiment of the present invention, the test configuration apparatus comprising two impedance matching circuits, each impedance matching circuit and a device under test, a length mismatch Y-branch cable, a test signal transmitter and a test signal receiver are associated;

Figure 39 shows an eye diagram measured using the test configuration device as shown in Figure 38;

Figure 40 is a circuit diagram showing a test configuration device including the branch as shown in Figure 17 and connected to respective output lines and respective components of the device under test, in accordance with an embodiment of the present invention An impedance matching circuit between impedances;

Figure 41 is a diagram showing an equivalent circuit diagram of a test configuration apparatus comprising two components to be tested, in accordance with an embodiment of the present invention;

Figure 42 shows a simulated eye diagram of a first input signal of the simulation of the test configuration device as shown in Figure 41;

Figure 43 is a diagram showing an equivalent circuit diagram of a test configuration device comprising four components under test in accordance with an embodiment of the present invention;

Figure 44 is a signal diagram showing a simulated four input signals of a test configuration device as shown in Figure 43;

Figure 45 shows an eye diagram of the simulated first input signal of the test configuration device as shown in Figure 44;

Figure 46 shows a schematic diagram of a test configuration device including an impedance matching circuit coupled to a first device under test via a first transmission line and coupled to a second transmission line a second device under test, the first transmission line having a length smaller than a quarter wavelength of a carrier of the test signal and the second transmission line having a length greater than a quarter wavelength of the carrier of the test signal;

Figure 47 is a timing chart showing the signals measured at the first device under test and measured by the second device under test as shown in Fig. 46.

400. . . Test configuration device

401. . . interface

402. . . Impedance matching circuit

403. . . Spring pin

403b. . . Schematic representation of a spring pin

404. . . Measured component

405. . . Signal generator

Claims (28)

A test configuration device comprising: an interface for a device under test, the interface comprising an impedance matching circuit, the impedance matching circuit comprising a resistor (R) and an inductor (L) connected in parallel, wherein the interface comprises a A spring pin that forms the impedance matching circuit. The test configuration device of claim 1, wherein the resistance (R) and the inductance (L) of the impedance matching circuit are formed by discrete electrical components. The test configuration device of claim 1, further comprising a signal generator for applying a test signal having an intermediate frequency lower than a maximum frequency to the interface, wherein the impedance matching circuit is configured to An electrical distance between the device under test and the impedance matching circuit is less than a quarter of an electrical wavelength corresponding to the highest frequency. The application of the testing apparatus arranged in item 1 of the scope of the patent, which further comprises receiving the test element, the test element comprises a receiving input impedance (Z _in), which is adapted to interface with the input impedance of the impedance matching circuit ( An electrical coupling is provided between Z _in ) such that one impedance of the impedance matching circuit (Z _ARC ) matches the input impedance (Z _in ). The test configuration device of claim 4, wherein the input impedance comprises a resistor (R) and a capacitor (C) connected in parallel, wherein the resistor (R) of the impedance matching circuit is equal to the input impedance ( The resistance (R) of Z _in ) is within a tolerance of +/- 10%, and wherein the inductance (L) of the impedance matching circuit is equal to the square of the resistance (R) of the input impedance (Z _in ) multiplying the input impedance (Z _in) the capacitance (C), within the error tolerance of +/- 10%. The test configuration device of claim 1, further comprising: a second interface for a second device under test, the second interface comprising an impedance matching circuit, the impedance matching circuit comprising a parallel a resistor (R) and an inductor (L), the resistor (R) and the inductor (L) being equal to the resistor (R) and the inductor (L) for the interface of the device under test; for component testing a test interface formed by an input line, a first output line, and a second output line, the input line being electrically connected between the test interface and a branch node, the first output line Electrically connected between the branch node and the interface for the device under test, the second output line is electrically connected between the branch node and the second interface for the second device under test. The test configuration device of claim 6, wherein the input line, the first output line, and the second output line comprise a transmission line, a waveguide, a microstrip line, a strip conductor of a printed circuit board, and a via hole. , connection (micro) strap, high frequency microwave cable, connectors, interconnects or components, SMA adapters or coaxial cables. The test configuration device of claim 6, wherein the first and second output lines are deviated from a symmetrical condition such that an impedance of the first output line deviates from an impedance of the second output line by more than 5% or the impedance of the impedance of the first output line and the impedance of the second output line The impedance of the junction deviates from the impedance of the input line by more than 5%. The test configuration device of claim 6, wherein the lengths of the first and second output lines deviate by more than 1%. The test configuration device of claim 6, wherein the impedances of the devices under test deviate from each other by more than 1%. The test configuration device of claim 6, wherein the first output line is formed on another layer in the circuit board that is different from the second output line. A spring pin includes: a first sleeve of a conductive material; a second sleeve of a conductive material; a tube of a resistive material, the first sleeve, the second sleeve, and the tube along the tube a common shaft is slidably attached to each other, wherein the tube is disposed between the first and second sleeves; and a spring of electrically conductive material for separating the first and second sleeves Wherein the spring pin forms a parallel connection of an inductance formed primarily by the spring and a resistor formed primarily by the tube. The spring pin of claim 12, wherein the first and second sleeves have the same diameter with a tolerance of +/- 5%. The spring pin of claim 12, wherein the tube has a smaller diameter than the first and second sleeves such that the tube can be within the first and second sleeves slide. a spring pin according to claim 12, wherein the spring is Arranged in the first and second sleeves. The spring pin of claim 15 wherein the spring is disposed within the tube. a spring pin comprising: a first sleeve of a conductive material; a second sleeve of a conductive material; a tube of insulating material, the first sleeve, the second sleeve and the tube along the tube The common shafts are slidably attached to each other, wherein the tube is disposed between the first and second sleeves; a spring of electrically conductive material for separating the first and second sleeves; and An elastic member comprising a resistive material attached between the first and second sleeves along the common shaft, wherein the spring pin forms an electrical component formed primarily by the spring and a primary A parallel connection of the resistors formed by the elastic elements. The spring pin of claim 17, wherein the elastic member is attached to the arrangement of the first and second sleeves and the barrel. The spring pin of claim 17, wherein the spring is a helical spring and the resilient element is disposed within the helical spring. The spring pin of claim 17, wherein the elastic element is a resistive elastomer. The spring pin of claim 17, wherein the elastic member is coated with a coating of an insulating material to prevent a relationship between the inductance mainly formed by the spring and the resistance mainly formed by the elastic member. Short circuit. The spring pin of claim 17, wherein the elastic member comprises an elastomer body having a main longitudinal axis; and a wire of a conductive material embedded in the body of the elastomer to enable the elastomer A top surface to a bottom surface of the body extend along the main longitudinal axis, wherein the resilient element is attached between the first and second sleeves to align the main longitudinal axis with the common axis. A spring pin comprising: an elastomer body having a main longitudinal axis; and a line of electrically conductive material embedded in the body of the elastomer such that between a top surface and a bottom surface of the elastomer body Extending along the main longitudinal axis, wherein the spring pin forms a parallel connection of an inductor (L) and a resistor (R) both formed by the lines. The spring pin of claim 23, wherein the wires are embedded in the body such that the wires are electrically interrupted from each other within the body. The spring pin of claim 23, wherein the wire is a carbon wire or a gold wire. A spring pin as described in claim 23, wherein the body has a cylindrical shape and wherein the wires are embedded in a cylindrical core of the cylindrical body, wherein the diameter of the core determines the inductance ( The value of L). An array of spring pins, such as the spring pins of claim 23, having the bottom surface of the spring pins connected to a common electrode. A method for testing a device under test, comprising the steps of: connecting a device under test through an interface including an impedance matching circuit, the impedance matching circuit comprising a resistor (R) and an inductor (L) connected in parallel, Wherein the interface comprises a spring pin, the spring pin forming the impedance matching circuit.