TWI414151B - Low power boots belt inverter circuit - Google Patents

Abstract

The present invention relates to a low-power bootstrap type inverter circuit capable of effectively reducing static leakage current generated in operation. The circuit is provided to drive a load and comprises: a front-end voltage step-up/step-down circuit with a front-end input terminal, an inverter, a first PMOS transistor, a second PMOS transistor, a first capacitor, a first NMOS transistor, a second NMOS transistor, a second capacitor and a front-end output terminal; and a rear-end CMOS inverter driving circuit with a rear-end input terminal and a rear-end output terminal. The rear-end input terminal is connected to the front-end output terminal, and the rear-end output terminal is connected to the load. When the voltage value of a voltage signal transmitted from the front-end output terminal to the rear-end input terminal is smaller than 0 volt, one NMOS transistor of the rear-end CMOS inverter driving circuit is turned off to reduce a static leakage current.

Description

Low power bootstrap inverter circuit

The invention relates to a low-power boot-belt inverter circuit, in particular to a nano-scale process, which has an operating voltage lower than a threshold voltage, and is more effective under the premise of maintaining a certain driving capability. A low power bootstrap inverter circuit that reduces the static leakage current generated during operation.

In the literature, the bootstrap inverter circuit is often used in a finite voltage source environment, but in a circuit design that drives a large load, such as an output stage used to drive large loads. Therefore, the bootstrap inverter circuit has been widely used in very large integrated circuits.

Moreover, at today's global promotion of environmental protection and green energy technology, low-power circuit design has become one of the main research directions of semiconductor industry and technology today, to reduce the energy consumption of electronic products (such as notebook computers). In general, reducing the operating voltage of a circuit is the most straightforward and effective way to achieve low power consumption. However, once the circuit is operating at an ultra-low operating voltage below a threshold voltage, the current drive capability of each of the transistors of the circuit will be significantly reduced, rendering the circuit inoperable at a reasonable speed. To this end, the industry needs to design a circuit occupying a larger area to overcome this drawback. But unfortunately, in a circuit manufactured by a nano-scale process, the problem of static leakage current is getting worse, and even the normal operation of the image to the circuit makes the original intention of low-power design that originally reduces power consumption greatly reduced.

Referring to FIG. 1a and FIG. 1b, FIG. 1a is a schematic diagram of a first operational principle of a conventional bootstrap inverter circuit, and FIG. 1b is a schematic diagram of a second operational principle of a conventional bootstrap inverter circuit. As shown in FIG. 1a, the conventional bootstrap inverter circuit 1 is used to drive a load circuit 12, and when the input voltage signal is switched from a low potential state (0) to a high potential state (V _DD ), A transistor 111, a third transistor 113, and a fifth transistor 115 are in a closed state, and the second transistor 112, the fourth transistor 114, and the sixth transistor 116 are in an on state. Further, the eighth transistor 118 is in a closed state because the sixth transistor 116 is in an on state. Since the first capacitor 13 has stored a voltage difference V _DD therein, the voltage of the first node 1a is reduced from 0 to -V _DD , and the source gate voltage difference of the seventh transistor 117 is 2 times V _DD . Strong conduction state. At this time, due to the leakage phenomenon of the transistor itself, especially in the transistor made by nano-advanced process, the static leakage current is more serious. Therefore, the transistor 118 is generated even if the gate voltage is zero, there is still a static leakage current 15.

As shown in FIG. 1b, when the input voltage signal is switched from a high potential state (V _DD ) to a low potential state (0), the first transistor 111, the third transistor 113, and the fifth transistor 115 are turned on. In the state, the second transistor 112, the fourth transistor 114, and the sixth transistor 116 are in a closed state. Further, the seventh transistor 117 is in a closed state because the first transistor 111 is in an on state. Since the second capacitor 14 has stored a voltage difference V _DD therein, the voltage of the second node 1b is raised from V _DD to 2V _DD , and the voltage difference of the eighth transistor gate source is 2 times V _DD 118 is strong. On state. At this time, also because the transistor is not fabricated by an absolutely ideal process, the static leakage current 15 of the seventh transistor 117 described above is also generated.

Moreover, under the current nano-scale process technology, the magnitude of the aforementioned static leakage current has increased significantly, especially under low-voltage operation, the magnitude of the static leakage current is quite close to the order of magnitude of the operating current of the circuit, and the static leakage current problem is highlighted. The severity of a circuit made from a nanoscale process.

The conventional bootstrap inverter circuit only considers driving a large load circuit with increased driving force and is designed for the leakage element. Today, nanoscale process production has become very popular, and the aforementioned static leakage current will have a more obvious impact on the normal operation of the circuit. For this reason, the conventional bootstrap inverter circuit does have the need for further improvement.

Therefore, the industry needs a process that can be manufactured in a nano-scale process and has a wide range of operating voltage capabilities (even operating voltages below a threshold voltage), and can effectively reduce operating time while maintaining a certain driving capability. A low power bootstrap inverter circuit with static leakage current.

The main object of the present invention is to provide a low power bootstrap inverter circuit that can be fabricated using a nanoscale process and has an operating voltage that is less than a threshold voltage.

A secondary object of the present invention is to provide a low power bootstrap inverter circuit that can effectively reduce the static leakage current generated during operation while maintaining a certain driving capability.

In order to achieve the above object, a low-power bootstrap inverter circuit is provided with a bias power supply for driving a load, comprising: a front-end step-up and step-down circuit, comprising a front end input end, an inverter, a first PMOS transistor, a second PMOS transistor, a first capacitor, a first NMOS transistor, a second NMOS transistor, a second capacitor, and a front end output; and a back end CMOS inversion The driver circuit includes a back end input and a back end output, the back end input is connected to the front end output, and the back end output is connected to the load to drive the load. In the front-end buck-boost circuit, the front-end input terminal is configured to input an input voltage signal to the front-end buck-boost circuit, the inverter has an input node and an output node, and the input node is connected thereto. a front end input end; the source of the first PMOS transistor is connected to the bias power supply, and the gate and the source of the second PMOS transistor are respectively connected to the output node of the inverter and the first PMOS transistor a drain, the two ends of the first capacitor are respectively connected to the front end input end and the drain of the first PMOS transistor; the source of the first NMOS transistor is grounded, the gate of the second NMOS transistor and The source is connected to the output node of the inverter and the drain of the first NMOS transistor, and the two ends of the second capacitor are respectively connected to the front end input terminal and the drain of the first NMOS transistor; The output terminal is connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor.

Therefore, in the low power bootstrap inverter circuit of the present invention, the front end buck-boost circuit and its rear CMOS inverter drive circuit are connected by only a single path (ie, one at the front end output and the rear). The wire between the input terminals, so when the voltage of the voltage signal transmitted from the front-end output to the rear-end input is boosted to less than 0 volts (such as -V _DD ), the back-end CMOS inverter is driven. The source gate voltage difference (V _SG ) of a PMOS transistor of the circuit is 2 times V _DD , which makes the PMOS transistor strongly conductive. At the same time, the NMOS transistor gate source voltage difference (V _GS ) of the back-end CMOS inverter driving circuit is -V _DD , so that the PMOS transistor is strongly turned off. On the other hand, if the voltage of the voltage signal transmitted from the front-end output to the back-end input is boosted to 2 times V _DD , the NMOS inverter gate has a source voltage difference (V _{GS )} ) is 2 times V _DD , making this NMOS transistor in a strong conduction state. At the same time, the source gate voltage difference (V _SG ) of the other PMOS transistor of the CMOS inverter driving circuit is -V _DD , so that the PMOS transistor is strongly turned off. Therefore, the low-power bootstrap inverter circuit of the present invention can effectively reduce the static leakage current generated during operation to a very low value (for example, pA) while maintaining a certain driving capability (the ability to push the load). grade). Moreover, since the low power bootstrap inverter circuit of the present invention can effectively reduce the static leakage current generated during operation, the low power bootband inverter circuit of the present invention can adopt a 90 nm class process (or The higher order process) is manufactured without the need to raise its operating voltage above a threshold voltage, so that the transistors of the low power bootstrap inverter circuit of the present invention can operate in a critical critical field. In this way, the power required for the operation of the low-power bootstrap inverter circuit of the present invention can be effectively reduced, and the power consumption caused by the extra static leakage current can be eliminated, which is in line with the recent efforts of the industry to reduce the energy consumption of electronic products. the trend of.

In the low-power bootstrap inverter circuit of the present invention, the circuit of the inverter in the front-end step-up and step-down circuit is not limited, and any circuit capable of achieving the inverting function can be applied to the front-end lifting piezoelectric of the present invention. In the inverter in the road. However, the inverter of the low power bootband inverter circuit of the present invention is preferably a CMOS inverter. In addition, the voltage of an input voltage signal input to the low power bootstrap inverter circuit of the present invention is not limited as long as the required components are provided. In this embodiment, the threshold voltage is about 0.25 volts due to the use of a 1 volt component, so it can operate between 0.15 volts and 1 volt.

Please refer to FIG. 2 , which is a schematic diagram of the circuit structure of the low power bootstrap inverter circuit 2 according to an embodiment of the present invention. As shown in FIG. 2, the low-power bootstrap inverter circuit 2 of the present invention is coupled with a bias power supply V _DD to drive a load (not shown), including: a front-end buck-boost circuit 21 and a The back end CMOS inverter drive circuit 22. The front-end buck-boost circuit 21 includes a front-end input terminal V _IN , an inverter 211 , a first PMOS transistor 212 , a second PMOS transistor 213 , a first capacitor 214 , and a first NMOS . The transistor 215, a second NMOS transistor 216, a second capacitor 217 and a front end output terminal 21c.

In addition, the back end CMOS inverter driving circuit 22 includes a back end input end 21d and a back end output end V _OUT , and the back end input end 21d is connected to the front end output end 21c, and the back end output end V _OUT is connected to A load (not shown) is used to drive this load. On the other hand, in the embodiment, the back end CMOS inverter driving circuit 22 is a conventional CMOS inverter driving circuit, and further includes a third PMOS transistor 221 and a third NMOS transistor 222. The rear end input terminal 21d is connected to the gate of the third PMOS transistor 221 and the gate of the third NMOS transistor 222, and the rear end output terminal V _OUT is opposite to the drain of the third PMOS transistor 221 and the third NMOS. The drain of the transistor 222 is connected.

Referring to FIG. 2, in the front end step-up and step-down circuit 21 of the low-power bootstrap inverter circuit 2 of the embodiment of the present invention, the front end input terminal V _IN is used to input an input voltage signal to the front end buck-boost voltage. Circuit 21, and in this embodiment, the voltage of the input voltage signal is between 0.15 volts and 1 volt. The inverter 211 has an input node 21a and an output node 21b, and the input node 21a is connected to the front end input terminal V _IN . In addition, the source of the first PMOS transistor 212 is connected to a bias power supply V _DD , and the gate and the source of the second PMOS transistor 213 are respectively connected to the output node 21b of the inverter 211 and the first PMOS battery. The cathode of the crystal 212 is connected, and the two ends of the first capacitor 214 are respectively connected to the front end input terminal V _IN and the drain of the first PMOS transistor 212.

On the other hand, the source of the first NMOS transistor 215 is grounded, and the gate and the source of the second NMOS transistor 216 are respectively connected to the output node 21b of the inverter 211 and the first NMOS transistor 215. The two ends of the second capacitor 217 are connected to the front end input terminal V _IN and the drain of the first NMOS transistor 215, respectively. Finally, the front end output terminal 21c is connected to the drain of the second PMOS transistor 213 and the drain of the second NMOS transistor 216.

As can be seen from FIG. 2, in the low power bootstrap inverter circuit 2 of an embodiment of the present invention, the front end buck-boost circuit 21 and the rear end CMOS inverter drive circuit 22 are only in a single path. Connected (ie, a wire between the front end output 21c and the rear end input 21d). Therefore, when the voltage of a voltage signal (not shown) transmitted from the front end output terminal 21c to the rear end input terminal 21d is boosted to less than 0 volts (e.g., -V _DD ), the embodiment of the present invention is low. The source gate voltage difference (V _SG ) of the third PMOS transistor 221 of the power spur inverter circuit of the power spur inverter circuit is 2 times V _DD , so the third PMOS transistor 221 is Strong conduction state. At the same time, the gate voltage difference (V _GS ) of the third NMOS transistor 222 is -V _DD , so the third NMOS transistor 222 is strongly turned off.

On the other hand, if the voltage of the voltage signal transmitted from the front end output terminal 21c to the rear end input terminal 21d is boosted to 2 times V _DD , the third NMOS transistor 222 gate source of the CMOS inverter driving circuit 22 is provided. The pole voltage difference (V _GS ) is 2 times V _DD , so the third NMOS transistor 222 is in a strong conducting state. At the same time, the source gate voltage difference (V _SG ) of the third PMOS transistor 221 is -V _DD , so the third PMOS transistor 221 is strongly turned off.

In this way, the low-power bootstrap inverter circuit of the present invention can effectively reduce the static leakage current generated during operation to a very low value (for example, pA) while maintaining a certain driving capability (the ability to push the load). Grade), or a value less than 1 nanoamperes (nA).

Hereinafter, the operation of each component in the low-power boot-type inverter circuit 2 according to an embodiment of the present invention will be described in detail with reference to the drawings, and the functions thereof can be achieved.

Please refer to FIG. 3 again, which is a schematic diagram of the operation of the low power bootstrap inverter circuit according to an embodiment of the present invention in a first operating state. Wherein, in the first operating state, the input voltage signal is switched from a high potential state (V _DD ) to a low potential state (0).

First, after the input voltage signal is switched from a high potential state (V _DD ) to a low potential state (0), the first PMOS transistor 212 is turned on, and the first NMOS transistor 215 is turned off. Since the first PMOS transistor 212 is turned on, the bias power supply (V _DD ) passes through the first PMOS transistor 212, and the first capacitor 214 is charged, so that the first capacitor 214 stores a V _DD voltage difference therebetween. And the potential of the source of the second NMOS transistor 216 is lowered to -V _DD .

Next, since the inverter 211 converts the input voltage signal from a low potential state (0) to a high potential state (V _DD ), the second PMOS transistor 213 is turned off, and the second NMOS transistor 216 is turned on. Thus, the potential of the drain of the second NMOS transistor 216 is transmitted to the front end output terminal 21c of the front end buck-boost circuit 21 such that its voltage is also -V _DD . That is to say, the voltage (-V _DD ) of the voltage signal of the front end output terminal 21c is a voltage equal to the voltage (V _DD ) of the negative one-time high potential state.

Then, the front end output terminal 21c transmits the voltage (-V _DD ) to the rear end input terminal 21d of the rear CMOS inverter driving circuit 22, so that the source gate voltage difference (V _SG ) of the third PMOS transistor 221 is obtained. It is 2 times V _DD , so the third PMOS transistor 221 is in a strong on state. At the same time, the gate voltage difference (V _GS ) of the third NMOS transistor 222 is -V _DD , so the third NMOS transistor 222 is strongly turned off. As such, the low power bootstrap inverter circuit of an embodiment of the present invention can effectively reduce the static leakage current generated during operation to a very low value while maintaining a certain driving capability (the ability to push the load). (eg pA rating), or a value less than 1 nanoamperes (nA).

Please refer to FIG. 4 again, which is a schematic diagram of the operation of the low power bootstrap inverter circuit according to an embodiment of the present invention in a second operating state. Wherein, in the second operating state, the input voltage signal is switched from a low potential state (0) to a high potential state (V _DD ).

First, after the input voltage signal is switched from a low potential state (0) to a high potential state (V _DD ), the first PMOS transistor 212 is turned off, and the first NMOS transistor 215 is turned on. The V _DD voltage difference stored in the first capacitor 214 causes the potential of the drain of the second PMOS transistor 213 to rise to 2V _DD .

Next, since the inverter 211 converts the input voltage signal from a high potential state (V _DD ) to a low potential state (0), the second PMOS transistor 213 is turned on, and the second NMOS transistor 216 is turned off. Thus, the potential of the drain of the second PMOS transistor 213 is transmitted to the front end output terminal 21c of the front end buck-boost circuit 21 so that its voltage is also 2V _DD . That is, the voltage (2V _DD ) of the voltage signal at the front end output terminal 21c is a voltage equal to the voltage (V _DD ) of the double high potential state.

Then, the front end output terminal 21c transmits the voltage (2V _DD ) to the rear end input terminal 21d of the rear CMOS inverter driving circuit 22, and the third NMOS transistor 222 has a gate source voltage difference (V _GS ) of 2 times. V _DD , so the third NMOS transistor 222 is in a strong conducting state. At the same time, the source gate voltage difference (V _SG ) of the third PMOS transistor 221 is -V _DD , so the third PMOS transistor 221 is strongly turned off. As such, the low power bootstrap inverter circuit of an embodiment of the present invention can effectively reduce the static leakage current generated during operation to a very low value while maintaining a certain driving capability (the ability to push the load). (eg pA rating), or a value less than 1 nanoamperes (nA).

In addition, since the first NMOS transistor 215 is turned on and the source of the first NMOS transistor 215 is grounded, the first NMOS transistor 215 discharges the second capacitor 217 to store a V _DD voltage. Worse than it.

As described above, in the first operational state (the input voltage signal is switched from a high potential state to a low potential state), the first PMOS transistor 212 charges the first capacitor 214, and in the second operational state ( The first NMOS transistor 215 discharges the second capacitor 217 when the input voltage signal is switched from a low potential state to a high potential state. Therefore, in the low power bootstrap inverter circuit of an embodiment of the present invention, The first PMOS transistor 212 and the first NMOS transistor 215 are charge and discharge transistors. In addition, in the first operational state or the second operational state, the voltage of the voltage signal received by the CMOS inverter driving circuit 22 of the low-power bootstrap inverter circuit according to an embodiment of the present invention (by the The back-end input terminal is determined according to the state (on or off) of the second PMOS transistor 213 and the second NMOS transistor 216 (2V _DD or -V _DD ), so the second PMOS transistor 213 and the second NMOS device Crystal 216 is a switching transistor.

Please refer to FIG. 5 , which shows a PMOS transistor and an NMOS transistor of a conventional bootstrap inverter circuit and a PMOS transistor and an NMOS transistor of a low power bootstrap inverter circuit according to an embodiment of the present invention. The static leakage current is a schematic diagram that changes as the magnitude of the push load increases. Wherein, ● indicates a static leakage current of an NMOS transistor of a low power bootstrap inverter circuit according to an embodiment of the present invention, and ■ indicates a PMOS power of a low power bootstrap inverter circuit according to an embodiment of the present invention. The static leakage current of the crystal, ○ is the static leakage current of the NMOS transistor of the conventional bootstrap inverter circuit, and □ represents the static leakage current of the PMOS transistor of the conventional bootstrap inverter circuit.

As can be seen from FIG. 5, regardless of the magnitude of the load used to drive (less than 1 pF or greater than 6 pF), the PMOS transistor and NMOS of the low power bootstrap inverter circuit of one embodiment of the present invention The values of the static leakage currents of the crystals are all on the pA level (less than 1 nA), that is, a value less than 1 nanoamperes (nA), which is significantly lower than the PMOS of the conventional bootstrap inverter circuit. The value of the static leakage current of the crystal and the NMOS transistor (both at the nA level).

Therefore, in the case of pushing the load of the same size, the low power bootstrap inverter circuit of one embodiment of the present invention has a significantly lower ability to reduce static leakage current than the conventional bootstrap inverter circuit, and is a span. Several orders of magnitude improvement.

In summary, in the low power bootstrap inverter circuit of the present invention, the front end buck-boost circuit and its rear CMOS inverter drive circuit are connected by only a single path (ie, a front-end output) The wire between the terminal and the rear input), so when the voltage of the voltage signal transmitted from the front-end output to the rear-end input is boosted to less than 0 volts (such as -V _DD ), the back-end CMOS is reversed. The source gate voltage difference (V _SG ) of a PMOS transistor of the phase driver circuit is twice V _DD , so that the PMOS transistor is in a strong conducting state. At the same time, the NMOS transistor gate source voltage difference (V _GS ) of the back-end CMOS inverter driving circuit is -V _DD , so that the PMOS transistor is strongly turned off. On the other hand, if the voltage of the voltage signal transmitted from the front-end output to the back-end input is boosted to 2 times V _DD , the NMOS inverter gate has a source voltage difference (V _{GS )} ) is 2 times V _DD , making this NMOS transistor in a strong conduction state. At the same time, the source gate voltage difference (V _SG ) of the other PMOS transistor of the CMOS inverter driving circuit is -V _DD , so that the PMOS transistor is strongly turned off. Therefore, the low-power bootstrap inverter circuit of the present invention can effectively reduce the static leakage current generated during operation to a very low value (for example, pA) while maintaining a certain driving capability (the ability to push the load). grade). Moreover, since the low power bootstrap inverter circuit of the present invention can effectively reduce the static leakage current generated during operation, the low power bootband inverter circuit of the present invention can adopt a 90 nm class process (or The higher order process) is manufactured without the need to raise its operating voltage above a threshold voltage, so that the transistors of the low power bootstrap inverter circuit of the present invention can operate in a critical critical field. In this way, the power required for the operation of the low-power bootstrap inverter circuit of the present invention can be effectively reduced, and the power consumption caused by the extra static leakage current can be eliminated, which is in line with the recent efforts of the industry to reduce the energy consumption of electronic products. the trend of.

The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

1. . . Conventional boots belt inverter circuit

111. . . First transistor

112. . . Second transistor

113. . . Third transistor

114. . . Fourth transistor

115. . . Fifth transistor

116. . . Sixth transistor

117. . . Seventh transistor

118. . . Eighth transistor

12. . . Load circuit

13. . . First capacitor

14. . . Second capacitor

15. . . Static leakage current

16. . . Reverse current

1a. . . First node

1b. . . Second node

2. . . Low power bootstrap inverter circuit

twenty one. . . Front end buck-boost circuit

twenty two. . . Back-end CMOS inverter drive circuit

211. . . inverter

212. . . First PMOS transistor

213. . . Second PMOS transistor

214. . . First capacitor

215. . . First NMOS transistor

216. . . Second NMOS transistor

217. . . Second capacitor

21a. . . Input node

21b. . . Output node

21c. . . Front end output

21d. . . Backend input

V _DD . . . Bias power supply

V _IN . . . Front end input

V _OUT . . . Backend output

221. . . Third PMOS transistor

222. . . Third NMOS transistor

FIG. 1a is a schematic diagram of a first operational principle of a conventional bootstrap inverter circuit.

FIG. 1b is a schematic diagram of a second operational principle of a conventional bootstrap inverter circuit.

2 is a schematic diagram showing the circuit structure of a low power bootstrap inverter circuit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of the operation of the low power bootstrap inverter circuit of the embodiment of the present invention in a first operating state.

4 is a schematic diagram of the operation of the low power bootstrap inverter circuit in a first operating state according to an embodiment of the invention.

5 is a static leakage current of a PMOS transistor and an NMOS transistor of a conventional bootstrap inverter circuit and a PMOS transistor and an NMOS transistor of a low power bootstrap inverter circuit according to an embodiment of the present invention. Schematic diagram of changes as the load size of the push increases.

2. . . Low power bootstrap inverter circuit

twenty one. . . Front end buck-boost circuit

twenty two. . . Back-end CMOS inverter drive circuit

211. . . inverter

212. . . First PMOS transistor

213. . . Second PMOS transistor

214. . . First capacitor

215. . . First NMOS transistor

216. . . Second NMOS transistor

217. . . Second capacitor

21a. . . Input node

21b. . . Output node

21c. . . Front end output

21d. . . Backend input

V _DD . . . Bias power supply

V _IN . . . Front end input

V _OUT . . . Backend output

221. . . Third PMOS transistor

222. . . Third NMOS transistor

Claims (9)

A low-power bootstrap inverter circuit is coupled with a bias power supply to drive a load, comprising: a front-end buck-boost circuit comprising a front-end input terminal, an inverter, a first PMOS transistor, a second PMOS transistor, a first capacitor, a first NMOS transistor, a second NMOS transistor, a second capacitor and a front end output terminal; and a back end CMOS inverter driving circuit, comprising a a back end input end and a back end output end, the back end input end being connected to the front end output end, the back end output end being connected to the load to push the load; wherein, in the front end buck-boost circuit, The front end input terminal is configured to input an input voltage signal to the front end buck-boost circuit, the inverter has an input node and an output node, and the input node is connected to the front end input end; the first PMOS electric a source of the crystal is connected to the bias power source, and a gate and a source of the second PMOS transistor are respectively connected to an output node of the inverter and a drain of the first PMOS transistor, the first capacitor Both ends are connected to the front end An input terminal and a drain of the first PMOS transistor; a source of the first NMOS transistor is grounded, and a gate and a source of the second NMOS transistor are respectively connected to an output node of the inverter and the a drain of the first NMOS transistor, the two ends of the second capacitor are respectively connected to the front end input end and the drain of the first NMOS transistor; the front end output end is opposite to the drain of the second PMOS transistor And connecting the drain of the second NMOS transistor. The low power bootstrap inverter circuit of claim 1, wherein the back end CMOS inverter driving circuit further comprises a third PMOS transistor and a third NMOS transistor, and thereafter The terminal input end is connected to the gate of the third PMOS transistor and the gate of the third NMOS transistor, and the back end output end is opposite to the drain of the third PMOS transistor and the third NMOS transistor Bungee connection. The low power bootstrap inverter circuit of claim 2, wherein the third NMOS is when a voltage of the voltage signal transmitted from the front end output to the rear input terminal is less than 0 volts. The transistor is turned off to reduce a static leakage current. The low power bootstrap inverter circuit of claim 3, wherein the static leakage current is less than 1 nanoamperes. The low power bootstrap inverter circuit according to claim 1, wherein when the input voltage signal is switched from a high potential state to a low potential state, the voltage of the voltage signal at the front end output terminal is Is a voltage equal to twice the voltage of the high potential state. The low power bootstrap inverter circuit of claim 5, wherein the first PMOS transistor system is coupled to the first PMOS transistor system after the input voltage signal is switched from a high potential state to a low potential state A capacitor is charged. The low power bootstrap inverter circuit according to claim 1, wherein when the input voltage signal is switched from a low potential state to a high potential state, the voltage of the voltage signal at the front end output terminal is Is a voltage equal to twice the voltage of the high potential state. The low power bootstrap inverter circuit of claim 7, wherein the first NMOS electro-crystalline system is coupled to the first NMOS electro-crystal system after the input voltage signal is switched from a low potential state to a high potential state Two capacitors are discharged. The low power bootstrap inverter circuit of claim 1, wherein the first PMOS transistor and the first NMOS transistor system are charge and discharge transistors, and the second PMOS transistor and the The second NMOS transistor is a switching transistor.