TWI411930B - System-level emulation/verification system and method thereof - Google Patents

Abstract

A system level emulation/verification system, including at least an operating device, for using a simulator to set soft intellectual properties (soft IPs) corresponding to a System-on-Chip (SOC) design module, and executing a simulation corresponding to the SOC design module; and for using a transactor to interact with the simulator via an Application Programming Interface (API); and a hard-wired based platform, including at least a hard IP which corresponds to a soft IP of the SOC design module, wherein the hard-wired based platform sets the hard IP according to a setting of the SOC design module, and outputs an operating result of the hard IP corresponding to the setting of the SOC design module; in addition, the hard-wired based platform executes an IP model proxy for receiving an output of the transactor and transmitting the output to the hard-wired platform for controlling the operation of the hard IP, and transmitting an operating result of the hard IP to the transactor executed by the operating device.

Description

System level simulation/verification system and method thereof

The present invention relates to an emulation/verification system for circuit design, and more particularly to simulation of overall circuit system design at a system-level before the entire system is tape-out. /Verified simulation verification system and its simulation/verification method.

With the rapid development of electronic technology, the proposed circuit system design tends to be complicated/large. Therefore, it is very important to quickly and early verify the correctness of the overall circuit and reduce its verification cost; in the past, circuit designers must first It takes a lot of time to design the hardware circuit of the circuit system, and after the hardware structure of the whole circuit is completed into a physical circuit, the whole circuit can be simulated and verified to confirm the correctness of the circuit system, and the writing system is used. Software on.

In order to speed up the development process, some verification/analog systems will perform simulation and verification before the circuit system completes the offline program and becomes a solid hardware circuit to reduce the cost of circuit design. For related technical content, refer to US Patent No. 4901259. The patent specification is not described here.)

However, these test platforms that can be used for simulation/verification before the circuit goes offline often require manual design, which means that different circuit systems need to be separately proposed. A large number of labor costs and circuit design time increase due to the corresponding test platform.

Even if the subsequent development of the simulation/verification platform does not require manual design, these analog/verification platforms not only use a large number of Field Programmable Gate Arrays (FPGAs), but also increase the simulation cost, and these FPGAs are harder to be physically solid. The actual operating frequency of the body circuit system operates. In other words, because the operating speed of the FPGA is much lower than the actual operating speed of the physical circuit after the offline program, or called the silicon-level speed, this leads to the inconsistency between the verification system result and the physical circuit system. .

In addition, existing analog/verification platforms may need to provide individual Printed Circuit Boards (PCBs) or Evaluation Boards (EVBs) to simulate/verify different circuit designs, which adds additional circuit cost. And the time required. In addition, in the past, a large number of FPGA analog/verification systems required repeated simulations at different operating frequencies to extend the time required for testing, not to mention the FPGAs in today's analog/verification platforms. The circuit details are not exactly the same as the physical circuit/silicon sample generated via the offline program.

Therefore, there is an urgent need to develop novel analog/verification methods and their associated analog/verification devices to improve circuit design accuracy, reduce production costs, and shorten development time for hardware and software.

According to a first embodiment of the present invention, a system-level emulation/verification system is disclosed. The system level simulation/verification system includes: an arithmetic device, a hard-wired based platform, and a serial link. The computing device is configured to execute a plurality of software modules, the plurality of software modules including: a simulator and a transactor. The simulator is configured to set a software-based intellectual property (software-based IP) corresponding to a system-on-chip (SOC) design module and execute a single chip corresponding to the system. One of the design modules simulates operation. The converter interacts with the simulator via an Application Programming Interface. The hardware circuit test platform includes: at least one hardware-based IP, which corresponds to a software package in the single-chip design module of the system, wherein the hardware The line test platform sets the hardware based on a setting corresponding to one of the system single chip design modules, and outputs the hardware operation corresponding to one of the settings, and the hardware circuit test platform Executing an IP model proxy to receive an output of the converter from a message channel and transmit it to the hardware line test platform to control the hardware矽智财, and the result of the operation of the hardware 传送智财 is transmitted to the converter executed by the computing device via the message channel. The connection circuit is coupled to the computing device and the hardware circuit test platform for providing the message channel contacting the computing device and the hardware circuit test platform.

According to another embodiment of the present invention, a system level simulation/verification method is disclosed The method includes: setting a software corresponding to a system single-chip design module in an emulator, and performing an analog operation corresponding to the single-chip design module of the system through the simulator; using a converter to Interacting with the simulator through an application interface; using a hardware circuit test platform including at least one hardware, to set the hardware according to a setting corresponding to one of the single chip design modules of the system Zhicai, and outputting the hardware 对应智财 corresponds to the operation result of one of the settings, wherein the hardware 对应智财 corresponds to a software 单 财 财 in the system single chip design module; and receives from a message channel The output of the converter is transmitted to the hardware circuit test platform to operate the hardware, and the operation result of the hardware is transmitted to the converter via the message channel.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

Please refer to FIG. 1. FIG. 1 is a schematic diagram showing a first embodiment of a system level simulation/verification system of the present invention. As shown in FIG. 1, system simulation/verification system 100 includes, but is not limited to, an computing device 110, a hardware circuit test platform 120, and a connection line 130. The computing device 110 includes at least an emulator 140, an application interface 150, and a converter 160. The simulator 150 is for performing a simulation operation of a system single chip design module, and the computing device 110 uses the converter 160 to interact with the simulator 140 through the application interface 150. In this embodiment, the hardware circuit test platform 120 includes a plurality of hardware components. For example, the hardware circuit test platform 120 may include at least one hardware, and the hardware circuit test platform 110 is based on The system single chip design module is configured to set the hardware and the operation result corresponding to the setting of the system single chip design module is transmitted to the computing device 110 via the connection line 130. Simulator 140 inside. Please note that Figure 1 shows only a single hardware 170智财 170 for illustrative purposes. In fact, the hardware circuit test platform 120 may also include a plurality of hardware hackers, in other words, hardware circuit testing. The number of hardware in the platform 120 can be based on design considerations. Here, the system single chip design module can be a system single chip design using a programming language architecture (that is, it has not been downlined to become a physical hardware circuit system), and the computing device 110 is simulated by The device 140 simulates/verifies this system single chip design module.

The hardware circuit test platform 120 receives the output of the converter 160 through a message channel provided by the connection line 130 through a smart agent server module 180, and controls the hardware based on the output of the converter 160. Operation and hardware line test The platform 120 further transmits the operation result of the hardware entity 170 to the converter 160 from the connection line 130 via the 矽智财代理服务模块 180. In an embodiment of the present invention, the emulator 140, the application interface 150, and the converter 160 can be implemented using a software module; for example, the emulator 140 can be converted and converted by using an application program interface 150 implemented by a software program. The device 160 interacts, and the converter 160 supports the circuitry for processing the transaction level architecture. Therefore, the adapter 160 is used to translate the information of the simulator 140 via the message channel (which is connected by Line 130 is implemented to communicate with the hardware line test platform 120. For the hardware circuit test platform 120, the Wisdom proxy server module 180 serves as an interface between the hardware circuit test platform 110 and the computing device 110, and receives the translated information via the converter 160 through the message channel. And interpreting the message transmitted by the translator 160 for the hardware line test platform 120 to call and setting the hardware and wisdom assets corresponding to the system single chip design module (such as the software 矽智财) (such as hardware 智智财170 The hardware circuit test platform 120 sets the hardware (such as hardware and wisdom) on the hardware circuit test platform 120 according to the setting of the system single chip design module in the simulator 140. It is operated according to the corresponding software and smart money setting in the system single chip design module in the simulator 140, and controls the hardware to make its output correspond to the system single chip design module. The operation result of the setting of the software and the smart money is translated by the intelligent agent server 180 and the converter 160 of the computing device 110 to further transfer the operation result of the hardware to the simulator 140. , Note that the operation result of the hardware 矽智财 170 referred to here corresponds to the setting of the software 矽智财in in the system single chip design module; in other words, the setting of the hardware 矽智财 170 on the hardware circuit test platform 120 Is the same as its corresponding system single chip set The setting of a software 矽智财 in the meter module.

In an embodiment of the present invention, the computing device 110 can be a personal computer or a workstation, and the hardware device 170 corresponds to a software package in the system single chip design module executed in the simulator 140; And the present invention can use a physical connection line 130 as a message channel between the computing device 110 and the hardware line test platform. The system level simulation/verification system of the present invention comprises an arithmetic device 110 and an emulator 140 therein, an application interface 150, a converter 160, and a hardware circuit test platform 120 and a system corresponding thereto for verification The hardware of the single-chip design module, such as the hardware of the intellectual property (such as hardware and intellectual property 170), uses the hardware circuit before the complete system single-chip design module performs the offline program and becomes the physical circuit system. The test platform 120 corresponds to at least one software 矽智财 170 of the software single chip design module, to transfer the operation result of the partial physical circuit (that is, the hardware 矽智财 170) back to the simulation. The device 140 is used for system level simulation/validation. However, the foregoing description is for illustrative purposes only and is not a limitation of the present invention. For example, the computing device 110 and the hardware circuit test platform 120 may further include more soft/hardware modules, and the first figure is for For the sake of brevity, only the components related to the embodiments are shown, and in different embodiments, the Wisdom proxy server module 180 can selectively use the software module/hardware module or the software module and The combination of hardware modules is implemented to interact with the simulator 140 in the computing device 110 via the converter 160 via the physical connection line 130. In addition, the hardware circuit test platform 120 can also use a control circuit (not shown) to manage/control the hardware on the hardware test platform 120 through the smart agent server module 180 (eg, Hardware 矽智财170). However, the foregoing description is for illustrative purposes only. Any use of the computing device 110 to execute the simulator 140 to perform a simulation of a circuit module system (such as a system single chip design module) in a programming language architecture, so that the overall circuit module system is offline Before becoming a physical hardware circuit, by using a part of the physical hardware circuit module corresponding to the circuit module system (such as hardware 170智财 170) to simulate the speed of the physical circuit operation (such as a wafer level speed) and The result is passed back to the simulator 140 in the computing device 110 for performing system-level simulation verification through the simulator 140 and effectively accelerating the development of the system-level simulation/verification system for the software system used on the circuit module system. All comply with the spirit of the invention and are within the scope of protection of the invention.

For example, through appropriate design changes, the computing device can be executed by using the converter 160 with the different structural system level simulation/verification system through the computing device 110 end and the hardware circuit testing platform 120 end. System level simulation/verification of a system single-chip design circuit (such as the aforementioned system single-chip design module) of the program language architecture in the simulator 140 in the 110, and using at least one hardware of the hardware circuit test platform 120 170 to perform the simulation operation of the corresponding software package in the system single-chip design (such as the above-mentioned system single-chip design module) to improve the correctness of the system level simulation/verification and reduce the verification cost; these related design changes are It is within the scope of protection of the present invention.

In addition, in an embodiment of the present invention, the system level simulation/verification system 100 can comply with the standard Co-Emulation Modeling Interface (SCE-MI) specification, and the application interface 150 can be one. Corresponding to the front The software of the Advanced Microcontroller Bus Architecture-Advanced High-Performance Bus (AMBAAHB bus). In addition, since the principles of the converter 160 and the hierarchical design of the processing program are known to those skilled in the art of the Electrical System Level system, they will not be described again for the sake of brevity.

Referring to FIG. 2, FIG. 2 is a flow chart showing the steps of an embodiment of the system level simulation/verification method applied to the system level simulation/verification system 100 shown in FIG. Please note that if the same result can be achieved substantially, it is not necessary to follow the sequence of steps in the process shown in Figure 2, and other steps may be inserted. The flow of the system level simulation/verification method includes the following steps: Step 202: The computing device 110 sets a software entity corresponding to a system single chip design module in the simulator 140, and executes the corresponding function through the simulator 140. The simulation operation of the system single chip design module, wherein the simulator 140 can be implemented by using a software program or a software platform in the computing device 110, and the system single chip design module is a system single chip design in a programming language architecture ( SOC design), and the computing device 110 is configured to execute (in a programming language) the software included in the system single-chip design circuit and other components (in the programming language) to execute the system through the simulator 140. Simulation/verification operation of a single-chip design circuit. In an embodiment of the invention, the converter 140 can be a soft phantom executed by the computing device 110. The group is used to translate the output of the simulator 140 to convert it into a message compatible with the smart agent module 180 in a hardware line test platform 120. In addition, in an embodiment of the present invention, the computing device 110 executes a test program (test bench) through the simulator 140 to perform a simulation operation of the system single chip design module, and executes the system list under the simulator 140. Before the simulation operation of the chip design module, the simulator 140 first instantiates the software corresponding to the system single chip design module to set the software corresponding to the system single chip design module; The setting of the single-chip design module includes at least the setting of (one or more) software entities within the system single-chip design module. The hardware circuit test platform 120 is based on the software 相对智财 corresponding to the software 矽智财财 170 software 矽 财 财 来 设定 设定 设定 设定 设定 设定 设定 设定 设定 设定 设定 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 It is consistent with the setting of the hardware and wisdom.

Step 204: The computing device 110 uses a converter 160 to interact with the simulator 140 through an application interface 150. In one embodiment, the application interface 150 can be a software program corresponding to a high-performance bus of the look-ahead microprocessor bus architecture.

Step 206: Use a hardware circuit test platform 120 having at least one hardware 170 智 170 to set according to one of the system single chip design modules. The hard hardware 170智财 170, and the output hardware 矽智财 170 corresponds to the operation result of the setting of the system single chip design module, wherein the hardware 170智财 170 series corresponds to the system single chip design module Software and wisdom. Please note that the number of hardware 170 财 170 is not one of the limitations of the present invention. With appropriate design changes, the system single-chip design module that performs the simulation operation through the simulator 140 has a plurality of software wise. And the hardware circuit test platform 120 has a plurality of hardware and intellectual assets corresponding to a plurality of software software and other software modules, and may also be designed according to the system single chip design. The settings in the group are respectively set to correspond to a plurality of hardware and hardware assets on the hardware circuit test platform 120, so as to use the physical hardware and the smart chip to perform the system single-chip design mode at a physical wafer level speed. The set of simulations is grouped and the results are passed back to the simulator 140 within the computing device 110 for subsequent simulation of the system level. More broadly, the system level simulation verification system of the present invention can also be used to perform the corresponding software in the computing device 110 using the hardware and hardware architecture on the hardware circuit test platform 120. The simulation of the financial and software architectures to provide better system level simulation operations. In addition, the hardware and software finance system can respectively correspond to the software and software wealth of the system single chip design module, and the physical hardware architecture (such as a storage device) can correspond to the storage of the programming language in the simulator 140. Module. The aforementioned related design changes are all within the scope of protection of the present invention.

Step 208: Receive the output of the converter 160 from a message channel and transmit it to the hardware circuit test platform 120 to operate the hardware, and execute the operation result of the hardware. The channel is passed to converter 160. In the system level simulation/verification system 100 shown in FIG. 1, the physical connection channel 130 is used to implement the information channel between the computing device 110 and the hardware circuit test platform 120. However, in practice, any available The mechanism or architecture of the desired message channel can be used to implement the connection channel 130 of the present invention, and such related design variations are within the scope of the present invention.

In addition, in another embodiment of the present invention, the hardware circuit test platform 120 may have other hardware modules, such as a memory unit, and if the hardware circuit test platform 120 has multiple hardware components.矽智财 (not shown in the figure) and/or hardware modules correspond to a plurality of software 矽智财和软件模块s in the system single-chip design module of the programming language architecture, then the hardware circuit test platform 120 can be set according to the settings of the corresponding software, software and software modules in the system single chip design module to be simulated by the simulator 140 via the converter 160 and the smart agent server module 180. The hardware circuit test platform 120 corresponding to the hardware and hardware modules, and then the physical operating speed (such as wafer level speed) to operate these physical hardware and hardware modules, and The result of the operation is passed back to the simulator 140. The foregoing related design changes are in accordance with the spirit of the invention and are within the scope of the invention.

Please refer to FIG. 3, which shows implementation details of one embodiment of the computing device 110 of the system level simulation/verification system 100 of the present invention. As shown, the computing device 110 can be implemented using a personal computer or a workstation, and the simulator 140 can be a software platform thereon, and the system single chip design module 320 is designed to be a programming language, and the simulation is performed. The controller 140 can execute a test code 310 to perform system level simulation verification in accordance with the test code 310 before the system single chip design module 320 has not become a physical circuit system. Since the test code 310 and the system single-chip design module 320 in the programming language architecture are well known to those skilled in the art of circuit design, the computing device 110 and the simulator 140 related to the present invention have been The details of the system single-chip design module 320 can be easily understood after reading the above descriptions of the first and second figures, so that it is not here. Repeat it again.

Please refer to FIG. 1 , FIG. 2 and FIG. 4 together. FIG. 4 is a detailed implementation of another embodiment of the system level simulation/verification system of the present invention. As shown in the figure, the system performs the system level simulation operation of the system single chip design module 320 on the computing device 110 (through the simulator), and the system single chip design module 320 is a programming language architecture. The circuit system, for example, can be constructed using Verilog or other Hardware Description Language (HDL) to construct the system single chip design module 320, and then execute the simulation/verification of the system single chip design module 320 via the test code. Before performing the simulation/verification of the simulation system level, the computing device 110 calls and sets the software corresponding to the software in the system single chip design module 320 through the simulator (which can be implemented using a software) (for example) Software 矽 智 财 322, 324, 326), assuming that there is a hardware 175 in an integrated circuit 190 on the hardware circuit test platform 120, the hardware architecture of the hardware 175 corresponds to the hardware description of the hardware description language architecture. For example, the hardware circuit test platform 120 can receive the converter (not shown in the figure) on the computing device 110 through the connection line by using the intelligent server proxy module (not shown). The setting details of the software 326 transmitted by the software are transmitted to the integrated circuit 190 to set the hardware 175 (as shown) in the integrated circuit 190. In this way, when the simulator (not shown in the figure) is executed through the test code to the simulation/verification operation corresponding to the software 智智财 326, the hardware 智智财175 will be based on it and the software. 326 matches the settings to operate, and the operation result of the setting of the hardware 175 财 175 relative to the software 智 智 326 is transmitted back to the simulator via the connection line 130 (not shown in the figure), therefore, the present invention can Before the system single-chip design module 320 performs the offline process and becomes the physical circuit, the hard-wired test and the other hardware components corresponding to the system single-chip design module 320 on the hardware circuit test platform 120 are used as much as possible. The simulation verification is performed at the operating speed of the physical circuit and transmitted back to the simulator (not shown) to complete the system level simulation verification of the system single chip design module 320.

In another embodiment of the present invention, the test/verification test code of the system single-chip design module for executing the program language architecture of the present invention additionally describes the behavior of other hardware modules, for example, if The hardware circuit test platform of the present invention comprises a hard disk device, such as a universal serial bus (USB) hard disk, and the test code can describe the software in the system single chip design module. The behavior of the USB memory hard disk software module. Therefore, when the test code is executed to When the software is compared with the software module of the USB hard disk, the corresponding hardware and the corresponding USB hard disk will be operated by the real circuit. The speed corresponds to the operation of the system single chip design module and the test code setting, and the operation result is transmitted back to the simulator. Please note that any simulation verification system that conforms to the processor level, such as the system level simulation verification system that complies with the standard collaborative simulation modeling interface SCE-MI specification or other related specifications, is only required to use at least one hardware line platform. A hardware, hardware, and/or hardware module that provides operational results at physical circuit speeds (such as wafer level speeds) to assist in the overall system hierarchy (such as system single-chip design modules) before the offline system level Simulation/validation is in accordance with the spirit of the invention and is within the scope of protection of the invention.

By adopting the system level simulation/verification system of the present invention and its system level simulation/verification method, the number of field-programmable gate arrays can be reduced, and some software entities can be hard-wired on the hardware platform. To simulate and return the results of its operation, it provides more reliable system level simulation/verification and speeds up software development.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧System level simulation/verification system

110‧‧‧ arithmetic device

120‧‧‧ hardware line test platform

130‧‧‧Connected lines

140‧‧‧ Simulator

150‧‧‧Application interface

160‧‧‧ converter

170, 175‧‧‧ Hardware

180‧‧‧矽智财代理服务模块

190‧‧‧ integrated circuit

310‧‧‧ test code

320‧‧‧System Single Chip Design Module

322, 324, 326‧‧‧Software

Figure 1 is a schematic illustration of a first embodiment of a system level simulation/verification system of the present invention.

Figure 2 is a flow chart showing the steps of an embodiment of the system level simulation/verification method applied to the system level simulation/verification system shown in Figure 1 of the present invention.

Figure 3 is a diagram showing the implementation details of one embodiment of the arithmetic unit of the system level simulation/verification system of the present invention.

Figure 4 is a diagram showing implementation details of another embodiment of the system level simulation/verification system of the present invention.

100‧‧‧System level simulation/verification system

110‧‧‧ arithmetic device

120‧‧‧ hardware line test platform

130‧‧‧Connected lines

140‧‧‧ Simulator

150‧‧‧Application interface

160‧‧‧ converter

170‧‧‧ Hardware, wisdom and wealth

180‧‧‧矽智财代理服务模块

Claims (14)

A system level simulation/verification system includes: an arithmetic device for executing a plurality of software modules, the plurality of software modules comprising: an simulator for setting a single chip design mode corresponding to a system The software group and the simulation operation corresponding to one of the system single chip design modules; and a converter interacting with the simulator via an application interface; a hardware circuit test platform including : At least one hardware, the hardware and finance department corresponds to a software package in the single-chip design module of the system. The hardware circuit test platform is based on the single-chip design module corresponding to the system. A setting is used to set the hardware and the output of the hardware is corresponding to the operation result of the setting, and the hardware line test platform executes a smart agent server module to self-sense Receiving, by the channel, an output of the converter and transmitting the output to the hardware circuit test platform for controlling the hardware and transmitting the operation result of the hardware to the operation via the message channel The converter is executed by the computing device; and a connecting circuit is coupled to the computing device and the hardware circuit testing platform for providing the message channel contacting the computing device and the hardware circuit testing platform. The system-level simulation/verification system of claim 1, wherein the hardware circuit test platform operates the hardware at a wafer level speed, wherein the hardware system corresponds to the system The software in the chip design module is smart. The system level simulation/verification system of claim 1, wherein the computing device executes a test code through the simulator to perform the simulation operation of the system single chip design module; the simulator is Before executing the simulation operation corresponding to the single-chip design module of the system, calling each software corresponding to the single-chip design module of the system; and setting the system of the single-chip design module of the system includes software 矽The smart money is set so that the hardware line test platform sets the hardware and wisdom according to the setting of the software and intellectual property that should be used by the hardware. The system level simulation/verification system of claim 1, wherein the computing device interacts with the smart agent proxy module via the message channel through the converter, and the computing device executes the converter Translating the message of the simulator and transmitting the message to the hardware line test platform through the server. For example, the system level simulation/verification system described in claim 4, wherein the application interface corresponds to a high efficiency bus of a look-ahead microprocessor bus structure. The system level simulation/verification system of claim 1, wherein the system level simulation/verification system complies with a specification of a standard collaborative simulation modeling interface. For example, the system level simulation/verification system described in claim 1 is simulated/verified before the overall system goes offline. A system level simulation/verification method includes: setting a software entity corresponding to a system single chip design module in an simulator, and performing simulation operation corresponding to the single chip design module of the system through the simulator Using a converter to interact with the simulator via an application interface; using a hardware line test platform including at least one hardware, to configure one of the single chip design modules corresponding to the system To set the hardware and wisdom, and output the hardware and wisdom corresponding to the operation result of one of the settings, wherein the hardware and the financial system correspond to a software package in the system single chip design module; And receiving the output of the converter from a message channel and transmitting the same to the hardware circuit test platform to operate the hardware and transmitting the operation result of the hardware to the message channel To the converter. The system level simulation/verification method described in claim 8 of the patent application system performs the simulation operation of the single chip design module of the system at a wafer level speed. The system level simulation/verification method of claim 8, wherein the simulator is used to execute a simulation operation corresponding to the single-chip design module of the system, and the test program is executed by the simulator to execute the system. The simulation operation of the single-chip design module; the step of setting the software corresponding to the system single-chip design module in the simulator includes: calling before performing the simulation operation corresponding to the single-chip design module of the system Each software corresponding to the single-chip design module of the system, wherein the setting of the single-chip design module of the system includes a software configuration, so that the hardware circuit test platform is based on the corresponding hardware. The software of Zhi Zhicai is set up to set the hardware and wisdom. The system level simulation/verification method of claim 8, wherein the step of using the converter to interact with the simulator via the application interface comprises: translating the message of the simulator and passing the message The message channel is transmitted. The system level simulation/verification method of claim 11, wherein the application interface corresponds to a high efficiency bus of a look-ahead microprocessor bus architecture. The system level simulation/verification method of claim 8, wherein the system level simulation/verification system complies with a specification of a standard collaborative simulation modeling interface. The system level simulation/verification method described in claim 8 of the patent application is performed before the entire system is offline.