TWI410050B - A phase-locked loop with novel phase detection mechanism - Google Patents

Abstract

A phase-locked loop (PLL) with novel phase detection mechanism is provided, including a phase frequency detector (PFD), a controller, a digital-to-analog (D2A) module, and a voltage-controlled oscillator/current-controlled oscillator (VCO/ICO), wherein PFD has a reference signal input and an input from output signal of the VCO/ICO and is connected to the controller, the controller is then further connected to D2A module, D2A module converts the control signal from the controller into an analog voltage to control the frequency and phase of VCO/ICO. It is worth noting that the PFD of the present invention has a novel phase detection mechanism so that the phase detection does not rely on edge alignment. In addition, the novel phase detection mechanism also allows flexible reference signal input, as opposed to the aforementioned fixed external source, such as, a crystal.

Description

Phase-locked loop with improved phase detection mechanism

The invention relates to a phase-locked loop, in particular to a phase-locked loop with an improved phase detection mechanism.

Phase-locked loop (PLL) is a frequency control system that is typically used in a wide range of circuit designs, including clock generation, clock recovery, spread spectrum, removal skew, clock distribution, jitter, and noise reduction. , frequency synthesis, and more. The operation of the PLL is based on the phase difference between the input signal and the feedback of the voltage controlled oscillator (VCO). PLLs are widely used as clock generators in electronic devices and support high-speed transmission protocols, such as USB 2.0, as an important component for synchronizing data transmission. Figure 1 shows a schematic diagram of a conventional PLL. As shown in the first figure, the conventional PLL includes a phase frequency detector (PFD) 101, a loop filter 102, a VCO 103, and a divider 104. As shown in the first figure, the PFD 101 receives the reference signal 110 and the feedback signal 104a from the divider 104, and outputs a control signal 101a indicating whether the feedback signal is behind or ahead of the reference signal. Loop filter 102 converts control signal 101a into voltage signal 102a for use by VCO 103 and acts as a bias. The VCO 103 oscillates faster or slower depending on the voltage signal 102a to produce an output signal 103a. The output signal 103a is also fed to the divider 104 to become the feedback signal 104a prior to being fed into the PFD 101. In this way, the PLL can produce a stable output signal, which is why PLLs are widely used as clock generators among other applications. In the clock generator, the output signal 103a is a clock provided to the remaining circuits in the electronic device to further control and synchronize the operation of the electronic device.

However, in conventional PLLs, the reference signal 110 is typically from a fixed external source, such as a crystal that produces a clock, as shown in the first figure. The final output signal 103a is typically a signal having an external crystal resonant frequency. For example, for a PLL used in a USB 2.0 application, a 480 MHz clock rate can be generated by using a 12 MHz crystal as the source of the reference signal 110.

In general, a phase frequency detector commonly used in conventional PLL designs relies on the relative timing of the edge of the feedback signal and the reference signal, that is, the phase. At this time, when the two signals are of the same frequency, a fixed output proportional to the phase difference is generated. On the other hand, the phase detector based on the logic gate used in the PLL provides the advantage that the VCO can be quickly forced to synchronize to the reference signal even if the reference signal is essentially different from the initial output frequency of the VCO. The second figure shows a traditional phase detection mechanism based on edge alignment. This edge alignment can be imposed on certain applications, such as high speed applications.

Another limitation of conventional phase frequency detectors is the need for a fixed external source. This not only increases the cost of the electronic device, but also hinders the flexibility of the design. Therefore, it is advantageous to create an improved phase detection mechanism for flexible PLL design and reduced manufacturing cost.

The present invention has been used to overcome the shortcomings of the conventional PLL design described above. The main object of the present invention is to provide an improved phase detection mechanism that makes phase detection flexible and can be applied to high speed applications.

Another object of the present invention is to provide a PLL with an improved phase detection mechanism to provide an elastic reference signal and eliminate the need for separate reference signal sources to reduce manufacturing cost and complexity.

To achieve the above object, the present invention provides a PLL with improved phase detection mechanism, including a phase frequency detector (PFD), a controller, a digital to analog (D2A) module, and a voltage controlled oscillator/current controlled oscillator (VCO). /ICO), wherein the PFD has a reference signal input and an input signal from the VCO/ICO, and is connected to the controller, and then the controller is further connected to the D2A module, and the D2A module converts the control signal from the controller into Analog voltage to control the frequency and phase of the VCO/ICO. It is worth noting that the PFD of the present invention has an improved phase detection mechanism to make phase detection independent of edge alignment. In addition, the improved phase detection mechanism also provides a flexible reference signal input as a relative external source, such as a crystal.

The above and other objects, features, aspects and advantages of the present invention will become apparent from

The PLL of the present invention uses an improved phase detection mechanism. As noted above, conventional phase frequency detectors often use a fixed external source, such as a crystal, as a reference signal. The final output signal of the PLL is typically the resonance of the reference signal. For example, in USB 2.0, a 480 MHz clock rate can be obtained from a fixed external 12 MHz crystal as a reference clock source.

This improved phase detection mechanism does not require a fixed external source. Rather, according to the phase detection mechanism of the PLL of the present invention, the reference signal and the VCO output signal are analyzed before the control signal is generated to the controller. The final output signal is related to the reference signal, but not necessarily the resonance of the frequency of the reference signal. The following describes how to analyze the reference signal and the output signal in phase detection in accordance with the present invention.

The third figure shows a first exemplary waveform diagram for improving phase detection in accordance with the present invention. For the sake of simplicity, the waveforms used in the exemplary embodiment are regular periodic waveforms, i.e., a series of 1, 0, 1, 0, 1, 0, ..., etc. As shown in FIG. 3, the first waveform is labeled A, that is, the signal A, and the second waveform is the delayed signal Ad, that is, the waveform having the same delay as the signal A. The third waveform is shown as signal B1 having a higher frequency than half the frequency of signal A. For the sake of simplicity, signal A can be considered as the signal observed by observer signal B. As shown in Fig. 3, if both the signal A and the delayed signal Ad are sampled at the rising edge of the signal B1, different four sets of pairs can be observed, namely (1, 1), (1, 0), ( 0, 0) and (0, 1), wherein the first item in each set of pairs is the level of signal A, and the second item is the level of delayed signal Ad. In addition, (1,1)->(1,0),(1,0)->(0,0),(0,0)->(0,1),(0,1)- can be observed. > (1, 1) transformation. That is, when the observer frequency is higher than half of the observed frequency, any combination of the above four transitions can be observed, that is, (1,1)->(1,0), (1,0)- >(0,0),(0,0)->(0,1),(0,1)->(1,1). Similarly, the fourth waveform display signal B2 has a lower frequency than one half of the signal A. If both signal A and delayed signal Ad are sampled at the rising edge of the fourth waveform (ie, signal B2), then a different four sets of pairs can be observed, namely (1,1), (1,0), ( 0,0), (0,1), where the first item in each set of pairs is the level of signal A, and the second item is the level of delayed signal Ad. In addition, (1,1)->(0,1),(0,1)->(0,0),(0,0)->(1,0),(1,0)- can be observed. > (1, 1) transformation. That is, when the observer frequency is lower than half of the observed frequency, any combination of the above four transitions can be observed, that is, ((1,1)->(0,1), (0,1)- >(0,0),(0,0)->(1,0),(1,0)->(1,1). The observation by the exemplary waveform shows (1,1)->(1,0) ), the transition of (1,0)->(0,0),(0,0)->(0,1),(0,1)->(1,1) is implied, the frequency of the observer, For example, the signal B1 is faster than half of the observed frequency, such as the signal A, and (1,1)->(0,1),(0,1)->(0,0),(0,0) The transition of ->(1,0),(1,0)->(1,1) implies the frequency of the observer, such as signal B2, which is slower than half of the observed frequency, such as signal A.

The fourth figure shows a second exemplary waveform diagram for improving phase detection in accordance with the present invention. The exemplary waveform is an observation that is generalized to show the transition pattern of the third graph and can also extend to irregular or aperiodic observer waveforms, namely, signal B1 and signal B2. As shown in the fourth figure, the first waveform is the signal A, and the second waveform is the delayed signal Ad. The third waveform shows that the observer signal B1 has a higher frequency than one half of the signal A. If both the signal A and the delayed signal Ad are sampled at the rising edge of the observer signal B1, then (1, 0), (0, 0), (0, 1), (1, 1), (1, 0), a sequence of (0,0).... Once again, four different types of transitions can be observed at different locations in the series of observed numbers, ie (1,1)->(1,0),(1,0)->(0, 0), (0,0)->(0,1),(0,1)->(1,1). Similarly, the fourth waveform shows that the observer signal B2 has a lower frequency than one half of the signal A. If both the signal A and the delayed signal Ad are sampled at the rising edge of the fourth waveform (ie, the observer signal B2), then (1, 1), (0, 1), (0, 0), (1, 0), (1, 1), (0, 1)... And similarly, four different types of transitions can be observed at different locations in the series of observed pairs, ie (1,1)->(0,1),(0,1)->(0 , 0), (0,0)->(1,0), (1,0)->(1,1). Thus, even when the observer signal has a non-periodic and irregular waveform, the occurrence of a transition can be used to indicate the relative frequency between the observed signal and the observer signal.

As a result of the above two examples, the relationship between the observed signal and the observer signal can be detected by observing the transition found in the series of observed signals. When the observer frequency is higher than half of the observed frequency, such as B1>A in the above example, four different types of transitions can be found in the series of observed pairs, ie (1,1)->( 1,0), (1,0)->(0,0),(0,0)->(0,1),(0,1)->(1,1). On the other hand, when the observer frequency is lower than half of the observed frequency, such as B2 < A in the above example, four different types of transitions can be found in the series of observed pairs, that is, (1, 1)->(0,1),(0,1)->(0,0),(0,0)->(1,0),(1,0)->(1,1). All other types of transitions, such as (1,1)->(0,0), (1,0)->(0,1), or vice versa, can be safely discarded without affecting detection. mechanism.

This detection of the transition pattern of the observed signal and the relationship between the observer and the relative frequency of the observed signal have two important implications. The first implication is that phase detection is no longer needed to align the edges of the difference signal between the reference signal and the VCO/ICO output signal prior to comparison. This is not important because edge alignment imposes very difficult limitations on phase detection for high speed applications. The second implication is that the reference signal no longer needs to be a fixed external source, such as a crystal. Rather, the reference signal can be any digital bit string, and the improved phase detection mechanism can perform the necessary phase detection operations for the PLL. With the improved phase detection mechanism, the PFD can easily output a signal indicating the relationship between the observed frequency and the observer frequency based on the number of observed signals versus the transition pattern found in the series.

Thus, the fifth diagram shows a schematic diagram of a phase locked loop (PLL) with an improved phase detection mechanism in accordance with the present invention. As shown in the fifth figure, the PLL of the present invention includes a phase frequency detector (PFD) 501, a controller 502, a digital to analog (D2A) module 503, and a voltage controlled oscillator/current controlled oscillator (VCO/ICO). 504. PFD 501 has a reference signal input 510 and an input from output signal 504a of VCO/ICO 504 and is coupled to controller 502. The controller 502 is then further coupled to the D2A module 503, and the D2A module 503 converts the control signal from the controller 502 into an analog voltage or current to control the frequency and phase of the VCO/ICO 504. It should be noted that the PFD 501 of the present invention has an improved phase detection mechanism according to the exemplary waveforms of the third and fourth figures. Thus, PFD 501 is compared to VCO output signal 504a and reference signal 510 to produce a signal indicative of whether the VCO output signal is faster or at a frequency that is closer to the reference fine number. Based on receiving signals from the PFD 501, the controller 502 controls the output analog voltage or current of the D2A module 503 to control the frequency and phase of the output signal 504a of the VCO/ICO 504.

It should be noted that when the reference signal 510 is stopped or disappears, the controller 502 will maintain the original signal before stopping the reference signal 510, that is, keep the control signal transmitted to the D2A module 503, so that the D2A module 503 The analog voltage/current output to the VCO/ICO will not be changed to change the frequency and phase of the output signal 504a. In other words, the output signal 504a is held, i.e., locked, until the reference signal 510 reappears. In this way, the PFD can be switched to a different reference signal as a basis for phase detection comparison. An exemplary embodiment of implementing "locking" is to implement a D2A module 503 using a counter or any peer-to-peer mechanism, and any peer-to-peer mechanism can be increased and decreased such that a signal representing a faster or slower frequency can be Increase or decrease the value as usual. When the reference signal 510 disappears, the counter or any peer to peer mechanism maintains the value such that no increase or decrease operations are performed to change the held value.

The main application of the PLL with improved phase detection mechanism of the present invention is an electronic device such as USB 2.0, which can use a data string from a host such as a personal computer (PC) as a reference signal for synchronization.

It is also worth noting that the improved phase detection mechanism can be further extended to include more than one delayed signal to accelerate convergence when the difference between the observer frequency and the observed frequency is very large. For example, a second delayed signal A' having a slight phase delay, a third delayed signal A" having more phase delay, and the like may be added so that the observed signal group (A, A', A"...) is Recorded in an improved phase detection mechanism to accelerate convergence at different frequencies.

Although the invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited by the details. Various substitutions and modifications have been suggested in the above description, and other substitutions and modifications will occur to those skilled in the art. All such substitutions and modifications are intended to be included within the scope of the invention as defined by the appended claims.

101. . . Phase frequency detector (PFD)

101a. . . control signal

102. . . Loop filter

102a. . . Voltage signal

103. . . Voltage controlled oscillator (VCO)

103a. . . output signal

104. . . Divider

104a. . . Feedback signal

110. . . Reference signal

501. . . Phase frequency detector (PFD)

502. . . Controller

503. . . Digital to analog (D2A) module

504. . . Voltage Controlled Oscillator / Current Controlled Oscillator (VCO/ICO)

504a. . . output signal

510. . . Reference signal input

A. . . signal

Ad. . . Delayed signal

B1. . . signal

B2. . . signal

The present invention can be understood in more detail by studying the above detailed description in conjunction with the examples and the referenced drawings, wherein:

The first figure shows a schematic diagram of a conventional phase-locked loop (PLL);

The second figure shows a waveform diagram of conventional phase detection based on edge alignment;

The third figure shows a first exemplary waveform diagram for improving phase detection in accordance with the present invention;

The fourth figure shows a second exemplary waveform diagram for improving phase detection in accordance with the present invention;

The fifth diagram shows a schematic diagram of a phase-locked loop (PLL) with an improved phase detection mechanism.

501. . . Phase frequency detector (PFD)

502. . . Controller

503. . . Digital to analog (D2A) module

504. . . Voltage Controlled Oscillator / Current Controlled Oscillator (VCO/ICO)

504a. . . output signal

510. . . Reference signal input

Claims (10)

A phase-locked loop with an improved phase detection mechanism includes: a phase frequency detector having a first input and a second input, and comparing a plurality of observed signal levels of the second input and At least one delaying the second input, and generating a signal according to the relative frequencies of the first input and the second input, indicating whether the frequency of the second input is faster or slower than the frequency of the first input, the observation The arriving signal level is obtained by sampling the second input and the delayed second input signal level when the first input is changed from a first level to a second level, and the delayed second input is Formed by the second input delay phase; a controller coupled to the phase frequency detector for receiving the signal from the phase frequency detector and generating a control signal; a digital to analog module Connected to the controller for receiving the control signal and generating an analog voltage/current output; and a voltage controlled oscillator coupled to the digital to analog module for receiving the analog voltage/current output, Adjusting an output signal, wherein the first input of the phase frequency detector is connected to the reference signal, and the second input is connected to the output signal of the voltage controlled oscillator, and the improved phase detection mechanism A plurality of the delayed second inputs are used, each of the delayed second inputs having the same waveform and different phases from each other. The phase-locked loop of claim 1, wherein the voltage controlled oscillator is replaceable by a current controlled oscillator. The phase-locked loop of claim 1, wherein the phase frequency detector compares the first input, the second input, and a delayed second input, the delayed second input having a waveform identical to the a second input having a phase delay, the second input and a delay of the first group of transition patterns of the second input having an occurrence of a transition indicating a frequency of the first input to a frequency of the second input Still fast. The phase-locked loop of claim 1, wherein the phase frequency detector compares the first input, the second input, and a delayed second input, the delayed second input having a waveform identical to the a second input having a phase delay, the second input and a second group of delaying the second input transition pattern having a transition occurring to indicate that the frequency of the first input is greater than the frequency of the second input Still slow. The phase-locked loop of claim 1, wherein the reference signal is an external crystal. The phase-locked loop of claim 1, wherein the reference signal is digital data from a host. The phase-locked loop of claim 3, wherein the first group of the second input and the delayed second input transition pattern comprises (1,1)->(1,0), (1, 0)->(0,0),(0,0)->(0,1),(0,1)->(1,1), the first item of each pair is the second input The level is observed and the second term is the observed level of the second input of the delay. According to the phase locked loop of claim 4, wherein the second input and A second group of transition patterns that delay the second input includes (1,1)->(0,1), (0,1)->(0,0),(0,0)->(1, 0), (1,0)->(1,1), the first item of each pair is the observation level of the second input, and the second item is the observation level of the second input of the delay. According to the phase locked loop of claim 1, wherein the digital to analog module maintains the original control signal value before the reference signal stops, so that the digital to analogy The module will not change the frequency and phase of the output signal without changing the analog voltage/current output delivered to the voltage controlled oscillator/current controlled oscillation. The phase-locked loop of claim 9, wherein the digit-to-analog module is implemented by a counter or a peer-to-peer mechanism that can be increased or decreased.