TWI409936B - Electrostatic discharge protection circuits - Google Patents

Abstract

An electrostatic discharge protection circuit. A transistor is coupled between a node and a ground and has a gate coupled to the ground. A diode chain is coupled between the node and a pad and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in the forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in the forward conduction direction from the node to the pad.

Description

Electrostatic discharge protection circuit

The invention relates to electrostatic discharge (ESD) protection, in particular to electrostatic discharge protection of high voltage pins in a low voltage process.

The electrostatic discharge phenomenon easily causes damage to the semiconductor element and affects the normal function of the integrated circuit. Therefore, when designing an integrated circuit, it is necessary to strengthen the protection design of the electrostatic discharge to enhance the electrostatic discharge sensitivity of the integrated circuit.

Nowadays, due to the progress of the low voltage (LV) process, more and more integrated circuits can be operated at lower operating voltages, such as the commonly used operating voltages of general logic circuits (ie 5V, 3.3V, 2.5V). , 1.8V, etc.). However, for some products with special application requirements, some pins in the integrated circuit need to operate at a higher voltage, such as: 7V, 8V, 9V, and so on. Among them, the higher voltage is generally greater than 5V and does not belong to the high voltage (HV) range, and is generally referred to as medium voltage (MV).

In the integrated circuit, if the medium voltage is applied to the low voltage component, the breakdown of the low voltage component will be caused, so that the low voltage component cannot work normally, that is, the electrostatic discharge protection circuit in the low voltage process cannot use the pin using the medium voltage. Protected. Therefore, there is a need for a circuit that achieves medium voltage ESD protection over existing low voltage processes.

The present invention provides an ESD protection circuit, comprising: a transistor coupled between a node and a ground, having a gate coupled to the ground; a diode string coupled to the node and Between the bonding pads, there are a plurality of first diodes connected in series, the first two-pole system is connected in a forward direction from the bonding pad to the node; and a second diode is coupled Connected between the node and the bonding pad, the second two-pole system is connected in a forward direction from the node to the bonding pad.

Furthermore, the present invention provides an ESD protection circuit comprising: an N-type transistor coupled between a node and a ground, and having a gate coupled to the ground; a first diode, Having a first anode and a first cathode, the first anode is coupled to a bonding pad; a second diode has a second anode and a second cathode, and the second anode is coupled to the first a cathode, wherein the second cathode is coupled to the node; and a third diode having a third anode and a third cathode, the third anode is coupled to the node, and the third cathode is coupled to The above bonding pad.

Furthermore, the present invention provides an ESD protection circuit, comprising: a transistor coupled between a node and a ground, having a gate coupled to the ground; a diode string coupled to Between the node and a bonding pad, a plurality of first diodes connected in series; and a second diode coupled between the node and the bonding pad, wherein one of the bonding pads When the first voltage is greater than a second voltage of the node, the first two-pole system is forwardly connected by the bonding pad to the node, and when the second voltage is greater than the first voltage, the second The two-pole system is guided by the direction from the above node to the bonding pad.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Example:

Fig. 1 shows an electrostatic discharge protection circuit 100 according to an embodiment of the present invention. The ESD protection circuit 100 includes a bonding pad 10, a diode chain 20, a diode 30, and a transistor 40. The bonding pad 10 is coupled to the pin for receiving the medium voltage signal. The diode string 20 is composed of four diodes 22, 24, 26 and 28 connected in series, wherein the anode of the diode 22 is coupled to the junction pad 10 and the cathode coupling of the diode 22. The anode connected to the diode 24, the cathode of the diode 24 is coupled to the anode of the diode 26, the cathode of the diode 26 is coupled to the anode of the diode 28, and the cathode of the diode 28 is coupled. To node 50. Therefore, the two-pole system in the diode string 20 is connected in a forward conduction direction from the bonding pad 10 to the node 50. The diode 30 is coupled between the bonding pad 10 and the node 50, and the diode 30 is connected in a forward direction from the node 50 to the bonding pad 10, that is, the anode of the diode 30 is coupled to the node 50. The cathode is coupled to the bond pad 10. The transistor 40 is coupled between the node 50 and the ground VSS, wherein the gate of the transistor 40 is coupled to the ground VSS. In this embodiment, the transistor 40 is an N-type metal oxide semiconductor (MOS) transistor. In an electrostatic discharge event, when the voltage on bond pad 10 is greater than the voltage at node 50, the two-pole system within diode string 20 is compliant in the direction from bond pad 10 to node 50. On the other hand, when the voltage on the node 50 is greater than the voltage of the bonding pad 10, the diode 30 is guided in the direction from the node 50 to the bonding pad 10.

Figure 2 is a cross-sectional view showing a diode according to an embodiment of the present invention. As shown in FIG. 2, the N-type well region 220 is disposed in the P-type substrate 210, and the P-type doped region 230 is disposed in the N-type well region 220. The P-type doping region 230 and the N-type well region 220 form a P-type diode 250. As shown in FIG. 2, the P-type diode 250 is surrounded by the N-type well region 220. Since the breakdown voltage of the N-type well region 220 to the P-type substrate 210 is high, the P-type diode 250 can be used for stacking. Therefore, in one embodiment of the present invention, the diodes and the diodes 30 in the diode string 20 in FIG. 1 are all P-type diodes 250.

Referring to Figure 1, the number of diodes in the diode string 20 is determined by the actual operating voltage of the medium voltage signal and the breakdown voltage of the transistor 40. For general logic circuits, commonly used operating voltages are 5V, 3.3V, 2.5V, 1.8V, and so on. However, for some of the pins of the logic circuit, it is necessary to operate at a higher voltage, for example, a voltage greater than 5, that is, medium voltage. For example, assume that the breakdown voltage of the transistor 40 is 8V, and the actual operating voltage of the medium voltage signal is 9V. Next, assuming that the guard band is 20%, the maximum voltage operating on the bond pad 10 is 10.8V. Next, the voltage difference between the maximum voltage of the bonding pad 10 and the breakdown voltage of the transistor 40 is 2.8V. Since the forward bias of the diode is approximately 0.7V. Therefore, when the voltage difference is 2.8V, four diodes are required in the diode string 20. In this embodiment, a medium voltage of 9 V is taken as an example, which is not intended to limit the scope of the invention. Depending on the medium voltage and the breakdown voltage of the low voltage components, the user can select the appropriate number of diodes.

The electrostatic discharge protection circuit according to the embodiment of the invention can provide medium voltage electrostatic discharge protection in a low voltage circuit formed by a low voltage process. Furthermore, the present invention provides higher voltage ESD protection in existing low voltage processes without the need for additional process cost.

The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Mat

20. . . Diode string

22, 24, 26, 28, 30. . . Dipole

40. . . Transistor

50. . . node

100. . . Electrostatic discharge protection circuit

210. . . P-type substrate

220. . . N type well area

230. . . P-doped region

250. . . P-type diode

VSS. . . Ground terminal

1 is a view showing an electrostatic discharge protection circuit according to an embodiment of the present invention; and FIG. 2 is a cross-sectional view showing a process of a diode according to an embodiment of the present invention.

10. . . Mat

20. . . Diode string

22, 24, 26, 28, 30. . . Dipole

40. . . Transistor

50. . . node

100. . . Electrostatic discharge protection circuit

VSS. . . Ground terminal

Claims (13)

An ESD protection circuit includes: a transistor having a first end, a second end, and a gate, wherein the first end and the gate are coupled to a ground; a diode string, coupled Connected to the second end of the transistor and a bonding pad, having a plurality of first diodes connected in series, wherein the first two-pole system is connected to the transistor by the bonding pad And a second diode coupled between the second end of the transistor and the bonding pad, wherein the second diode system is smoothed by the transistor to the bonding pad The electrical discharge protection circuit is applied in a low voltage circuit formed by a low voltage process, and a first operating voltage of the low voltage circuit is lower than a first voltage value; wherein the bonding The pad is coupled to a pin, and when the non-electrostatic discharge event occurs, a second operating voltage applied to the pin is higher than the first voltage value; wherein the first voltage value is about 5 volt. The electrostatic discharge protection circuit according to claim 1, wherein the transistor is an N-type MOS transistor. The electrostatic discharge protection circuit of claim 1, wherein the first diode and the second diode are a P-type diode. For example, the electrostatic discharge protection circuit described in claim 3, The P-type diode includes: an N-type well region disposed on a P-type substrate; and a P-type doped region disposed in the N-type well region. The electrostatic discharge protection circuit of claim 1, wherein the number of the first diodes is determined according to the second operating voltage and a breakdown voltage of the transistor. An ESD protection circuit includes: an N-type transistor having a first end, a second end, and a gate, wherein the first end and the gate are coupled to a ground; a first diode The body has a first anode and a first cathode, the first anode is coupled to a bonding pad, a second diode has a second anode and a second cathode, and the second anode is coupled to the a first cathode, wherein the second cathode is coupled to the second end of the N-type transistor; and a third diode having a third anode and a third cathode, the third anode being coupled to the The second end of the N-type transistor, and the third cathode is coupled to the bonding pad; wherein the ESD protection circuit is applied to a low voltage circuit formed by a low voltage process, and a first of the low voltage circuit The operating voltage is lower than a first voltage value; wherein the bonding pad is coupled to a pin, and when an electrostatic discharge event occurs, a second operating voltage applied to the pin is higher than the first voltage Value A first voltage value is about 5 volts. The electrostatic discharge protection circuit of claim 6, wherein the first diode, the second diode, and the third diode are a P-type diode. The electrostatic discharge protection circuit of claim 7, wherein the P-type diode comprises: an N-type well region disposed on a P-type substrate; and a P-type doped region disposed on the N-type Well area. An ESD protection circuit includes: a transistor having a first end, a second end, and a gate, wherein the first end and the gate are coupled to a ground; a diode string, coupled Connected between the second end of the transistor and a bonding pad, having a plurality of first diodes connected in series; and a second diode coupled to the second end of the transistor and Between the bonding pads; wherein, when a first voltage of one of the bonding pads is greater than a second voltage of the second end of the transistor, the first two-pole system is in a direction from the bonding pad to the transistor And when the second voltage is greater than the first voltage, the second two-pole system is in a direction to pass from the transistor to the bonding pad; wherein the electrostatic discharge protection circuit is applied by a low voltage circuit formed by the low pressing process, and a first operating voltage of the low voltage circuit is less than 5V; wherein the bonding pad is coupled to a pin and when there is no static discharge When the event occurs, a second operating voltage applied to the pin is higher than 5V. The electrostatic discharge protection circuit of claim 9, wherein the transistor is an N-type MOS transistor. The electrostatic discharge protection circuit of claim 9, wherein the first diode and the second diode are a P-type diode. The electrostatic discharge protection circuit of claim 11, wherein the P-type diode comprises: an N-type well region disposed on a P-type substrate; and a P-type doped region disposed on the N-type Well area. The electrostatic discharge protection circuit of claim 9, wherein the number of the first diodes is determined according to the second operating voltage and a breakdown voltage of the transistor.