TWI407223B - Active device array substrate - Google Patents

Abstract

An active device array substrate having a substrate with a display region and a periphery circuit region outside the display region is provided. The active device array substrate includes a pixel array, a plurality of traces, and a third conductive layer. The pixel array is disposed within the display region. The plurality of traces disposed on the periphery circuit region is electrically connected to the pixel array, wherein at least one part of the traces includes a first conductive layer, a second conductive layer, and a passivation layer. The first conductive layer is disposed on the substrate. The second conductive layer is disposed adjacent to an upper projection of the first conductive layer, and the first conductive layer and the second conductive layer are alternatively disposed on the substrate. The passivation covers the first conductive layer and the second conductive layer. The third conductive layer is disposed on the passivation layer and crosses cover the width of the trace.

Description

Active device array substrate

The present invention relates to an array substrate, and more particularly to an active device array substrate.

With the dramatic advancement of computer performance and the rapid development of Internet and multimedia technologies, the size of video or video devices has become increasingly thin. In the development of displays, with the advancement of optoelectronic technology and semiconductor manufacturing technology, liquid crystal display panels with superior features such as high image quality, good space utilization efficiency, low power consumption, and no radiation have gradually become the mainstream of the market.

FIG. 1A is a top plan view of an active device array substrate of a conventional liquid crystal display panel. Referring to FIG. 1A, a conventional active device array substrate 100 includes a substrate 110 having a display area 102 and a peripheral circuit region 104, a plurality of scan lines 120, a plurality of data lines 130, and a picture. The array 140 has a plurality of traces 150 and a plurality of pads 160. The pixel array 140 has a plurality of pixels 142 arranged in an array, and the pixels 142 are controlled by the scan lines 120 and the data lines 130, respectively.

As shown in FIG. 1A, each of the traces 150 is connected to the pad 160 and the scan line 120 or the data line 130, respectively. For example, the electronic signals are sequentially input to the pixel electrodes 146 in the corresponding pixels 142 via the corresponding pads 160, the traces 150, the data lines 130, and the active elements 144 in the pixels 142. Fig. 1B is a cross-sectional view of the area of Fig. 1A taken along line AA'. Referring to FIG. 1B, the trace 150 is formed by stacking two layers of conductor layers 170a and 170b. When the transparent conductor layer 170c crosses the trace 150 and transmits signals thereon, the transparent conductor layer 170c is easily graded on the bottom layer. The phenomenon of burning occurs at the most severe change, and the position where it occurs is shown as B in Fig. 1A and Fig. 1B. As a result, the trace 150 cannot smoothly transmit the signal, and the pixel 142 on the pixel array 140 cannot be driven smoothly, which affects the display function of the entire liquid crystal display panel.

The invention provides an active device array substrate, which can reduce the height difference caused by the topography of the transparent conductor layer in the trace, thereby reducing the probability of burning and the like when crossing the trace.

The present invention provides an active device array substrate having a substrate, and the substrate has a display area and a peripheral circuit area outside the display area, and the active device array substrate includes a pixel array, a plurality of traces, and a first Three conductor layer. The pixel array is located in the display area. A plurality of traces are located on the peripheral circuit region and electrically connected to the pixel array, wherein at least a portion of each trace includes a first conductor layer, a second conductor layer, and a protective layer. The first conductor layer is on the substrate. The second conductor layer is disposed on the adjacent side of the first conductor layer above the orthographic projection surface, and the second conductor layer and the first conductor layer are misaligned on the substrate. The protective layer covers the first conductor layer and the second conductor layer. The third conductor layer is on the protective layer, and the third conductor layer spans the first conductor layer and the second conductor layer of the trace.

In an embodiment of the invention, the areas of the first conductor layer and the second conductor layer on the substrate are separated from each other.

In an embodiment of the invention, the active device array substrate may further include a gate insulating layer, wherein the gate insulating layer is located between the first conductor layer and the second conductor layer. In this case, in the trace, the first conductor layer and the third conductor layer are formed, for example, by a laminate of a gate insulating layer and a protective layer, and the second conductor layer and the third conductor layer are, for example, a protective layer. Composition.

In an embodiment of the invention, the maximum height of the third conductor layer in the trace is h ₁ , and the minimum height of the third conductor layer on the substrate is h ₂ , and h ₁ -h ₂ ≦ 3,500 angstroms.

In an embodiment of the present invention, the active device array substrate further includes a driving circuit, wherein the driving circuit inputs a driving signal into the pixel array via the routing, and the first conductor layer and the second conductor layer can transmit The same drive signal. Of course, the first conductor layer and the second conductor layer can also transmit different driving signals.

In an embodiment of the invention, the pixel array includes a plurality of scan lines and a plurality of data lines and a plurality of pixels. The trace is electrically connected to one of the scan lines or one of the data lines. Each pixel includes an active component and a pixel electrode, wherein the active component is electrically connected to the corresponding scan line and the data line, and the active component includes a gate, a gate insulating layer, a channel layer, a source and a The drain electrode is disposed on the substrate, the gate insulating layer covers the gate, the channel layer is on the gate insulating layer above the gate, and the source and the drain are located on both sides of the channel layer. The pixel electrode is connected to the drain. Wherein, the gate and the scan line are the same film layer as the first conductor layer, and the source, the drain, the data line and the second conductor layer are the same film layer, and the pixel electrode and the third conductor layer are the same film layer, and the gate insulation The layer is between the first conductor layer and the second conductor layer, and the protective layer is between the second conductor layer and the third conductor layer.

In an embodiment of the present invention, the number of the first sub-wirings formed by the first conductor layer in the above-mentioned routing is plural, and the second sub-wiring formed by the second conductor layer in the routing The number is multiple, and the first sub-line and the second sub-line are alternately arranged on the substrate.

In an embodiment of the invention, the areas of the first trace and the second trace on the substrate do not overlap each other.

In an embodiment of the invention, the third conductor layer is electrically connected to the other trace, and the third conductor layer transmits a different signal to the first conductor layer or the second conductor layer.

Based on the above, the wiring of the present invention in the peripheral circuit region adopts a design in which the plurality of conductor layers are displaced from each other, so that the transparent conductor layer disposed above the trace can be smoothly traversed, so that the present invention can reduce the trace below the transparent conductor layer. Film thickness gap to improve the burnt-out phenomenon of the traces on the active device array substrate

The above described features and advantages of the present invention will be more apparent from the following description.

2 is a top plan view of an active device array substrate according to an embodiment of the invention. Referring to FIG. 2, the active device array substrate 200 of the present embodiment has a substrate 201 having a display area 202 and a peripheral circuit region 204 outside the display area 202, and the active device array substrate 200 includes a substrate. The pixel array 210 in the display area 202 and the plurality of traces 220 on the peripheral circuit area 204, wherein the traces 220 are electrically connected to the pixel array 210 in the display area 202. In this embodiment, the active device array The substrate 200 further includes a driving circuit 230 disposed in the peripheral circuit region 204. The driving circuit 230 inputs a driving signal into the pixel array 210 via the trace 220. In addition, as shown in FIG. 2, the pixel array 210 includes a plurality of scan lines 240 and a plurality of data lines 250 and a plurality of pixels 260. The trace 220 is electrically connected, for example, to one of the scan lines 240 or one of the data lines 250. In the display area 202, each pixel 260 includes an active component 262 and a pixel electrode 264. The active component 262 is electrically connected to the corresponding scan line 240 and the data line 250.

In particular, the active device array substrate 200 of the present invention is further designed in the peripheral circuit region 204 for the structure of the traces 220 such that the transparent conductor layer above the traces 220 can be more gently covered over the traces 220. The phenomenon that the transparent conductor layer burns at the intersection with the trace 220 is avoided. For further clarification, the following description will be made by taking a portion of the trace 220 disposed in the region 204 of FIG. 2 for partial enlargement. In other words, the trace 220 on the active array substrate 201 of the present invention may be disposed in the region 204 of FIG. Trace 220 at any location within.

3A is a plan view of the active device array substrate according to the first embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line A-A' of FIG. 3A. Referring to FIG. 3A and FIG. 3B, at least a portion of the trace 220 on the active device array substrate 200 of the present embodiment includes a first conductor layer M1, a second conductor layer M2, and a protective layer I2. Specifically, the first conductor layer M1 is located on the substrate 201. In this embodiment, the second conductor layer M2 and the first conductor layer M1 are, for example, connected in parallel. In other words, the first conductor layer M1 and the second conductor layer M2 are at both ends of the trace 220 (ie, the signal input end and The signal outputs are connected to each other to deliver the same signal to the pixel array 210. Of course, in other embodiments, the first conductor layer M1 and the second conductor layer M2 are not connected to each other at both ends of the trace 220 (ie, the signal input end and the signal output end), so that the second conductor layer M2 on the trace. Different signals are respectively transmitted to the first conductor layer M1, and the invention is not limited thereto. As shown in FIG. 3A and FIG. 3B, the second conductor layer M2 is disposed on the adjacent side of the front surface of the first conductor layer M1, in particular, in the same trace 220, the second conductor layer M2 and the first The conductor layers M1 are respectively disposed on the substrate 201 in a staggered manner. The protective layer I2 covers the first conductor layer M1 and the second conductor layer M2. Moreover, the active device array substrate 200 of the present embodiment has a third conductor layer M3 spanning the trace 220 on the peripheral circuit region 204, and the third conductor layer M3 is located on the protective layer I2. In this embodiment, the third The conductor layer M3 is, for example, a transparent conductor layer composed of indium tin oxide or indium zinc oxide.

In more detail, the third conductor layer M3 is electrically connected between different traces 220, for example, as shown in FIG. 3A, the third conductor layer M3 is electrically connected to the other trace 220', and thus the third conductor The signal transmitted by the layer M3 is different from the signal transmitted by the first conductor layer M1 and the signal transmitted by the second conductor layer M2. In addition, the areas of the first conductor layer M1 and the second conductor layer M2 on the substrate 201 do not overlap each other. In other words, as shown in FIG. 3B, the areas of the first conductor layer M1 and the second conductor layer M2 on the substrate 201 are separated from each other. And spaced apart by a distance d1. In this way, for the third conductor layer M3 crossing the first conductor layer M1 and the second conductor layer M2, since the film thickness of the bottom layer is relatively uniform, the third conductor layer M3 can be more smoothly covered in the trace. 220, so that the third conductor layer M3 does not have a large topographic relief when it spans the trace 220 having the multilayer conductor layer. Therefore, in the actual operation process, the signal can be smoothly transmitted in the relatively smooth third conductor layer M3 to solve the problem that the transparent conductor layer is easily burned when crossing the trace 220 in the prior art.

In addition, in the active device array substrate 200 of the present embodiment, a gate insulating layer I1 may be further disposed between the first conductor layer M1 and the second conductor layer M2 when the wiring is formed, so that in the trace 220, The first conductor layer M1 and the third conductor layer M3 are formed, for example, by a laminate of a gate insulating layer I1 and a protective layer I2, and the second conductor layer M2 and the third conductor layer M3 are, for example, protected by a protective layer I2. Composition. In this way, the film thickness difference between the corresponding first conductor layer M1 region and the corresponding second conductor layer M2 region in the trace 220 can be narrowed, thereby reducing the climbing slope when the third conductor layer M3 crosses the trace 220. For example, with respect to the substrate 201, the maximum height of the third conductor layer M3 in the trace 220 is, for example, h ₁ , and the minimum height of the third conductor layer M3 on the substrate 201 is, for example, h ₂ , and is in this embodiment. In the trace 220 of the active array substrate 201, h ₁ - h ₂ ≦ 3500 Å.

Of course, according to the design spirit of the structure of the foregoing trace 220, in the same trace 220, the first conductor layer M1 and the second conductor layer M2 are arranged offset from each other, so in other embodiments, the first conductor layer M1 and the first conductor layer The two-conductor layer M2 can also be directly disposed on the substrate 201. In other words, in other embodiments, the gate insulating layer I1 can also be selected, and the trace 220 on the active device array substrate 200 of the present invention. The film structure between the first conductor layer M1 and the substrate 201 or between the second conductor layer M2 and the substrate 201 is not limited.

Specifically, in an actual manufacturing process, the thickness of the first conductor layer M1 is, for example, 3,500 angstroms, the thickness of the gate insulating layer I1 is, for example, 3,300 angstroms, and the thickness of the first conductive layer M1 is, for example, 2,800 angstroms, the protective layer I2. The thickness is, for example, 2000 angstroms. Therefore, in the present embodiment, the third conductor layer M3 spans the gap H ₁ (height difference) corresponding to the first conductor layer M1 in the trace 220 to 3500 angstroms, and the third conductor layer M3 spans in the trace 220 off the second conductive layer M2 corresponds to the difference of H ₂ (the height difference) of 2800 angstroms, and the third conductive layer M3 corresponding to the trace 220 and the first conductive layer region M1 corresponding to the difference between H ₃ M2-off region of the second conductive layer (height difference) is 500 angstroms.

In the first embodiment of the present invention, the number of the first sub-wirings 220A formed by the first conductor layer M1 in the trace 220 is a single strip, and the second sub-layer formed by the second conductor layer M2 in the trace 220 The number of the traces 220B is a single strip, but the invention is not limited thereto, and the designer can extend the design concept of the trace 220 described above based on the impedance of the trace 220, the layout space of the substrate 201, or the requirements on the process. For the same trace 220, the number of the first sub traces 220A and the number of the second sub traces 220B are multiple.

4A is a plan view showing a trace of an active device array substrate according to a second embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along line A-A' of FIG. 4A. Referring to FIG. 4A and FIG. 4B simultaneously, in the active device array substrate 200 of the embodiment, the number of the first sub-wirings 220A formed by the first conductor layer M1 in the trace 320 is plural, and the second conductor layer is The number of the second sub-wirings 220B formed by the M2 is plural, and the widths of the plurality of first conductor layers and the widths of the plurality of second conductor layers are not limited to the same; and, the first sub-route 220A The second sub traces 220B are alternately arranged on the substrate 201. In other words, each of the first sub traces 220A is located between two adjacent second sub traces 220B, and each of the second sub traces 220B Located between two adjacent first sub-lines 220A. Moreover, the projected areas of the first sub-wiring 220A and the second sub-wiring 220B on the substrate 201 do not overlap each other.

In addition, it is worth mentioning that the foregoing routings 220 and 320 are made in a manner compatible with the original process of the active device array substrate. In detail, the relationship between the constituent film layers of the traces 220 and the constituent film layers of the pixel 260 structure will be described below by taking the structure of the pixel 260 shown in FIG. 2A as an example.

The left side of FIG. 5 is a cross-sectional view of the trace shown in FIG. 4B, and the right side of FIG. 5 is a cross-sectional view of the pixel of FIG. Referring to FIG. 5, the active device 262 includes a gate 262G, a gate insulating layer I1, a channel layer 262C, a source 262S and a drain 262D. The gate 262G is located on the substrate 201, and the gate insulating layer I1 covers the gate. The pole 262G, the channel layer 262C is located on the gate insulating layer I1 above the gate 262G, and the source 262S and the drain 262D are located on both sides of the channel layer 262C, and the pixel electrode 264 is connected to the drain via the opening of the protective layer I2 262D connection. As shown in FIG. 5, the gate 262G and the scan line 240 are the same film layer as the first conductor layer M1, and the gate 262G, the scan line 240, and the first conductor layer M1 can be fabricated by the same mask process. The source 262S, the drain 262D, the data line 250 and the second conductor layer M2 are the same film layer, and the source 262S, the drain 262D, the data line 250 and the second conductor layer M2 can be fabricated by the same mask process. The pixel electrode 264 and the third conductor layer M3 are the same film layer, and the pixel electrode 264 and the third conductor layer M3 can be fabricated by the same mask process. In addition, as described above, the gate insulating layer I1 may be further included in the trace 220, and the gate insulating layer I1 is located between the first conductor layer M1 and the second conductor layer M2, and the protective layer I2 is located at the second conductor layer M2 and the third layer. Between the conductor layers M3.

In summary, the active device array substrate of the present invention has at least some or all of the following advantages:

1. Compared with the prior art, the laminated conductor layer is used as the trace on the non-display area, and since the present invention changes the trace to the multilayer conductor layer which is disposed in a dislocated configuration, the trace of the misalignment configuration of the present invention has a relatively gentle line. The terrain to improve the burning of the transparent conductor layer across the trace during the transmission of the signal.

The active device array substrate of the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention, and any one of ordinary skill in the art without departing from the spirit and scope of the present invention. A few modifications and refinements may be made, and the scope of protection of the present invention is defined by the scope of the appended claims.

100, 200. . . Active device array substrate

102, 202. . . Display area

104, 204. . . Peripheral circuit area

110, 201. . . Substrate

120, 240. . . Scanning line

130, 250. . . Data line

140, 210. . . Pixel array

142, 260. . . Pixel

150, 220, 220', 320. . . Traces

160. . . Pad

144, 262. . . Active component

146, 264. . . Pixel electrode

170 a, 170b. . . Conductor layer

170c. . . Transparent conductor layer

220A. . . First sub-line

220 B. . . Second sub-line

230. . . Drive circuit

262. . . Active component

262C. . . Channel layer

262D. . . Bungee

262G. . . Gate

262S. . . Source

D1. . . spacing

h ₁ . . . maximum height

h ₂ . . . Minimum height

H ₁ . . . The third conductor layer spans the fault corresponding to the first conductor layer in the trace

H ₂ . . . The third conductor layer spans the fault corresponding to the second conductor layer in the trace

H ₃ . . . a third conductor layer in the trace corresponding to the first conductor layer region and the corresponding second conductor layer region

I1. . . Brake insulation

I2. . . The protective layer

M1. . . First conductor layer

M2. . . Second conductor layer

M3. . . Third conductor layer

W. . . Width of the trace

FIG. 1A is a top plan view of an active device array substrate of a conventional liquid crystal display panel.

Fig. 1B is a cross-sectional view of the area of Fig. 1A taken along line AA'.

2 is a top plan view of an active device array substrate according to an embodiment of the invention.

3A is a top plan view of an active device array substrate in accordance with a first embodiment of the present invention.

Fig. 3B is a cross-sectional view taken along line A-A' of Fig. 3A.

4A is a top plan view of an active device array substrate in accordance with a second embodiment of the present invention.

Fig. 4B is a cross-sectional view taken along line A-A' of Fig. 4A.

The left side of FIG. 5 is a schematic cross-sectional view of the trace shown in FIG. 4B.

200. . . Active device array substrate

201. . . Substrate

220. . . Traces

220A. . . First sub-line

220B. . . Second sub-line

D1. . . spacing

h ₁ . . . maximum height

h ₂ . . . Minimum height

H ₁ . . . The third conductor layer spans the fault corresponding to the first conductor layer in the trace

H ₂ . . . The third conductor layer spans the fault corresponding to the second conductor layer in the trace

H ₃ . . . a third conductor layer in the trace corresponding to the first conductor layer region and the corresponding second conductor layer region

I1. . . Brake insulation

I2. . . The protective layer

M1. . . First conductor layer

M2. . . Second conductor layer

M3. . . Third conductor layer

W. . . Width of the trace

Claims (11)

An active device array substrate having a substrate, the substrate having a display area and a peripheral circuit area outside the display area, the active device array substrate comprising: a pixel array located in the display area; and a plurality of strips a wire, located in the peripheral circuit region and electrically connected to the pixel array, wherein each of the wires has at least one portion including: a first conductor layer on the substrate; and a second conductor layer disposed on the wire a conductor layer having an adjacent side above the orthographic projection surface, wherein the second conductor layer and the first conductor layer are misaligned on the substrate; a protective layer covering the first conductor layer and the second conductor layer; A third conductor layer is disposed on the protective layer, and the third conductor layer spans the first conductor layer and the second conductor layer of the trace. The active device array substrate according to claim 1, wherein a projected area of the first conductor layer and the second conductor layer on the substrate is separated from each other. The active device array substrate according to claim 1, further comprising a gate insulating layer, wherein the gate insulating layer is located between the first conductor layer and the second conductor layer. The active device array substrate according to claim 3, wherein in the trace, the first conductor layer and the third conductor layer are formed by lamination of the gate insulating layer and the protective layer. The protective layer is formed between the second conductor layer and the third conductor layer. The active device array substrate according to claim 1, wherein a maximum height of the third conductor layer in the trace is h ₁ , and a minimum of the third conductor layer on the substrate The height is h ₂ and h ₁ -h ₂ ≦ 3500 angstroms. The active device array substrate of claim 1, further comprising a driving circuit, wherein the driving circuit inputs a driving signal into the pixel array via the traces, and the first conductor layer and the first The two conductor layers pass the same drive signal. The active device array substrate according to claim 6, wherein the first conductor layer and the second conductor layer transmit different driving signals. The active device array substrate of claim 1, wherein the pixel array comprises: a plurality of scan lines and a plurality of data lines, wherein the traces are electrically connected to one of the scan lines or the plurality of scan lines One of the data lines; each of the pixels includes: an active component electrically connected to the corresponding scan lines and the data lines, the active component including a gate and a gate insulation a layer, a channel layer, a source and a drain, wherein the gate is on the substrate, the gate insulating layer covers the gate, and the channel layer is on the gate insulating layer above the gate, the source a pole and the drain are located on both sides of the channel layer; and a pixel electrode is connected to the drain, wherein the gates, the scan lines and the first conductor layer are the same film layer, the sources a pole, the data lines and the second conductor layer are the same film layer, the pixel electrodes and the third conductor layer are the same film layer, the gate insulating layer is located at the first conductor layer and the Between the second conductor layers, and the protective layer is located at the second conductor layer and the third Between the conductor layers. The active device array substrate according to claim 1, wherein the number of the first sub-wirings formed by the first conductor layer in the trace is plural, and the second conductor in the trace The number of the second sub-wirings formed by the layer is multiple, and the first sub-wiring lines and the second sub-wiring lines are alternately arranged on the substrate. The active device array substrate of claim 1, wherein the projected areas of the first sub-wirings and the second sub-wirings on the substrate do not overlap each other. The active device array substrate according to claim 1, wherein the third conductor layer is electrically connected to another trace, and the third conductor layer and the first conductor layer or the second conductor layer are transferred Different signals.