TWI405334B - Field effect transistor - Google Patents
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- TWI405334B TWI405334B TW098102305A TW98102305A TWI405334B TW I405334 B TWI405334 B TW I405334B TW 098102305 A TW098102305 A TW 098102305A TW 98102305 A TW98102305 A TW 98102305A TW I405334 B TWI405334 B TW I405334B
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Description
本發明有關一使用非結晶形氧化物之場效電晶體。The present invention relates to a field effect transistor using an amorphous oxide.
場效電晶體(FETs)包括一閘極電極、一源極電極、及一汲極電極,且係電子主動裝置,其藉由經過施加至該閘極電極的電壓控制電流進入一通道層之流動而控制該源極電極及該汲極電極間之電流。FETs特別地是被稱為薄膜電晶體(TFTs),其當作該通道層使用一沈積在諸如陶瓷、玻璃、或塑膠基板的絕緣基板上之薄膜。Field effect transistors (FETs) include a gate electrode, a source electrode, and a drain electrode, and are electronic active devices that control the flow of current into a channel layer by a voltage applied to the gate electrode. The current between the source electrode and the drain electrode is controlled. FETs are specifically referred to as thin film transistors (TFTs) which serve as a channel layer using a thin film deposited on an insulating substrate such as a ceramic, glass, or plastic substrate.
該前述之TFTs係藉由使用一薄膜技術所形成,且因此該TFTs具有被輕易地形成在一具有相當大區域的基板上之優點,且因此廣泛地被用作一用於諸如液晶顯示器之平板顯示器的驅動裝置。特別地是,一主動液晶顯示器(ALCD)藉由使用形成在一玻璃基板上之TFTs打開/關閉每一影像像素。再者,用於未來之高性能有機LED顯示器(OLED),其係藉由TFTs有效地控制每一像素之電流。此外,實現一具有較高性能之液晶顯示器,其中具有驅動及控制整個影像之功能的周邊電路係在一影像區域之附近藉由使用TFTs形成在一基板上。The aforementioned TFTs are formed by using a thin film technique, and thus the TFTs have an advantage of being easily formed on a substrate having a relatively large area, and thus are widely used as a flat plate for use in, for example, a liquid crystal display. The drive of the display. In particular, an active liquid crystal display (ALCD) turns on/off each image pixel by using TFTs formed on a glass substrate. Furthermore, for future high performance organic LED displays (OLEDs), which effectively control the current of each pixel by TFTs. Further, a liquid crystal display having higher performance is realized in which peripheral circuits having a function of driving and controlling the entire image are formed on a substrate by using TFTs in the vicinity of an image area.
目前大部分受歡迎之TFTs係採用多晶矽薄膜或非結晶形矽薄膜當作通道層材料者。用於像素驅動之非結晶形矽TFTs及用於整個影像驅動/控制之高效能多晶矽TFTs已被實際使用。Most of the popular TFTs currently use polycrystalline germanium films or amorphous germanium films as channel layer materials. The amorphous 矽 TFTs for pixel driving and the high performance polysilicon TFTs for the entire image driving/control have been practically used.
已往所開發之TFTs、包括非結晶形矽TFTs及多晶矽TFTs的缺點係在製造那些裝置中需要一高溫製程,這使得其難以在塑膠板、薄膜、或其他類似基板上形成該TFTs。The disadvantages of previously developed TFTs, including amorphous germanium TFTs and polycrystalline germanium TFTs, require a high temperature process in the fabrication of those devices which makes it difficult to form the TFTs on plastic sheets, films, or other similar substrates.
同時,彈性顯示器之發展在近年已變得活躍的,其中一形成在樹脂基板、諸如聚合物板件或薄膜上之TFT具有LCD或OLED之驅動電路的作用。這吸引注意至有機半導體薄膜,其可在低溫被沈積,且具有導電性,當作一可被沈積在塑膠薄膜等上之材料。Meanwhile, development of an elastic display has become active in recent years, and one of the TFTs formed on a resin substrate such as a polymer plate member or a film has a function of a driving circuit of an LCD or an OLED. This attracts attention to an organic semiconductor film which can be deposited at a low temperature and which is electrically conductive as a material which can be deposited on a plastic film or the like.
稠五苯係一有機半導體薄膜之範例,且其研究及發展被推進。其已被報告該稠五苯之載子移動率係約0.5 cm2 /Vs,其係等同於非結晶形矽TFTs之載子移動率。An example of a pentacene-based organic semiconductor film, and its research and development has been advanced. It has been reported that the carrier mobility of the pentacene is about 0.5 cm 2 /Vs, which is equivalent to the carrier mobility of amorphous 矽 TFTs.
然而,稠五苯及其他有機半導體具有於熱穩定性為低(<攝氏150度)之問題,且於生產一可用於實際使用之裝置中不會成功。However, pentacene and other organic semiconductors have problems of low thermal stability (<150 degrees Celsius) and are not successful in producing a device that can be used in practice.
近來已吸引注意而如適用於TFT之通道層的另一材料係氧化物材料。譬如,用作一具有ZnO當作主要成份之透明傳導性氧化物多晶矽薄膜的通道層之TFTs被主動地開發。此薄膜可為在相當低溫沈積,且形成在塑膠板、薄膜、或其他類似樹脂基板上。然而,大致上,具有ZnO當作主要成份之化合物不能在室溫形成一穩定之非結晶形相,且代替地形成一多晶矽相,其在該多晶晶粒邊界造成電子散射及使得其難以增加該電子移動率。此外,此一多晶化合物之電性質被多晶晶粒之形狀及互連所大幅地影響,其能視而一薄膜沈積條件之製造製程等定,且因此於一些案例中,結果之TET裝置具有變動的特徵。Another material that has recently attracted attention as applied to the channel layer of the TFT is an oxide material. For example, TFTs used as a channel layer of a transparent conductive oxide polysilicon film having ZnO as a main component are actively developed. The film can be deposited at relatively low temperatures and formed on a plastic sheet, film, or other similar resin substrate. However, in general, a compound having ZnO as a main component cannot form a stable amorphous phase at room temperature, and instead forms a polycrystalline germanium phase, which causes electron scattering at the polycrystalline grain boundary and makes it difficult to increase the Electronic mobility. In addition, the electrical properties of the polycrystalline compound are greatly affected by the shape and interconnection of the polycrystalline grains, which can be determined by the manufacturing process of a thin film deposition condition, and thus in some cases, the resulting TET device Has a changing feature.
關於此間題,使用以銦-鎵-鋅-氧為基礎之非結晶形氧化物的薄膜電晶體已被報告於K.Nomura等人、自然第432冊、第488-492頁(2004-11)中。此電晶體能在室溫形成於塑膠或玻璃基板上。該電晶體亦在大約6至9之場效移動率達成一常閉電晶體之特徵。另一有利之特徵係該電晶體相對於可見光為透明的。特別地是,該前述文件敘述一使用非結晶形氧化物之技術,該氧化物具有用於TFT之通道層的銦:鎵:鋅=1.1:1.1:0.9(原子比)之成份比率。Regarding this issue, a thin film transistor using an amorphous oxide based on indium-gallium-zinc-oxygen has been reported in K. Nomura et al., Nature 432, pp. 488-492 (2004-11). in. The transistor can be formed on a plastic or glass substrate at room temperature. The transistor also features a normally closed transistor at a field effect mobility of about 6 to 9. Another advantageous feature is that the transistor is transparent to visible light. In particular, the foregoing document describes a technique using an amorphous oxide having a composition ratio of indium:gallium:zinc = 1.1:1.1:0.9 (atomic ratio) for the channel layer of the TFT.
雖然使用三種金屬元素銦、鎵及鋅之非結晶形氧化物係在該前述文件中被採用,以成份控制及材料調整之容易性的觀點,使用較少種金屬元素係較佳的。Although amorphous metal oxides using three metal elements of indium, gallium, and zinc are employed in the foregoing documents, it is preferred to use a smaller number of metal elements from the viewpoint of composition control and ease of material adjustment.
在另一方面,當藉由濺鍍或類似方法所沈積時,使用一型式之金屬元素、諸如ZnO及In2 O3 之氧化物大致上形成多晶薄膜,且據此係極可能造成TFT裝置的特徵中之波動,如上面所述。On the other hand, when deposited by sputtering or the like, a polycrystalline film is formed substantially using a type of metal element such as ZnO and an oxide of In 2 O 3 , and accordingly, a TFT device is highly likely to be formed. Fluctuations in the characteristics, as described above.
由應用物理通信89,062103(2006年)中之報告已知在以銦-鋅-氧為基礎之非結晶形氧化物的研究結果,該氧化物當作使用二型式金屬元素之範例。然而,其已知當該氧化物被儲存於大氣中時,以銦-鋅-氧為基礎之非結晶形氧化物的電阻係數可被變化,且如此改善該環境係想要的。The results of studies on indium-zinc-oxygen-based amorphous oxides are known from the application of Physical Communication 89,062103 (2006) as an example of the use of a two-type metal element. However, it is known that when the oxide is stored in the atmosphere, the resistivity of the amorphous-based oxide based on indium-zinc-oxygen can be varied, and thus the environment is desired to be improved.
此外,在以銦-鋅-氧為基礎之非結晶形氧化物的研究結果已被報告在固態電子學、50(2006年)、第500-503頁中。於此報告中,施行攝氏500度之熱處理,且因此其想要的是在較低溫度製造一裝置。這是因為如果該裝置能在低溫被製成,一不貴之玻璃基板或樹脂基板能被使用。In addition, the results of studies on amorphous oxides based on indium-zinc-oxygen have been reported in Solid State Electronics, 50 (2006), pages 500-503. In this report, a heat treatment of 500 degrees Celsius is performed, and thus it is desirable to manufacture a device at a lower temperature. This is because if the device can be fabricated at a low temperature, an inexpensive glass substrate or resin substrate can be used.
因此,在該薄膜電晶體之領域中,一包括較少種金屬元素及具有優異之穩定性的非結晶形氧化物係想要的。Therefore, in the field of the thin film transistor, a non-crystalline oxide which includes a small number of metal elements and has excellent stability is desired.
本發明基於上面論及之問題被完成,且本發明之一目的係提供一場效電晶體,其使用一非結晶形氧化物,該氧化物所包括之元素種類少,且呈現一較大之開關比。再者,本發明之另一目的係提供一場效電晶體,其對於大氣中之儲存具有一優異之環境穩定性。The present invention has been accomplished on the basis of the above-discussed problems, and an object of the present invention is to provide a field effect transistor which uses an amorphous oxide which includes a small number of elements and exhibits a large switch ratio. Furthermore, another object of the present invention is to provide a potent transistor having an excellent environmental stability for storage in the atmosphere.
根據本發明之場效電晶體包括至少一通道層、一閘極絕緣層、一源極電極、一汲極電極、及一閘極電極,它們被形成在一基板上,其中該通道層係由包含至少銦及硼之非結晶形氧化物材料所製成,且其中該非結晶形氧化物材料具有元素比率B/(In+B)係0.05或較高及0.29或較低。The field effect transistor according to the present invention comprises at least one channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, which are formed on a substrate, wherein the channel layer is An amorphous oxide material comprising at least indium and boron, and wherein the amorphous oxide material has an elemental ratio B/(In+B) of 0.05 or higher and 0.29 or lower.
再者,根據本發明之場效電晶體包括至少一通道層、一閘極絕緣層、一源極電極、一汲極電極、及一閘極電極,它們被形成在一基板上,其中該通道層係由包含至少銦、鋅及硼之非結晶形氧化物材料所製成,且其中該非結晶形氧化物材料具有元素比率B/(In+Zn+B)係0.05或較高及0.29或較低。Furthermore, the field effect transistor according to the present invention comprises at least one channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, which are formed on a substrate, wherein the channel The layer is made of an amorphous oxide material comprising at least indium, zinc and boron, and wherein the amorphous oxide material has an element ratio B/(In+Zn+B) of 0.05 or higher and 0.29 or more low.
再者,根據本發明之顯示器包括:該場效電晶體;及至少一像素裝置,其具有一與該場效電晶體的源極電極及汲極電極中之一者連接的電極。Furthermore, the display according to the present invention comprises: the field effect transistor; and at least one pixel device having an electrode connected to one of a source electrode and a drain electrode of the field effect transistor.
根據本發明,該通道層係由諸如包含銦及硼之非結晶形氧化物的新穎材料所製成,且因此能實現一呈現良好特徵之薄膜電晶體。特別地,本發明達成此一效果,使得包括該開關比及該S值之電晶體特徵係優異的,且環境穩定性係良好的。According to the present invention, the channel layer is made of a novel material such as an amorphous oxide containing indium and boron, and thus a thin film transistor exhibiting good characteristics can be realized. In particular, the present invention achieves such an effect that the transistor characteristics including the switching ratio and the S value are excellent, and the environmental stability is good.
敘述用於具體化本發明之示範具體實施例。The exemplary embodiments used to embody the invention are described.
本發明之發明家已認真地研究包含二型式金屬元素之氧化物材料,諸如包含銦(In)及硼(B)之氧化物,當作一薄膜電晶體之通道層的材料。圖2說明藉由濺鍍所形成之各種氧化物薄膜的電阻係數中之暫時性變化。於圖2中,在銦及另一金屬元素M之間,所使用之每一薄膜具有大約0.2的元素比率M/(In+M)。如由圖2變得明顯者,包含銦及鋅的氧化物(In-Zn-O)及包含銦及錫的氧化物(In-Sn-O)之每一個的電阻係數中之暫時性變化係大的。對比於此,其變得明顯的是包含銦及硼的氧化物(In-B-O)及包含銦及鎵的氧化物(In-Ga-O)之每一個的電阻係數中之暫時性變化幾乎不發生。該氧化物(In-B-O)於電性質中具有優異之環境穩定性,且如此係一想要之半導體材料。The inventors of the present invention have earnestly studied an oxide material comprising a two-type metal element, such as an oxide containing indium (In) and boron (B), as a material of a channel layer of a thin film transistor. Figure 2 illustrates the temporal variation in the resistivity of various oxide films formed by sputtering. In FIG. 2, between indium and another metal element M, each film used has an element ratio M/(In+M) of about 0.2. As is apparent from FIG. 2, a temporary change in the resistivity of each of the oxide containing indium and zinc (In-Zn-O) and the oxide containing indium and tin (In-Sn-O) is big. In contrast, it becomes apparent that the temporary change in the resistivity of each of the oxide containing indium and boron (In-BO) and the oxide containing indium and gallium (In-Ga-O) hardly occur. The oxide (In-B-O) has excellent environmental stability in electrical properties and is thus a desired semiconductor material.
其次,上述材料被用於通道,以製造薄膜電晶體之原型。於氧化物(In-Zn-O)及氧化物(In-Sn-O)之每一個的案例中,其係難以實現具有一開關比等於或大於五數量級之電晶體。對比於此,於該氧化物(In-B-O)之案例中,如由圖1中所說明之轉移特徵(Id-Vg曲線)可明顯知道,其係可能實現具有一開關比等於或大於十數量級之電晶體。Second, the above materials are used in the channels to make prototypes of thin film transistors. In the case of each of oxide (In-Zn-O) and oxide (In-Sn-O), it is difficult to realize a transistor having a switching ratio equal to or greater than five orders of magnitude. In contrast, in the case of the oxide (In-BO), as is apparent from the transfer characteristic (Id-Vg curve) illustrated in FIG. 1, it is possible to realize that the switching ratio is equal to or greater than ten orders of magnitude. The transistor.
圖3A及3B係圖解,其中當In-M-O(金屬元素M係該週期表之第III族元素)之氧化物被用於通道時,電晶體特徵每次係彼此比較。如圖3A所說明,包括一含有In-B-O之通道的薄膜電晶體(TFT)比包括一含有In-Ga-O之通道的TFT及包括一含有In-Al-O之通道的TFT呈現一較大之開關比。如在圖3B所說明,包括該含有In-B-O之通道的TFT比包括該含有In-Ga-O之通道的TFT及包括該含有In-Al-O之通道的TFT呈現一較小之S值。因此,使用該通道用之In-B-O的TFT呈現想要之電晶體特徵。3A and 3B are diagrams in which when the oxide of In-M-O (metal element M is a group III element of the periodic table) is used for the channel, the crystal characteristics are compared with each other each time. As illustrated in FIG. 3A, a thin film transistor (TFT) including a channel containing In-BO exhibits a comparison with a TFT including a channel containing In-Ga-O and a TFT including a channel containing In-Al-O. Big switch ratio. As illustrated in FIG. 3B, the TFT including the channel containing In-BO exhibits a smaller S value than the TFT including the channel containing the In-Ga-O and the TFT including the channel containing the In-Al-O. . Therefore, the TFT using the In-B-O for this channel exhibits the desired transistor characteristics.
其次,根據本發明的場效電晶體之具體實施例被詳細地敘述。Next, a specific embodiment of the field effect transistor according to the present invention will be described in detail.
首先,根據此具體實施例的場效電晶體之結構被敘述。First, the structure of the field effect transistor according to this embodiment is described.
圖8A、8B、及8C係橫截面視圖,說明根據此具體實施例之場效電晶體的結構範例。於圖8A、8B、及8C中,基板、通道層、閘極絕緣層、源極電極、汲極電極、及閘極電極分別被表示為參考數字10、11、12、13、14及15。8A, 8B, and 8C are cross-sectional views illustrating an example of the structure of a field effect transistor according to this embodiment. In FIGS. 8A, 8B, and 8C, the substrate, the channel layer, the gate insulating layer, the source electrode, the drain electrode, and the gate electrode are denoted by reference numerals 10, 11, 12, 13, 14, and 15, respectively.
根據此具體實施例之場效電晶體係三端子裝置,包括該閘極電極15、該源極電極13、及該汲極電極14。該場效電晶體具有一施加電壓Vg至該閘極電極、控制流經該通道層之電流Id、及切換該源極電極及該汲極電極間之電流Id的功能。The field effect transistor system three-terminal device according to this embodiment includes the gate electrode 15, the source electrode 13, and the drain electrode 14. The field effect transistor has a function of applying a voltage Vg to the gate electrode, controlling a current Id flowing through the channel layer, and switching a current Id between the source electrode and the drain electrode.
圖8A說明一頂部閘極結構之範例,其中該閘極絕緣層12及該閘極電極15被連續地形成在該半導體通道層11上。再者,圖8B說明一底部閘極結構之範例,其中該閘極絕緣層12及該半導體通道層11被連續地形成在該閘極電極15上。再者,圖8C說明該底部閘極電晶體的另一範例。於圖8C中,基板(n+ 矽基板,其兼作閘極電極)、絕緣層(SiO2 )、通道層(氧化物)、源極電極、及汲極電極被分別表示為參考數字21、22、25、23及24。FIG. 8A illustrates an example of a top gate structure in which the gate insulating layer 12 and the gate electrode 15 are continuously formed on the semiconductor channel layer 11. Furthermore, FIG. 8B illustrates an example of a bottom gate structure in which the gate insulating layer 12 and the semiconductor channel layer 11 are continuously formed on the gate electrode 15. Again, Figure 8C illustrates another example of the bottom gate transistor. In FIG. 8C, the substrate (n + germanium substrate, which also serves as the gate electrode), the insulating layer (SiO 2 ), the channel layer (oxide), the source electrode, and the drain electrode are denoted as reference numerals 21, 22, respectively. , 25, 23 and 24.
該場效電晶體之結構係不限於上面所論及的本發明中之結構,且任意之頂部/底部閘極結構或交錯/反向交錯結構可被使用。The structure of the field effect transistor is not limited to the structure of the present invention as discussed above, and any of the top/bottom gate structures or staggered/inverted staggered structures may be used.
其次更詳細地敘述構成此具體實施例之場效電晶體的零組件。Next, the components constituting the field effect transistor of this embodiment will be described in more detail.
如上面所述,此具體實施例之場效電晶體的特徵為將包含至少銦及硼之非結晶形氧化物使用於該通道層。包含銦及硼之非結晶形氧化物(In-B-O)及包含銦、硼及鋅之非結晶形氧化物(In-Zn-B-O)係特別想要的材料。包含銦、錫、及硼之非結晶形氧化物係同樣可採用的。As described above, the field effect transistor of this embodiment is characterized in that an amorphous oxide containing at least indium and boron is used for the channel layer. A non-crystalline oxide (In-B-O) containing indium and boron and a non-crystalline oxide (In-Zn-B-O) containing indium, boron and zinc are particularly desirable materials. Non-crystalline oxides containing indium, tin, and boron are also available.
於此具體實施例中,硼相對於該非結晶形氧化物中所包含之所有該等金屬元素的比率係等於或大於10原子%及等於或小於40原子%。對於所有該等元素,由In-B-O所製成之非結晶形氧化物包含最大數量之氧、第二最大數量之銦、及第三最大數量之硼。對於所有該等元素,由In-Zn-B-O所製成之非結晶形氧化物包含最大數量之氧、第二最大數量之鋅(或銦)、第三最大數量之銦(或鋅)、及第四最大數量之硼。In this embodiment, the ratio of boron to all of the metal elements contained in the amorphous oxide is equal to or greater than 10 atom% and equal to or less than 40 atom%. For all of these elements, the amorphous oxide made from In-B-O comprises a maximum amount of oxygen, a second maximum amount of indium, and a third maximum amount of boron. For all of these elements, the amorphous oxide made of In-Zn-BO comprises a maximum amount of oxygen, a second maximum amount of zinc (or indium), a third maximum amount of indium (or zinc), and The fourth largest amount of boron.
使用包含用於該通道層之銦及硼的非結晶形氧化物,本發明之發明家在該薄膜電晶體上之認真研究期間找出以下者。亦即,當具有特定之元素比率B/(In+B)的氧化物半導體係施加至該通道時,一呈現想要之特徵的電晶體能被實現。Using the amorphous oxide comprising indium and boron for the channel layer, the inventors of the present invention identified the following during the careful study of the thin film transistor. That is, when an oxide semiconductor system having a specific element ratio B/(In+B) is applied to the channel, a transistor exhibiting a desired feature can be realized.
在對於薄膜電晶體之通道採用In-B-O中,有一較佳之銦及硼元素比率。該較佳之元素比率B/(In+B)係0.05(5原子%)或較高,因為,在此元素比率,非結晶形薄膜能藉由濺射沈積所獲得,使該基板溫度被保持在室溫。這是因為如上面所述,該多晶相造成TFT裝置的特徵中之波動,其中多晶晶粒之形狀及互連係視薄膜沈積方法而大幅地變化。In the use of In-B-O for the channel of the thin film transistor, there is a preferred ratio of indium to boron. The preferred element ratio B/(In+B) is 0.05 (5 atom%) or higher because, at this element ratio, the amorphous film can be obtained by sputter deposition, so that the substrate temperature is maintained at Room temperature. This is because, as described above, the polycrystalline phase causes fluctuations in the characteristics of the TFT device, in which the shape and interconnection of the polycrystalline grains largely vary depending on the film deposition method.
圖5係一曲線圖,說明當一使用In-B-O薄膜之場效電晶體被製成時,該元素比率B/(In+B)上之場效移動率的相依之範例。如由圖5變得明顯者,當硼之含量減少時,該場效移動率變得較大。該場效移動率之所需值視該場效電晶體之使用而定。譬如,一電泳顯示器可被具有大約0.05cm2 /Vs之場效移動率的TFT所驅動。液晶顯示器可被具有大約0.1cm2 /Vs之場效移動率的TFT所驅動。於一有機EL顯示器中,一想要之場效移動率係等於或大於1cm2 /Vs。由此觀點,銦及硼間之元素比率B/(In+B)係想要地等於或小於0.29、更想要地係等於或小於0.22、及最想要地係等於或小於0.2。Fig. 5 is a graph showing an example of the dependence of the field effect mobility ratio on the element ratio B/(In+B) when a field effect transistor using an In-BO film is fabricated. As is apparent from Fig. 5, when the content of boron is decreased, the field effect mobility becomes large. The required value of the field effect mobility depends on the use of the field effect transistor. For example, an electrophoretic display can be driven by a TFT having a field effect mobility of about 0.05 cm 2 /Vs. The liquid crystal display can be driven by a TFT having a field effect mobility of about 0.1 cm 2 /Vs. In an organic EL display, a desired field effect mobility is equal to or greater than 1 cm 2 /Vs. From this point of view, the element ratio B/(In+B) between indium and boron is desirably equal to or less than 0.29, more desirably equal to or less than 0.22, and most desirably equal to or less than 0.2.
圖6係一曲線圖,說明藉由研究以In-B-O為基礎之場效電晶體的閾值電壓之成份相依所獲得之結果。當該以In-B-O為基礎之場效電晶體的閾值電壓Vth係等於或大於0伏特時,一電路被輕易地建立。如在圖6所說明,該元素比率B/(In+B)想要地係等於或大於0.1,因為該閾值電壓Vth於此案例中係正的。Figure 6 is a graph showing the results obtained by studying the compositional dependence of the threshold voltage of a field effect transistor based on In-B-O. When the threshold voltage Vth of the field effect transistor based on In-B-O is equal to or greater than 0 volt, a circuit is easily established. As illustrated in FIG. 6, the element ratio B/(In+B) is desirably equal to or greater than 0.1 because the threshold voltage Vth is positive in this case.
圖7係一曲線圖,說明藉由研究以In-B-O為基礎之場效電晶體的電晶體特徵所獲得之結果。如在圖7所說明,當該元素比率B/(In+B)被設定至一等於或大於0.12及等於或小於0.2之值時,具有較小S值之電晶體能被實現。Figure 7 is a graph illustrating the results obtained by studying the crystal characteristics of a field effect transistor based on In-B-O. As illustrated in FIG. 7, when the element ratio B/(In+B) is set to a value equal to or greater than 0.12 and equal to or less than 0.2, a transistor having a smaller S value can be realized.
其由上面得出以下結論,即在對於場效電晶體之通道層採用In-B-O中,銦及硼間之元素比率B/(In+B)想要地係0.05或較高及0.29或較低、更想要地係0.1或較高及0.22或較低、且最想要地係0.12或較高及0.2或較低。It concludes from the above that in the case of using In-BO for the channel layer of the field effect transistor, the element ratio B/(In+B) between indium and boron is desired to be 0.05 or higher and 0.29 or more. Low, more desirable is 0.1 or higher and 0.22 or lower, and most desirably 0.12 or higher and 0.2 or lower.
此具體實施例中之氧化物(通道層)的厚度想要地係等於或大於10奈米及等於或小於200奈米,更想要地係等於或大於20奈米及等於或小於70奈米、且最想要地係等於或大於25奈米及等於或小於40奈米。The thickness of the oxide (channel layer) in this embodiment is desirably equal to or greater than 10 nm and equal to or less than 200 nm, more desirably equal to or greater than 20 nm and equal to or less than 70 nm. And the most desirable ground is equal to or greater than 25 nm and equal to or less than 40 nm.
再者,為了獲得優異之TFT特徵,用作該通道層的非結晶形氧化物薄膜之導電性想要地係設定至0.000001S/cm或更多及10S/cm或更少。當該導電性係大於10S/cm時,其係難以獲得一常閉電晶體及增加該開關比。於極端之案例中,閘極電壓之施加無法打開/關閉該源極及汲極電極間之電流,且該TFT不會用作一電晶體。在另一方面,當該導電性係比0.000001S/cm較小時,造成該氧化物薄膜為一絕緣體,其係難以增加該開啟電流。於極端之案例中,閘極電壓之施加無法打開/關閉該源極及汲極電極間之電流,且該TFT不會用作一電晶體。Further, in order to obtain excellent TFT characteristics, the conductivity of the amorphous oxide film used as the channel layer is desirably set to 0.000001 S/cm or more and 10 S/cm or less. When the conductivity is greater than 10 S/cm, it is difficult to obtain a normally closed transistor and increase the switching ratio. In an extreme case, the application of the gate voltage cannot open/close the current between the source and the drain electrode, and the TFT does not function as a transistor. On the other hand, when the conductivity is smaller than 0.000001 S/cm, the oxide film is caused to be an insulator, which is difficult to increase the on current. In an extreme case, the application of the gate voltage cannot open/close the current between the source and the drain electrode, and the TFT does not function as a transistor.
雖然該通道層之材料成份係亦獲得該前述導電性之想要範圍的一因素,該非結晶形氧化物薄膜想要地具有大約1014 至1018 /cm3 之電子載子濃度。Although the material composition of the channel layer also obtains a factor of the desired range of the aforementioned conductivity, the amorphous oxide film desirably has an electron carrier concentration of about 10 14 to 10 18 /cm 3 .
基於金屬元素之成份比率、於薄膜沈積期間之氧分壓、及在薄膜形成之後的退火條件,施加至該通道層之氧化物的導電性能被控制。圖11係一曲線圖,說明In-B-O半導體薄膜的電阻係數與元素比率B/(In+B)之相關性。其變得明顯的是當該元素比率B/(In+B)增加時,該導電性變得較小(其電阻係數變得較大)。控制薄膜沈積期間之氧分壓,以主要地控制該氧化物半導體薄膜中之氧不足量,藉此該電子載子濃度能被控制。圖11說明在不同氧分壓藉由濺鍍所沈積之薄膜的導電性。其變得明顯的是當於薄膜沈積期間之氧分壓增加時,該導電性變得較小。The conductivity of the oxide applied to the channel layer is controlled based on the composition ratio of the metal element, the oxygen partial pressure during film deposition, and the annealing conditions after the film formation. Figure 11 is a graph showing the dependence of the resistivity of the In-B-O semiconductor film on the element ratio B / (In + B). It becomes apparent that when the element ratio B/(In+B) is increased, the conductivity becomes smaller (the resistivity thereof becomes larger). The oxygen partial pressure during film deposition is controlled to mainly control the oxygen deficiency in the oxide semiconductor film, whereby the electron carrier concentration can be controlled. Figure 11 illustrates the conductivity of a film deposited by sputtering at different oxygen partial pressures. It becomes apparent that the conductivity becomes smaller as the oxygen partial pressure during film deposition increases.
如上面所述,該導電性能基於該等薄膜沈積條件被控制至某種程度。然而,對於控制該導電性有限制,視該元素比率B/(In+B)而定。譬如,當該元素比率B/(In+B)係等於或大於0.4時,該薄膜大體上變成一絕緣體,而不會視薄膜沈積期間之氧分壓而定。於一案例中,在此該元素比率B/(In+B)係等於或小於0.1,甚至當於薄膜沈積期間之氧分壓增加時,其係難以將具有該導電性之半導體薄膜形成至一等於或小於1S/cm之值。As described above, the electrical conductivity is controlled to some extent based on the film deposition conditions. However, there is a limit to controlling the conductivity, depending on the element ratio B/(In+B). For example, when the element ratio B/(In+B) is equal to or greater than 0.4, the film becomes substantially an insulator irrespective of the oxygen partial pressure during film deposition. In one case, the element ratio B/(In+B) is equal to or less than 0.1, and even when the oxygen partial pressure during film deposition increases, it is difficult to form a semiconductor film having the conductivity to one. A value equal to or less than 1 S/cm.
於此具體實施例中,除了銦、硼、及氧以外,不可避免地包含之元素或具有不利地影響該等特徵之含量的元素被允許當作該非結晶形氧化物中所包含之元素。In this embodiment, elements inevitably contained or elements having a content adversely affecting the characteristics other than indium, boron, and oxygen are allowed to be regarded as elements contained in the amorphous oxide.
該閘極絕緣層12之材料係未特別限制,只要該材料具有優異之絕緣特性。然而,其想要的是使用一主要成分為矽之薄膜,因為優異之電晶體特徵。雖然其未十分清楚為什麼該等特徵變得優異,該理由被考慮為一優異之介面可被形成於包含硼的通道層及主要成分為矽的閘極絕緣層之間。The material of the gate insulating layer 12 is not particularly limited as long as the material has excellent insulating properties. However, what it wants is to use a film whose main component is ruthenium because of its excellent crystal characteristics. Although it is not fully understood why these features become excellent, the reason is considered to be that an excellent interface can be formed between the channel layer containing boron and the gate insulating layer whose main component is germanium.
特別地是,其主要成分為矽的材料之想要範例包括矽氧化物SiOx 、矽氮化物SiNx 、及矽氧氮化物SiOx Ny 。此外,Si-B-O、Si-Hf-O、Si-Al-O或Si-Y-O能被用作一複合之氧化物,其主要成分為矽。In particular, desirable examples of materials whose main component is niobium include niobium oxide SiO x , niobium nitride SiN x , and niobium oxynitride SiO x N y . Further, Si-BO, Si-Hf-O, Si-Al-O or Si-YO can be used as a composite oxide whose main component is ruthenium.
藉由採用一具有優異之絕緣特性的薄膜,如上面所述,在該源極及閘極電極之間與在該汲極及閘極電極之間,該漏洩電流能被減少至大約10-11 安培。By using a film having excellent insulating properties, as described above, the leakage current can be reduced to between about 10 and 11 between the source and gate electrodes and between the drain and gate electrodes. ampere.
該閘極絕緣層之厚度係譬如大約50至300奈米。The thickness of the gate insulating layer is, for example, about 50 to 300 nm.
該源極電極13、該汲極電極14、及該閘極電極15之每一材料係未特別限制,只要優異之導電性能被獲得,且至該通道層之電連接係可能的。Each of the source electrode 13, the drain electrode 14, and the gate electrode 15 is not particularly limited as long as excellent electrical conductivity is obtained, and electrical connection to the channel layer is possible.
譬如,譬如In2 O3 :Sn或ZnO之透明傳導性薄膜、或譬如金、鎳、鎢、鉬、銀、或鉑之金屬電極能被使用。任何包括金-鈦分層結構之層狀結構係亦可採用的。For example, a transparent conductive film such as In 2 O 3 :Sn or ZnO, or a metal electrode such as gold, nickel, tungsten, molybdenum, silver, or platinum can be used. Any layered structure including a gold-titanium layered structure may also be employed.
當作該基板10,玻璃基板、塑膠基板、塑膠薄膜等可被使用。As the substrate 10, a glass substrate, a plastic substrate, a plastic film, or the like can be used.
該前述之通道層及該閘極絕緣層相對於可見光係透明的,且因此其係可能藉由使用透明材料當作該等前述電極及基板之每一材料獲得一透明之場效電晶體。The aforementioned channel layer and the gate insulating layer are transparent with respect to visible light, and thus it is possible to obtain a transparent field effect transistor by using a transparent material as each of the foregoing electrodes and substrates.
當作一沈積該等前述氧化物薄膜之方法,提供有一氣相製程,諸如濺鍍方法(SP方法)、脈衝雷射沈積方法(PLD方法)、及電子束沈積方法。應注意的是在該等氣相製程之中,該濺鍍方法由生產力之觀點係合適的。然而,該薄膜沈積方法係不限於那些方法。再者,該基板於薄膜沈積期間之溫度能夠被維持在一狀態中,在此該基板未被有意地加熱,換句話說,在室溫。據此,此方法能於一低溫製程期間被執行,且因此該場效電晶體能形成在該基板、諸如塑膠板或箔材上。As a method of depositing the foregoing oxide thin films, a vapor phase process such as a sputtering method (SP method), a pulsed laser deposition method (PLD method), and an electron beam deposition method are provided. It should be noted that in these vapor phase processes, the sputtering method is suitable from the viewpoint of productivity. However, the film deposition method is not limited to those methods. Furthermore, the temperature of the substrate during film deposition can be maintained in a state where the substrate is not intentionally heated, in other words, at room temperature. Accordingly, the method can be performed during a low temperature process, and thus the field effect transistor can be formed on the substrate, such as a plastic sheet or foil.
下文,參考圖9A及9B,此具體實施例之場效電晶體的特徵被敘述。Hereinafter, with reference to Figures 9A and 9B, the features of the field effect transistor of this embodiment are described.
圖9A說明在各種閘極電壓Vg所獲得之Id-Vd特徵的範例,且圖9B說明當Vd=6V時之Id-Vg特徵(轉移特徵)的範例。該電晶體的特徵中之差異能被表示為場效移動率μ、閾值電壓(Vth)、開關比、及S值中之差異。FIG. 9A illustrates an example of Id-Vd characteristics obtained at various gate voltages Vg, and FIG. 9B illustrates an example of Id-Vg characteristics (transfer characteristics) when Vd=6V. The difference in the characteristics of the transistor can be expressed as the difference in field effect mobility μ, threshold voltage (Vth), switching ratio, and S value.
該場效移動率可為由一線性區域或一飽和區域之特徵所獲得。譬如,其係可能採用建立一曲線圖之方法,該曲線圖代表來自該等轉移特徵之結果的Id1/2 -Vg,以便由該曲線圖之斜率獲得該場效移動率。於本發明之敘述中,除非以別的方式指明,藉由該方法施行評估。The field effect mobility can be obtained from features of a linear region or a saturated region. For example, it is possible to use a method of creating a graph representing Id 1/2 -Vg from the results of the transition features in order to obtain the field effect mobility from the slope of the graph. In the context of the present invention, evaluation is performed by this method unless otherwise indicated.
雖然提供有獲得該閾值之一些方法,該閾值電壓Vth可為由譬如代表Id1/2 -Vg之曲線的x截距所獲得。While some methods of obtaining the threshold are provided, the threshold voltage Vth can be obtained from an x-thick such as a curve representing Id 1/2 - Vg.
該開關比能由該等轉移特徵中之最大Id值對該Id最小值的比率所獲得。The switch ratio is obtained from the ratio of the maximum Id value of the transfer characteristics to the minimum value of Id.
該S值能代表Log(Id)-Vg之曲線圖的傾度之倒數所獲得,該曲線圖係由該等轉移特徵之結果所建立。The S value can be obtained by reciprocal of the inclination of the graph of Log(Id)-Vg, which is established from the results of the transfer characteristics.
該等電晶體特徵中之差異係不限於上面者,但亦可藉由各種參數所代表。The difference in the characteristics of the transistors is not limited to the above, but can also be represented by various parameters.
像主動式矩陣基板之半導體裝置係設有根據此具體實施例之場效電晶體,如上面所述。一透明之半導體裝置係設有一透明之基板及透明之非結晶形氧化物TFTs。因此,當該透明之主動式矩陣基板被應用至一顯示器時,該顯示器之孔徑比可增加。特別地,當該主動式矩陣基板用於一有機EL顯示器時,一由該基板側面(底部放射)放射光線之結構能被使用。設有依據此具體實施例之場效電晶體的主動式矩陣基板可使用於譬如ID標籤或IC標籤之各種應用。A semiconductor device like an active matrix substrate is provided with a field effect transistor according to this embodiment, as described above. A transparent semiconductor device is provided with a transparent substrate and transparent amorphous oxide TFTs. Therefore, when the transparent active matrix substrate is applied to a display, the aperture ratio of the display can be increased. In particular, when the active matrix substrate is used for an organic EL display, a structure in which light is radiated from the side (bottom of the substrate) can be used. An active matrix substrate provided with a field effect transistor in accordance with this embodiment can be used in a variety of applications such as ID tags or IC tags.
下文,一顯示器被特別詳細地敘述當作設有依據此具體實施例之場效電晶體的主動式矩陣基板之範例。Hereinafter, a display is specifically described as an example of an active matrix substrate provided with a field effect transistor according to this embodiment.
一作為依據此具體實施例的場效電晶體之輸出端子的汲極電極係與一像素裝置之電極連接,諸如有機或無機之電致發光(EL)裝置或液晶裝置,藉此該顯示器能被製成。下文,該顯示器的一特定結構範例係參考說明該顯示器之橫截面視圖敘述。A drain electrode as an output terminal of a field effect transistor according to this embodiment is connected to an electrode of a pixel device, such as an organic or inorganic electroluminescence (EL) device or a liquid crystal device, whereby the display can be production. Hereinafter, a specific structural example of the display is described with reference to a cross-sectional view of the display.
譬如,如在圖12所說明,場效電晶體係形成在一基底111上。該場效電晶體包括通道層112、源極電極113、汲極電極114、閘極絕緣層115、及閘極電極116。該汲極電極114係經過層間絕緣層117與一電極118連接。該電極118被帶入與一發光層119造成接觸。該發光層119被帶入與一電極120造成接觸。根據如上面所述之此一結構,注射至該發光層119之電流能基於該電流值被控制,該電流經過該通道層112中所形成之通道由該源極電極113流動至該汲極電極114。因此,該電流能基於該場效電晶體的閘極電極116之電壓被控制。該電極118、該發光層119、及該電極120具有無機或有機電致發光裝置之作用。For example, as illustrated in Figure 12, a field effect transistor system is formed on a substrate 111. The field effect transistor includes a channel layer 112, a source electrode 113, a drain electrode 114, a gate insulating layer 115, and a gate electrode 116. The drain electrode 114 is connected to an electrode 118 via an interlayer insulating layer 117. The electrode 118 is brought into contact with a light-emitting layer 119. The luminescent layer 119 is brought into contact with an electrode 120. According to the structure as described above, the current injected into the light-emitting layer 119 can be controlled based on the current value flowing from the source electrode 113 to the drain electrode through the channel formed in the channel layer 112. 114. Therefore, the current can be controlled based on the voltage of the gate electrode 116 of the field effect transistor. The electrode 118, the light-emitting layer 119, and the electrode 120 function as inorganic or organic electroluminescent devices.
如在圖13所說明,結構能被採用,其中該汲極電極114被延伸至亦具有該電極118之作用,且如此用作該電極118,用於施加一電壓至藉由該高電阻薄膜121及122所夾住之液晶胞元或電泳微粒胞元123。該液晶胞元或電泳微粒胞元123、該高電阻薄膜121及122、與該等電極118及120構成一像素裝置。施加至該像素裝置之電壓能基於該電流之值被控制,該電流經過該通道層112中所形成之通道由該源極電極113流動至該汲極電極114。因此,該電流能基於該TFT的閘極電極116之電壓被控制。當該像素裝置之顯示媒介係一膠囊,其中一流體及微粒被密封在一絕緣包覆料內,該高電阻薄膜121及122係不需要的。As illustrated in FIG. 13, a structure can be employed in which the drain electrode 114 is extended to also function as the electrode 118 and is used as the electrode 118 for applying a voltage to the high resistance film 121. And 122 liquid crystal cells or electrophoretic particle cells 123 sandwiched. The liquid crystal cell or electrophoretic particle cell 123, the high resistance films 121 and 122, and the electrodes 118 and 120 constitute a pixel device. The voltage applied to the pixel device can be controlled based on the value of the current flowing from the source electrode 113 to the drain electrode 114 through the channel formed in the channel layer 112. Therefore, the current can be controlled based on the voltage of the gate electrode 116 of the TFT. When the display medium of the pixel device is a capsule in which a fluid and particles are sealed in an insulating coating, the high resistance films 121 and 122 are not required.
於上述二範例之每一個中,該薄膜電晶體典型具有交錯的結構(頂部閘極型)。然而,本發明不須被限制於上述之此一結構。譬如,當作為該薄膜電晶體之輸出端子的汲極電極及該像素裝置被連接,以便在位相上為完全相同時,諸如共面型式之另一結構能被採用。In each of the above two examples, the thin film transistor typically has a staggered structure (top gate type). However, the present invention is not necessarily limited to the above structure. For example, when the gate electrode as the output terminal of the thin film transistor and the pixel device are connected so as to be identical in phase, another structure such as a coplanar type can be employed.
於上述二範例之每一個中,用於驅動該像素裝置之該對電極係提供平行於該基底。然而,本發明不須被限制於上述之此一結構。譬如,當作為該薄膜電晶體之輸出端子的汲極電極及該像素裝置被連接,以便在位相上為完全相同時,該等電極之任一電極或該二電極可被提供垂直於該基底。In each of the above two examples, the pair of electrodes for driving the pixel device are provided parallel to the substrate. However, the present invention is not necessarily limited to the above structure. For example, when the drain electrode as the output terminal of the thin film transistor and the pixel device are connected so as to be completely identical in phase, any one or both of the electrodes may be provided perpendicular to the substrate.
於用於驅動該像素裝置之該對電極被提供於平行於該基底的案例中,當該像素裝置係一EL裝置或一反射型像素裝置、諸如一反射型液晶裝置時,該等電極之任一電極係需要相對於一光線放射波長或反射光之波長為透明的。當該像素裝置係一透射型像素裝置、諸如透射型液晶裝置時,該等電極兩者係需要相對於透射光為透明的。In the case where the pair of electrodes for driving the pixel device are provided in parallel to the substrate, when the pixel device is an EL device or a reflective pixel device, such as a reflective liquid crystal device, An electrode system needs to be transparent with respect to a wavelength of light emitted or a wavelength of reflected light. When the pixel device is a transmissive pixel device, such as a transmissive liquid crystal device, both of the electrodes need to be transparent with respect to the transmitted light.
依據此具體實施例之薄膜電晶體能包括所有透明之構成元件,且因此一透明之顯示器能被形成。該顯示器亦可被設在一低熱阻之基底上,諸如一塑膠基板,其係重量輕、彈性、透明的。The thin film transistor according to this embodiment can include all of the transparent constituent elements, and thus a transparent display can be formed. The display can also be placed on a low thermal resistance substrate, such as a plastic substrate, which is lightweight, flexible, and transparent.
其次,參考圖14,敘述一顯示器,其中二維地配置多數像素,每一像素包括一EL元件(在此具體實施例中為有機EL元件)及一場效電晶體。Next, referring to Fig. 14, a display in which a plurality of pixels are two-dimensionally arranged, each of which includes an EL element (in this embodiment, an organic EL element) and a field effect transistor.
圖14說明一用於驅動有機EL層204之電晶體201及一用於進行像素選擇之電晶體202。提供一電容器203,以保有被選擇之條件及儲存共用電極線207與該電晶體202的源極部份間之電荷,藉此保有該電晶體201之閘極信號。藉由掃描電極線205及一信號電極線206決定一待選擇之像素。Figure 14 illustrates a transistor 201 for driving the organic EL layer 204 and a transistor 202 for pixel selection. A capacitor 203 is provided to maintain the selected conditions and to store the charge between the common electrode line 207 and the source portion of the transistor 202, thereby maintaining the gate signal of the transistor 201. A pixel to be selected is determined by the scan electrode line 205 and a signal electrode line 206.
更特別地,一影像信號被應用當作一經過該掃描電極線205由驅動器電路(未示出)至該閘極電極之脈衝信號。同時,一脈衝信號係由另一驅動器電路(未示出)經過該信號電極線206施加至該電晶體202,以選擇該像素。在此時,該電晶體202被打開,藉此電荷被儲存於坐落在該信號電極線206及該電晶體202的源極部份間之電容器203中。然後,該電晶體201之閘極電壓被保持至一想要之電壓,以打開該電晶體201。維持此狀態,直至下一信號被接收。於該狀態期間,其中該電晶體201被打開,一電壓及一電流被連續地供給至該有機EL層204,藉此維持光放射。More specifically, an image signal is applied as a pulse signal from the driver circuit (not shown) to the gate electrode through the scan electrode line 205. At the same time, a pulse signal is applied to the transistor 202 via the signal electrode line 206 by another driver circuit (not shown) to select the pixel. At this time, the transistor 202 is turned on, whereby the charge is stored in the capacitor 203 between the signal electrode line 206 and the source portion of the transistor 202. Then, the gate voltage of the transistor 201 is maintained to a desired voltage to turn on the transistor 201. This state is maintained until the next signal is received. During this state, in which the transistor 201 is turned on, a voltage and a current are continuously supplied to the organic EL layer 204, thereby maintaining light emission.
圖14說明該結構性範例,其中每一像素包括二電晶體及一電容器。但為了改善該性能,譬如,較大數目之電晶體可被併入在每一像素中。Figure 14 illustrates this structural example in which each pixel includes a di-electrode and a capacitor. However, to improve this performance, for example, a larger number of transistors can be incorporated in each pixel.
下面所敘述者係本發明之範例。然而,本發明係不限於以下之範例。The following description is an example of the invention. However, the present invention is not limited to the following examples.
於此範例中,圖8A所說明之頂部閘極TFT裝置被製成具有一以In-B-O為基礎之非結晶形氧化物當作通道層。In this example, the top gate TFT device illustrated in FIG. 8A is formed to have a non-crystalline oxide based on In-B-O as a channel layer.
一以In-B-O為基礎之非結晶形氧化物薄膜首先被形成為一玻璃基板上之通道層(藉由康寧公司所製造之1737)。特別地是,該以In-B-O為基礎之非結晶形氧化物薄膜係在氬氣及氧氣之混合大氣中藉由射頻濺鍍法所形成。在此時,如圖10所說明之濺鍍沈積設備被使用。於圖10中,樣本、目標、真空泵、真空計、及基板夾具被分別表示為參考數字31、32、33、34、及35。為每一氣體導入系統提供一氣體流量控制器36。一壓力控制器及一薄膜沈積室被分別表示為參考數字37及38。該真空泵33係一排氣單元,用於抽空該薄膜沈積室38之內部。該基板夾具35係一用於保持該基板之單元,該氧化物薄膜將在該基板上形成於該薄膜沈積室內。該目標(固體材料來源)32被放置相向於該基板夾具。該沈積設備係另設有一能量來源(射頻電源)(未示出),用於造成該材料由該目標32蒸發;及一單元,用於供給氣體至該薄膜沈積室之內部。An amorphous oxide film based on In-B-O was first formed as a channel layer on a glass substrate (1737 manufactured by Corning Incorporated). In particular, the In-B-O-based amorphous oxide film is formed by a radio frequency sputtering method in a mixed atmosphere of argon gas and oxygen gas. At this time, a sputtering deposition apparatus as illustrated in FIG. 10 is used. In FIG. 10, the sample, the target, the vacuum pump, the vacuum gauge, and the substrate holder are denoted by reference numerals 31, 32, 33, 34, and 35, respectively. A gas flow controller 36 is provided for each gas introduction system. A pressure controller and a thin film deposition chamber are denoted by reference numerals 37 and 38, respectively. The vacuum pump 33 is an exhaust unit for evacuating the inside of the thin film deposition chamber 38. The substrate holder 35 is a unit for holding the substrate on which the oxide film is to be formed in the thin film deposition chamber. The target (solid material source) 32 is placed facing the substrate holder. The deposition apparatus is further provided with an energy source (RF power source) (not shown) for causing the material to evaporate from the target 32, and a unit for supplying gas to the interior of the film deposition chamber.
該沈積設備具有二氣體導入系統,一系統係用於氬,且另一系統係用於氬及氧之混合氣體(Ar:O2 =95:5)。以能夠使該設備個別地控制該各個氣體流量之氣體流量控制器36、及用於控制該排氣比率之壓力控制器37,一預定之氣體大氣能在該薄膜沈積室中被獲得。The deposition apparatus has a two gas introduction system, one system for argon and the other system for a mixed gas of argon and oxygen (Ar: O 2 = 95: 5). A predetermined gas atmosphere can be obtained in the film deposition chamber by a gas flow controller 36 capable of individually controlling the respective gas flow rates of the apparatus, and a pressure controller 37 for controlling the exhaust ratio.
於此範例中,當作一目標,In2 O3 及B2 O3 的2吋尺寸設計之目標被用於藉由同時濺鍍形成In-B-O薄膜。對於該個別之目標,該輸入RF功率係70瓦特及35瓦特。於該薄膜沈積期間之大氣被設定,使得該總壓力係0.4巴,且該氣體流量比率係Ar:O2 =100:1。該薄膜沈積比率及該基板溫度被分別設定至12奈米/分及攝氏25度。在該薄膜沈積之後,該薄膜係在攝氏300度於大氣中遭受一退火製程達60分鐘。In this example, as a goal, the target of the 2 吋 size design of In 2 O 3 and B 2 O 3 was used to form an In-BO film by simultaneous sputtering. For this individual target, the input RF power is 70 watts and 35 watts. The atmosphere during deposition of the film was set such that the total pressure was 0.4 bar and the gas flow ratio was Ar:O 2 = 100:1. The film deposition ratio and the substrate temperature were set to 12 nm/min and 25 degrees Celsius, respectively. After the film was deposited, the film was subjected to an annealing process at atmospheric pressure of 300 degrees Celsius for 60 minutes.
在該如此獲得薄膜之表面上施行切入射X射線繞射分析(薄膜方法,入射角:0.5度)。沒有明顯之繞射峰值被偵測,這指示所形成之以In-B-O為基礎的薄膜係一非結晶形薄膜。A cut-incident X-ray diffraction analysis was performed on the surface of the thus obtained film (film method, incident angle: 0.5 degree). No significant diffraction peaks were detected, indicating that the formed In-B-O based film was an amorphous film.
對於圖案分析進一步進行光譜橢圓光度法測量,以顯露該薄膜具有大約0.5奈米的根均方(Rrms)之粗糙度及大約30奈米之厚度。一感應地耦合電漿放射光譜方法(ICP方法)被使用於分析該金屬成份比率,以顯露該薄膜金屬成份比率為In:B=85:15。換句話說,其被發現該元素比率B/(In+B)是0.15。Spectral ellipsometry measurements were further performed on the pattern analysis to reveal that the film had a root mean square (Rrms) roughness of about 0.5 nm and a thickness of about 30 nm. An inductively coupled plasma emission spectrometry method (ICP method) is used to analyze the ratio of the metal components to reveal that the ratio of the metal composition of the film is In:B=85:15. In other words, it was found that the element ratio B/(In+B) was 0.15.
該導電性、該電子載子濃度、及該電子移動率被評估及分別估計為大約10-3 S/cm、2x1015 /cm3 、及大約4cm2 /Vs。The conductivity, the electron carrier concentration, and the electron mobility were evaluated and estimated to be about 10 -3 S/cm, 2 x 10 15 /cm 3 , and about 4 cm 2 /Vs, respectively.
該汲極電極14及該源極電極13係其次經過微影術及一光阻剝落方法形成及佈圖。該等電極之材料係一金-鈦分層薄膜。該金層之厚度係40奈米,且該鈦層之厚度係5奈米。The drain electrode 14 and the source electrode 13 are formed and patterned by lithography and a photoresist peeling method. The material of the electrodes is a gold-titanium layered film. The thickness of the gold layer is 40 nm, and the thickness of the titanium layer is 5 nm.
該閘極絕緣層12係其次經過微影術及一光阻剝落方法形成及佈圖。該閘極絕緣層12係一藉由濺射沈積法沈積至150奈米厚度之SiO2 薄膜。該SiO2 薄膜之特定介電常數係大約3.7。The gate insulating layer 12 is formed and patterned by lithography and a photoresist peeling method. The gate insulating layer 12 is deposited by sputtering deposition to a 150 nm thick SiO 2 film. The specific dielectric constant of the SiO 2 film is about 3.7.
該閘極電極15係亦經過微影術及一光阻剝落方法形成。該通道長度及該通道寬度分別係50微米及200微米。該電極之材料是金,且其厚度係30奈米。TFT係以上述方式製成。The gate electrode 15 is also formed by lithography and a photoresist peeling method. The length of the channel and the width of the channel are 50 microns and 200 microns, respectively. The material of the electrode is gold and its thickness is 30 nm. The TFT is fabricated in the above manner.
其次,該TFT之特徵被評估。Second, the characteristics of the TFT are evaluated.
圖9A及9B說明在室溫所測量之TFT的電流-電壓特徵之範例。圖9A說明Id-Vd特徵,反之圖9B說明Id-Vg特徵。於圖9A中,藉由Vd變化所造成的汲極電壓Vd上之源極-汲極電流Id的相依係在施加一恆定的閘極電壓Vg之下測量。如在圖9A所說明,大約Vd=6伏特觀察到飽和(夾止),其係一典型之半導體電晶體行為。TFT特徵係使得該閾值在Vd=6伏特係大約1.5伏特。在Vg=10伏特,流動Id=大約1.0x10-4 安培之電流。9A and 9B illustrate examples of current-voltage characteristics of TFTs measured at room temperature. Figure 9A illustrates the Id-Vd feature, whereas Figure 9B illustrates the Id-Vg feature. In FIG. 9A, the dependence of the source-drain current Id on the gate voltage Vd caused by the change in Vd is measured under application of a constant gate voltage Vg. As illustrated in Figure 9A, saturation (clamping) is observed at approximately Vd = 6 volts, which is a typical semiconductor transistor behavior. The TFT characteristics are such that the threshold is about 1.5 volts at Vd = 6 volts. At Vg = 10 volts, the flow Id = a current of approximately 1.0 x 10 -4 amps.
再者,該電晶體之開關比超過109 。於該飽和區域中,由輸出特徵所計算之場效移動率係大約2.5cm2 /Vs。Moreover, the switching ratio of the transistor exceeds 10 9 . In this saturated region, the field effect mobility calculated from the output characteristics is approximately 2.5 cm 2 /Vs.
在此範例中所製成之TFT具有優異之可重複性,且所製成之多數裝置中的特徵中之波動係小的。The TFTs produced in this example have excellent repeatability, and the fluctuations in the features in most of the devices produced are small.
如上面所述,當In-B-O之新穎的非結晶形氧化物被應用於該通道層時,優異之電晶體特徵可被實現。特別地是,有一優點,即構成元素之種類係比該傳統以In-Ga-Zn-O為基礎之氧化物較少。因此,其能被期待減少製造負載及製造成本。As described above, when a novel amorphous oxide of In-B-O is applied to the channel layer, excellent transistor characteristics can be realized. In particular, there is an advantage in that the type of constituent elements is less than the conventional oxide based on In-Ga-Zn-O. Therefore, it can be expected to reduce manufacturing load and manufacturing cost.
在此範例中,對於具有一包含銦及硼當作主要成份之通道層的薄膜電晶體檢查該In-B成份相依。In this example, the In-B composition is checked for a thin film transistor having a channel layer containing indium and boron as main components.
此範例採用一用於薄膜沈積之組合的方法,以便檢查該通道層之材料成份相依。亦即,使用一藉由濺鍍立刻在單一基板上形成具有各種成份的氧化物之薄膜的方法進行該檢查。然而,其係不需要應用此組合的技術。一想要成份之目標(材料來源)可被製備,以沈積用於每一成份之薄膜。具有各種成份之薄膜亦可藉由分開地控制用於多數目標之輸入功率所形成。This example uses a method for the combination of film deposition to check the material composition of the channel layer. That is, the inspection is performed by a method of forming a film of an oxide having various compositions on a single substrate by sputtering immediately. However, it does not require the technique of applying this combination. A desired ingredient (source of material) can be prepared to deposit a film for each component. Films having various compositions can also be formed by separately controlling the input power for most targets.
以三元切入射濺鍍設備之使用形成In-B-O薄膜。使該目標相對於該基板傾斜地定位,該基板表面上之薄膜的成份係由於離該目標的距離中之差異而變化。其結果是,能獲得一在該基板上具有寬廣之組成分層的薄膜。於形成該In-B-O薄膜中,In2 O3 之二目標及B2 O3 的一目標係同時地遭受濺鍍。該輸入RF功率被分別地設定至35瓦特及70瓦特。於該薄膜沈積期間之大氣被設定,使得該總壓力係0.35巴,且該氣體流量比率係Ar:O2 =100:1。該基板溫度被設定至攝氏25度。The In-BO film is formed by the use of a ternary cut incident sputtering apparatus. The target is positioned obliquely relative to the substrate, and the composition of the film on the surface of the substrate varies due to the difference in distance from the target. As a result, a film having a broad compositional layer on the substrate can be obtained. In forming the In-BO film, the target of In 2 O 3 and a target of B 2 O 3 are simultaneously subjected to sputtering. The input RF power is set to 35 watts and 70 watts, respectively. The atmosphere during the deposition of the film was set such that the total pressure was 0.35 bar and the gas flow ratio was Ar:O 2 = 100:1. The substrate temperature was set to 25 degrees Celsius.
該如此形成薄膜之物理性質係藉由發螢光的X射線分析、光譜橢圓光度法法、X射線繞射、及四點探測電阻係數測量所評估。再者,一組合的TFT函式庫(一基板上之具有各種通道成份的TFT)係藉由使用一In-B-O成份分級薄膜所製成。TFT結構係一底部閘極及頂部接觸型。The physical properties of the thus formed film are evaluated by fluorescing X-ray analysis, spectral ellipsometry, X-ray diffraction, and four-point detection resistivity measurement. Further, a combined TFT library (TFT having various channel components on a substrate) is formed by classifying a film using an In-B-O composition. The TFT structure is a bottom gate and a top contact type.
在該元素比率B/(In+B)係0.05或較高之區域中,其係經過X射線繞射(XRD)測量確認所形成之In-B-O薄膜係非結晶形。於部份薄膜區域中,其中該元素比率B/(In+B)係比0.05較小,觀察到該晶體之繞射峰值。由上面論及之結果可被下結論,即可藉由將In-B-O薄膜中之元素比率B/(In+B)設定至0.05或較高而獲得一非結晶形薄膜。In the region where the element ratio B/(In+B) is 0.05 or higher, it was confirmed by X-ray diffraction (XRD) measurement that the formed In-B-O film was amorphous. In the partial film region, in which the element ratio B/(In+B) is smaller than 0.05, the diffraction peak of the crystal is observed. From the results discussed above, it can be concluded that an amorphous film can be obtained by setting the element ratio B/(In+B) in the In-B-O film to 0.05 or higher.
該In-B-O成份分級薄膜之薄片電阻被四點探測方法所測量,且該薄膜之厚度被光譜橢圓光度法所測量,以便獲得該薄膜之電阻係數。其結果是,如在圖11所說明,其被確認該電阻係數隨著該元素比率B/(In+B)而改變,且該電阻被發現在富含銦之成份(該元素比率B/(In+B)為小之成份)上為低的,及在富含硼之成份(該元素比率B/(In+B)為大之成份)上為高的。The sheet resistance of the In-B-O composition graded film was measured by a four-point detection method, and the thickness of the film was measured by spectral ellipsometry to obtain the resistivity of the film. As a result, as explained in Fig. 11, it is confirmed that the resistivity changes with the element ratio B/(In+B), and the resistance is found in the indium-rich component (the element ratio B/( In+B) is low on the small component and high on the boron-rich component (the element ratio B/(In+B) is large).
再者,當該薄膜沈積大氣中之氧分壓已被改變時,獲得該In-B-O成份分級薄膜之電阻係數。其被發現如在圖11所說明,由於氧分壓中之增加,該In-B-O薄膜之電阻升高。這或許是由於氧不足之減少及該電子載子濃度之作為結果的降低。其亦被發現該電阻係適合用於該TFT主動層之成份範圍相對該氧分壓而改變。Further, when the partial pressure of oxygen in the film deposition atmosphere has been changed, the resistivity of the graded film of the In-B-O component is obtained. It was found that as illustrated in Fig. 11, the electric resistance of the In-B-O film was increased due to an increase in oxygen partial pressure. This may be due to a decrease in oxygen deficiency and a decrease in the concentration of the electron carrier. It has also been found that the resistance is suitable for the composition of the active layer of the TFT to vary with respect to the oxygen partial pressure.
圖15說明測量該In-B-O薄膜的電阻係數隨著時間變化之結果。遍及一寬廣之成份範圍(該元素比率B/(In+B)為0.05至0.5之範圍),在以該In-B-O為基礎之薄膜中觀察到電阻係數隨著時間無變化。再者,圖2說明在其他材料之中,電阻係數隨著時間中之變化的比較。以與In-B-O薄膜相同之方式形成的In-Zn-O薄膜及In-Sn-O薄膜呈現一趨勢,以隨著時間減少該電阻係數。那些結果證實該In-B-O薄膜具有一優越之環境穩定性。Figure 15 illustrates the measurement of the resistivity of the In-B-O film as a function of time. Throughout a broad range of compositions (the element ratio B/(In+B) is in the range of 0.05 to 0.5), no change in resistivity with time was observed in the film based on this In-B-O. Furthermore, Figure 2 illustrates the comparison of resistivity over time among other materials. The In-Zn-O film and the In-Sn-O film formed in the same manner as the In-B-O film exhibited a tendency to reduce the resistivity with time. Those results confirmed that the In-B-O film had a superior environmental stability.
其次,具有該In-B-O薄膜當作該n通道層的場效電晶體(FET)之特徵及成份相依被檢查。該電晶體具有圖8C所說明之底部閘極結構。特別地是,一In-B-O成份分級薄膜係形成在具有熱氧化物薄膜之矽基板上,且接著施行佈圖與電極形成,藉此在單一基板上形成包括彼此具有不同成份之主動層的裝置。在該裝置形成之後,在攝氏300度於大氣中施行一退火製程。很多FETs被製成在3吋晶圓上,且以特徵之觀點作評估。該FETs具有一底部閘極、頂部接觸結構,其對於該閘極電極使用n+ -Si,對於該絕緣層使用SiO2 ,且對於該源極及汲極電極使用Au/Ti。該通道層寬度及該通道層長度分別係150微米及10微米。用於該FET評估之源極-汲極電壓係6伏特。Next, the characteristics and composition dependence of the field effect transistor (FET) having the In-BO film as the n-channel layer are examined. The transistor has a bottom gate structure as illustrated in Figure 8C. In particular, an In-BO composition graded film is formed on a tantalum substrate having a thermal oxide film, and then patterning and electrode formation are performed, thereby forming a device including active layers having different compositions from each other on a single substrate. . After the device is formed, an annealing process is performed in the atmosphere at 300 degrees Celsius. Many FETs are fabricated on 3-inch wafers and evaluated from a feature standpoint. The FETs have a bottom gate, top contact structure for which n + -Si is used for the gate electrode, SiO 2 is used for the insulating layer, and Au/Ti is used for the source and drain electrodes. The channel layer width and the channel layer length are 150 microns and 10 microns, respectively. The source-drain voltage for the FET evaluation is 6 volts.
於該TFT特徵評估中,該電子移動率係由Id1/2 相對於該閘極電壓(Vg)之斜率所獲得(Id:汲極電流),且該電流開關比係由該最大Id值及該最小Id值之比率所獲得。當關於Vg畫出Id1/2 時,相對於該Vg軸之截距被取作該閾值電壓,且dVg/d(log Id)之最小值被取作該S值(增加該電流達一數量級所需之電壓值)。In the TFT feature evaluation, the electron mobility is obtained by the slope of Id 1/2 with respect to the gate voltage (Vg) (Id: drain current), and the current switching ratio is determined by the maximum Id value. The ratio of the minimum Id value is obtained. When Id 1/2 is plotted with respect to Vg, the intercept relative to the Vg axis is taken as the threshold voltage, and the minimum value of dVg/d(log Id) is taken as the S value (increasing the current by an order of magnitude) The required voltage value).
藉由在該基板上之各種位置評估TFT特徵檢查TFT特徵關於該元素比率B/(In+B)中之改變。其被發現由於該等TFT特徵視該基板上之位置、亦即視該元素比率B/(In+B)而定變化之結果。各種成份中之Id-Vg特徵被說明在圖4中。The change in the element ratio B/(In+B) is checked by evaluating the TFT characteristics by evaluating the TFT features at various locations on the substrate. It has been found that the TFT characteristics vary depending on the position on the substrate, that is, the element ratio B/(In+B). The Id-Vg characteristics of the various components are illustrated in FIG.
於富含銦成份之案例中(譬如,圖4之(A)),該開啟電流係大的,且該關閉電流係相當大的。一具有該富含銦成份之裝置能被使用,用於需要大開啟電流之應用。當施加一具有比圖4之(A)的案例中較小之元素比率B/(In+B)的薄膜時,該閾值係負的。In the case of an indium-rich component (for example, (A) of Fig. 4), the turn-on current is large, and the turn-off current is relatively large. A device having the indium-rich composition can be used for applications requiring a large on-current. When a film having a smaller element ratio B/(In+B) than in the case of (A) of Fig. 4 is applied, the threshold is negative.
對比於此,於一富含硼成份之案例中(譬如,或圖4之(C)或(D)),該開啟電流係相當小,但該閾值電壓係正的,且因此獲得一“常閉特徵”。一具有富含硼成份之裝置能被使用,用於需要小關閉電流之應用。In contrast, in the case of a boron-rich component (for example, or (C) or (D) of Figure 4, the turn-on current is relatively small, but the threshold voltage is positive, and thus a "normal" Closed feature." A device with a boron-rich composition can be used for applications that require a small shutdown current.
於圖4之(B)的案例中之裝置呈現最優異之特徵。此裝置(圖4之(B))之特徵亦被單獨地說明在圖1中。如在圖1所說明,在具有0.16之元素比率B/(In+B)的裝置(圖4之(B))之案例中,等於或大於十數量級之開關比可被獲得。該S值是0.4V/十倍頻,該場效移動率係3cm2 /Vs,且該閾值電壓係4V。The device in the case of (B) of Figure 4 presents the most superior features. The features of this device (Fig. 4(B)) are also separately illustrated in Fig. 1. As illustrated in FIG. 1, in the case of the device having an element ratio B/(In+B) of 0.16 ((B) of FIG. 4), a switching ratio equal to or greater than ten orders of magnitude can be obtained. The S value is 0.4 V/decade, the field effect mobility is 3 cm 2 /Vs, and the threshold voltage is 4V.
圖5說明該場效移動率之元素比率B/(In+B)相依。其能被看出當該硼含量係減少時,該場效移動率增加。當該元素比率B/(In+B)係0.29或較低時,獲得0.05cm2 /Vs或較高之場效移動率。再者,當該元素比率B/(In+B)係0.22或較少時,獲得0.1cm2 /Vs或較高之場效移動率,且當該元素比率B/(In+B)係0.2或較低時,獲得1cm2 /Vs或較高之場效移動率。Figure 5 illustrates the element ratio B/(In+B) dependence of the field effect mobility. It can be seen that this field effect mobility increases as the boron content decreases. When the element ratio B/(In+B) is 0.29 or lower, a field effect mobility of 0.05 cm 2 /Vs or higher is obtained. Furthermore, when the element ratio B/(In+B) is 0.22 or less, a field effect mobility of 0.1 cm 2 /Vs or higher is obtained, and when the element ratio B/(In+B) is 0.2. At or lower, a field effect mobility of 1 cm 2 /Vs or higher is obtained.
再者,圖6說明該閾值電壓之元素比率B/(In+B)相依。大致上,當一薄膜電晶體之閾值電壓Vth係0伏特或較高時,一電路被輕易地建立。如可為由圖6看出,當該元素比率B/(In+B)係0.1或較高時,Vth變成正的。Furthermore, FIG. 6 illustrates the element ratio B/(In+B) dependence of the threshold voltage. In general, when the threshold voltage Vth of a thin film transistor is 0 volt or higher, a circuit is easily established. As can be seen from Fig. 6, when the element ratio B/(In+B) is 0.1 or higher, Vth becomes positive.
圖7說明該S值之元素比率B/(In+B)相依。如由圖7變得明顯者,當該元素比率B/(In+B)係等於或大於0.12及等於或小於0.2時,獲得一小的S值,其係想要的。Figure 7 illustrates the element ratio B/(In+B) dependence of the S value. As is apparent from Fig. 7, when the element ratio B/(In+B) is equal to or greater than 0.12 and equal to or less than 0.2, a small S value is obtained, which is desirable.
於圖3A及3B中,In-Ga-O被施加至該通道層的電晶體之特徵係與In-Al-O被施加至該通道層的電晶體之特徵作比較。In-Ga-O被施加至該通道層的電晶體之樣本、與In-Al-O被施加至該通道層的電晶體之樣本被生產及評估,如於上述In-B-O被施加至該通道層的電晶體之案例中。具有銦及鎵間之各種成份比率的裝置(具有銦及鋁或鎵間之各種成份比率的裝置)、呈現優異之電晶體特徵的裝置被挑選出。待比較之電晶體特徵被說明在圖3A及3B中。如在圖3A所說明,於銦及第三族元素的B(硼)、鋁、及鎵之一的組合中,In-B-O呈現該最大之開關比。如由圖3B變得明顯者,當In-B-O被使用時,一具有該最小S值之電晶體能被實現。因此,其變得明顯的是該非結晶形氧化物半導體使用二金屬元素當作該TFT之通道材料,In-B-O係優異的。In FIGS. 3A and 3B, the characteristics of the transistor to which In-Ga-O is applied to the channel layer are compared with the characteristics of the transistor in which In-Al-O is applied to the channel layer. A sample of In-Ga-O applied to the transistor of the channel layer, and a sample of the transistor to which the In-Al-O is applied to the channel layer is produced and evaluated, as applied to the channel as described above. In the case of a layer of transistors. A device having a ratio of various components between indium and gallium (a device having a ratio of various components between indium and aluminum or gallium), and a device exhibiting excellent crystal characteristics are selected. The characteristics of the transistor to be compared are illustrated in Figures 3A and 3B. As illustrated in FIG. 3A, In-B-O exhibits the maximum switching ratio in a combination of B (boron), aluminum, and gallium of indium and a third group element. As is apparent from Fig. 3B, when In-B-O is used, a transistor having the minimum S value can be realized. Therefore, it becomes apparent that the amorphous oxide semiconductor uses a dimetal element as a channel material of the TFT, and the In-B-O system is excellent.
在此範例中,生產TFT裝置,其中一非結晶形In-Zn-B-O氧化物半導體係施加至一通道層。該TFT具有圖8B所說明之結構。In this example, a TFT device is produced in which a non-crystalline In-Zn-B-O oxide semiconductor system is applied to a channel layer. This TFT has the structure illustrated in Fig. 8B.
聚對苯二甲酸乙二醇酯(PET)薄膜被製備為一基板。該電晶體之通道長度及通道寬度分別係60微米及180微米。A polyethylene terephthalate (PET) film was prepared as a substrate. The channel length and channel width of the transistor are 60 micrometers and 180 micrometers, respectively.
首先,在此PET基板10上,該閘極電極15被微影術及一光阻剝落方法所形成,且該閘極絕緣層12被形成及佈圖。First, on the PET substrate 10, the gate electrode 15 is formed by lithography and a photoresist peeling method, and the gate insulating layer 12 is formed and patterned.
該閘極電極15係由具有50奈米厚度之鉬薄膜所製成。該閘極絕緣層12係藉由濺鍍法沈積至具有150奈米厚度之SiOx 薄膜。該SiOx 薄膜之特定介電常數係大約3.7。The gate electrode 15 is made of a molybdenum film having a thickness of 50 nm. The gate insulating layer 12 is deposited by sputtering to a SiO x film having a thickness of 150 nm. The specific dielectric constant of the SiO x film is about 3.7.
其次,該電晶體之通道層係經過微影術及一光阻剝落方法藉由濺鍍及佈圖所形成。該通道層係由以In-Zn-B-O為基礎之非結晶形氧化物所製成,其在In:Zn:B=4:6:1之成份比率包含銦、鋅及硼。Secondly, the channel layer of the transistor is formed by sputtering and patterning through lithography and a photoresist stripping method. The channel layer is made of an amorphous oxide based on In-Zn-B-O, which contains indium, zinc and boron at a composition ratio of In:Zn:B=4:6:1.
一以In-Zn-B-O為基礎之非結晶形氧化物薄膜係在氬氣及氧氣之混合大氣中藉由射頻濺鍍所形成。An amorphous oxide film based on In-Zn-B-O is formed by radio frequency sputtering in a mixed atmosphere of argon and oxygen.
在此範例中,三目標(材料來源)藉由同時沈積被用於形成一薄膜。該三目標分別係In2 O3 、B2 O3 及ZnO之2吋尺寸設計的燒結材料。藉由分開地控制用於那些目標之輸入RF功率,一具有想要之In:Zn:B成份比率的氧化物薄膜被獲得。該大氣被設定,使得該總壓力係0.5巴,且該氣體流量比率係Ar:O2 =100:1。該基板溫度被設定至攝氏25度。In this example, three targets (sources of material) are used to form a film by simultaneous deposition. The three targets are sintered materials of two sizes of In 2 O 3 , B 2 O 3 and ZnO, respectively. An oxide film having a desired In:Zn:B composition ratio is obtained by separately controlling the input RF power for those targets. The atmosphere is set such that the total pressure is 0.5 bar and the gas flow ratio is Ar:O 2 =100:1. The substrate temperature was set to 25 degrees Celsius.
該如此形成之氧化物薄膜被發現為一非結晶形薄膜,因為在X射線繞射(薄膜方法,入射角:0.5度)中沒有明顯之繞射峰值被偵測。該非結晶形氧化物薄膜之厚度係大約30奈米。The thus formed oxide film was found to be an amorphous film because no significant diffraction peak was detected in the X-ray diffraction (film method, incident angle: 0.5 degree). The thickness of the amorphous oxide film is about 30 nm.
一光學吸收光譜分析顯露所成形之非結晶形氧化物薄膜具有大約3電子伏特之禁止帶能量寬度,且相對於可見光係透明的。An optical absorption spectroscopy revealed that the formed amorphous oxide film had a forbidden band energy width of about 3 electron volts and was transparent with respect to visible light.
該源極電極、該汲極電極、及該閘極電極係由包括In2 O3 :Sn之透明傳導性薄膜所製成,且每一電極具有100奈米之厚度。The source electrode, the drain electrode, and the gate electrode are made of a transparent conductive film including In 2 O 3 :Sn, and each electrode has a thickness of 100 nm.
以特徵之觀點評估該如此製成之TFT。The thus fabricated TFT was evaluated from the viewpoint of characteristics.
在室溫所測量及評估的PET薄膜上所形成之此範例的電晶體之開關比超過109 。所計算之場效移動率係大約5cm2 /Vs。The switching ratio of this exemplary transistor formed on a PET film measured and evaluated at room temperature exceeded 10 9 . The calculated field effect mobility is approximately 5 cm 2 /Vs.
再者,採用依據此範例之通道用的In-Zn-B-O之薄膜電晶體具有高效能及高環境之穩定性。Furthermore, the thin film transistor using In-Zn-B-O for the channel according to this example has high performance and high environmental stability.
當該非結晶形氧化物材料之元素比率B/(In+Zn+B)係0.05或較高及0.29或較低時,優異之電晶體操作被確保。When the element ratio B/(In+Zn+B) of the amorphous oxide material is 0.05 or higher and 0.29 or lower, excellent transistor operation is ensured.
與使用不包含硼之In-Zn-O當作該通道的薄膜電晶體作比較,使用該以In-Zn-B-O為基礎之氧化物半導體當作該通道的此範例之薄膜電晶體係亦在環境之穩定性中改善(在大氣中之儲存期間的特徵波動係小的)。Compared with a thin film transistor using In-Zn-O which does not contain boron as the channel, the thin film electrocrystal system using this In-Zn-BO based oxide semiconductor as the example of the channel is also Improvement in the stability of the environment (feature fluctuations during storage in the atmosphere are small).
雖然本發明已參考示範具體實施例作敘述,應了解本發明係不限於所揭示之示範具體實施例。以下申請專利之範圍將給與最寬廣之解釋,以便涵括所有此等修改及同等結構與功能。While the invention has been described with reference to the preferred embodiments, the invention The scope of the following patent application is to be accorded the broadest description
10...基板10. . . Substrate
11...通道層11. . . Channel layer
12...閘極絕緣層12. . . Gate insulation
13...源極電極13. . . Source electrode
14...汲極電極14. . . Bipolar electrode
15...閘極電極15. . . Gate electrode
21...基板twenty one. . . Substrate
22...絕緣層twenty two. . . Insulation
23...源極電極twenty three. . . Source electrode
24...汲極電極twenty four. . . Bipolar electrode
25...通道層25. . . Channel layer
31...樣本31. . . sample
32...目標32. . . aims
33...真空泵33. . . Vacuum pump
34...真空計34. . . Vacuum gauge
35...基板夾具35. . . Substrate fixture
36...氣體流量控制器36. . . Gas flow controller
37...壓力控制器37. . . pressure controller
38...薄膜沈積室38. . . Film deposition chamber
111...基底111. . . Base
112...通道層112. . . Channel layer
113...源極電極113. . . Source electrode
114...汲極電極114. . . Bipolar electrode
115...閘極絕緣層115. . . Gate insulation
116...閘極電極116. . . Gate electrode
117...層間絕緣層117. . . Interlayer insulation
118...電極118. . . electrode
119...發光層119. . . Luminous layer
120...電極120. . . electrode
121...薄膜121. . . film
122...薄膜122. . . film
123...胞元123. . . Cell
201...電晶體201. . . Transistor
202...電晶體202. . . Transistor
203...電容器203. . . Capacitor
204...電致發光層204. . . Electroluminescent layer
205...電極線205. . . Electrode line
206...電極線206. . . Electrode line
207...電極線207. . . Electrode line
圖1係一曲線圖,說明以銦-硼-氧為基礎之場效電晶體的轉移特徵。Figure 1 is a graph illustrating the transfer characteristics of a field effect transistor based on indium-boron-oxygen.
圖2係一曲線圖,說明以銦-硼-氧為基礎之場效電晶體的電阻係數中之暫時性變化。Figure 2 is a graph illustrating the temporal variation in the resistivity of a field effect transistor based on indium-boron-oxygen.
圖3A及3B係圖解,說明在以銦-硼-氧為基礎之場效電晶體、以銦-鋁-氧為基礎之場效電晶體、及以銦-鎵-氧為基礎之場效電晶體之中的特徵比較,其中圖3A說明待比較之開關比,且圖3B說明待比較之S值。3A and 3B are diagrams illustrating a field effect transistor based on indium-boron-oxygen, a field effect transistor based on indium-aluminum-oxygen, and a field effect electric based on indium-gallium-oxygen. Comparison of features among the crystals, wherein Figure 3A illustrates the switching ratio to be compared, and Figure 3B illustrates the S values to be compared.
圖4係一曲線圖,說明以具有各種元素比率B/(In+B)的銦-硼-氧為基礎之場效電晶體的轉移特徵。Figure 4 is a graph illustrating the transfer characteristics of a field effect transistor based on indium-boron-oxygen having various element ratios B/(In+B).
圖5係一曲線圖,說明場效移動率的元素比率B/(In+B)相依。Fig. 5 is a graph showing the element ratio B/(In+B) dependence of the field effect mobility.
圖6係一曲線圖,說明閾值電壓之元素比率B/(In+B)相依。Fig. 6 is a graph illustrating the element ratio B/(In+B) dependence of the threshold voltage.
圖7係一曲線圖,說明S值之元素比率B/(In+B)相依。Fig. 7 is a graph showing the element ratio B/(In+B) dependence of the S value.
圖8A、8B、及8C係橫截面視圖,說明根據本發明的一具體實施例之場效電晶體的結構範例。8A, 8B, and 8C are cross-sectional views illustrating an example of the structure of a field effect transistor in accordance with an embodiment of the present invention.
圖9A及9B係曲線圖,說明根據本發明的一具體實施例之場效電晶體的特徵之範例。9A and 9B are graphs illustrating an example of the characteristics of a field effect transistor in accordance with an embodiment of the present invention.
圖10係一示意圖,說明一用於製造該場效電晶體的薄膜形成設備之結構。Figure 10 is a schematic view showing the structure of a thin film forming apparatus for fabricating the field effect transistor.
圖11係一曲線圖,說明一以銦-硼-氧為基礎之半導體薄膜的電阻係數之元素比率B/(In+B)相依。Figure 11 is a graph showing the element ratio B / (In + B) dependence of the resistivity of a semiconductor film based on indium-boron-oxygen.
圖12係一概要橫截面視圖,說明根據本發明的顯示器之範例。Figure 12 is a schematic cross-sectional view showing an example of a display in accordance with the present invention.
圖13係一概要橫截面視圖,說明根據本發明的顯示器之另一範例。Figure 13 is a schematic cross-sectional view showing another example of a display in accordance with the present invention.
圖14係一概要結構視圖,說明一顯示器,其中像素被二維地配置,每一像素包括一有機EL(電激發光)裝置及一薄膜電晶體。Figure 14 is a schematic structural view illustrating a display in which pixels are two-dimensionally arranged, each pixel including an organic EL (electroluminescence) device and a thin film transistor.
圖15係一曲線圖,說明該以銦-硼-氧為基礎之半導體薄膜的電阻係數中之暫時性變化。Figure 15 is a graph showing the temporal change in the resistivity of the indium-boron-oxygen based semiconductor film.
Claims (10)
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| JP2008012592A JP5219529B2 (en) | 2008-01-23 | 2008-01-23 | Field effect transistor and display device including the field effect transistor |
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| CA2585190A1 (en) * | 2004-11-10 | 2006-05-18 | Canon Kabushiki Kaisha | Amorphous oxide and field effect transistor |
| WO2011027701A1 (en) * | 2009-09-04 | 2011-03-10 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device and method for manufacturing the same |
| CN102598283B (en) | 2009-09-04 | 2016-05-18 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| KR20220038542A (en) | 2009-10-21 | 2022-03-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Analog circuit and semiconductor device |
| KR20170130641A (en) * | 2009-10-21 | 2017-11-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Liquid crystal display device and electronic device including the same |
| CN102723364B (en) * | 2009-10-21 | 2015-02-25 | 株式会社半导体能源研究所 | Semiconductor device with a plurality of transistors |
| KR20240042253A (en) | 2009-10-29 | 2024-04-01 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| WO2011058934A1 (en) | 2009-11-13 | 2011-05-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method thereof |
| KR101833198B1 (en) | 2009-12-04 | 2018-03-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device and electronic device including the same |
| KR101998737B1 (en) * | 2009-12-18 | 2019-07-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Liquid crystal display device and electronic device |
| KR101434948B1 (en) | 2009-12-25 | 2014-08-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
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| KR20140106977A (en) * | 2013-02-27 | 2014-09-04 | 삼성전자주식회사 | Metal oxide semiconductor Thin Film Transistors having high performance and methods of manufacturing the same |
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| KR102598375B1 (en) * | 2018-08-01 | 2023-11-06 | 이데미쓰 고산 가부시키가이샤 | Crystal structure compound, oxide sintered body, sputtering target, crystalline oxide thin film, amorphous oxide thin film, thin film transistor and electronic equipment |
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| US8314425B2 (en) | 2012-11-20 |
| JP5219529B2 (en) | 2013-06-26 |
| EP2243164A1 (en) | 2010-10-27 |
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| TW201001701A (en) | 2010-01-01 |
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| CN101926008B (en) | 2012-08-29 |
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