TWI405259B - A plasma etch method and a computer readable memory medium - Google Patents

Abstract

A plasma etching method for forming a trench on a substrate or on a film formed on the substrate, includes an substrate arranging step of arranging the substrate on which the trench is to be formed in a processing chamber having therein a first and a second electrode disposed to face each other vertically; a processing gas introducing step of introducing a processing gas for etching into the processing chamber; a plasma generating step of generating a plasma by applying a high frequency electric power to either of the first and the second electrode; and a DC voltage applying step of applying a DC voltage to said either of the electrodes. Further, a computer-readable storage medium stores therein a computer-executable control program, wherein, when the control program is being executed, a computer is made to control a plasma processing apparatus to perform the plasma etching method.

Description

Plasma etching method and computer readable memory medium

The present invention relates to a plasma etching method for forming a trench on a substrate or an interlayer insulating film formed on a substrate, and a computer readable memory medium.

In the semiconductor element, the wiring interval is reduced due to the miniaturization, and a large capacitance is generated between the wirings, because the propagation speed of the signal is lowered, resulting in a delay in the operation speed. In order to solve this problem, an insulating material (Low-k material) having a lower dielectric constant has recently been used as an interlayer insulating film, and copper having low electrical resistance and high electromigration resistance has been used as a wiring material (Cu). At the same time, the double damascene method is often used in forming the groove wiring or the connection hole of copper.

When a multilayer wiring of copper is formed by the dual damascene method, an etching stopper film is formed on the underlying copper wiring, and a Low-k film is formed thereon as an interlayer insulating film, and a metal hard mask layer is formed thereon. After the anti-reflection film (BARC) and the photoresist film, the Low-k film is etched to form a via hole, and then after etching the trench, the etching stopper film is etched to penetrate the via hole, and then Cu is buried. Wiring layer.

On the other hand, in the case of integrating a power IC of a power MOSFET, a trench is formed on a germanium substrate (semiconductor wafer) in order to obtain a high power, and a trench in which an extended drain region is disposed in the trench is proposed. Slot horizontal power MOSFET. In the trench lateral power MOSFET, since the extended drain region required for the withstand voltage can be controlled by the depth of the trench, there is a so-called on-resistance per unit area, which is smaller than that of the conventional germanium substrate surface. The advantages of the power MOSFET in the polar region.

The trench formed in the Low-k film directly affects the thickness of the wiring, and the trench formed in the germanium substrate for expanding the drain region directly affects the withstand voltage, and thus the uniformity of etching Extremely important. However, when such trenches are formed, since etching cannot be stopped with different films, it is easy to cause unevenness in the etching depth, and when the trench is etched, the uniformity of the etching rate in the plane of the control semiconductor wafer becomes important.

In the past, plasma etching has been dominated by capacitively coupled parallel plate plasma etching devices. A capacitively coupled parallel plate plasma etching apparatus is provided with a pair of parallel plate electrodes (upper and lower electrodes) disposed in a reaction chamber, and a high frequency is applied to one side of the electrode while introducing a processing gas into the reaction chamber, and at the electrode A high-frequency electric field is formed therebetween, and a plasma of the processing gas is formed by the high-frequency electric field, and plasma etching is performed on a specific layer of the semiconductor wafer.

Specifically, a plasma etching apparatus in which a high frequency for forming a plasma is applied to an upper electrode and a plasma is formed, a high frequency for ion introduction is applied to the lower electrode, and a suitable plasma state is formed (for example, a patent) Document 1).

With such a capacitive coupling type parallel plate plasma etching apparatus, when etching is performed using a negative gas of CF ₄ , there is generally a tendency that the plasma density of the central portion of the semiconductor wafer is lowered, and an etching rate is present at the central portion. The tendency to decrease. Therefore, the etching rate is controlled by controlling the parameters from the pressure in the reaction chamber or the applied power of the high-frequency power source, and the in-plane uniformity of etching is sought.

However, when the uniformity of the etching is controlled by the existing parameters, even if the etching rate of the central portion can be lowered, since the etching rate of other portions changes at the same time, it becomes a W-type or M-type etching rate distribution, which is difficult. The uniformity of the etching to the extent required for trench etching is obtained. Moreover, in the etching of the trenches, although directed to low-power etching, in the low-power process, it is difficult to control the etching rate with such existing parameters.

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2000-173993

The present invention has been made in view of the above problems, and an object of the present invention is to provide a plasma etching which can perform etching of a groove having excellent in-plane uniformity for a film directly or on a substrate which is not limited to high-frequency power. method.

Further, it is an object to provide a computer readable memory medium that memorizes a program for performing such a plasma etching method.

In order to solve the above problems, the present invention provides a plasma etching method for forming a trench formed on a substrate or a substrate, and is provided to be provided so as to face up and down with the first electrode and the second electrode. a step of arranging a substrate on which a groove is to be formed in the processing container; a step of introducing a processing gas for etching into the processing container; and applying a high frequency to any of the first electrode and the second electrode a step of generating a plasma, and a step of applying a DC voltage to any of the electrodes.

The aforementioned DC voltage is preferably in the range of -400 to -1500V. Further, the trench is preferably formed on the interlayer insulating film formed on the substrate, and the trench may be formed after the interlayer insulating film is formed into a via hole. Further, in the object to be processed for testing, a DC voltage value at which the in-plane uniformity of the desired etching can be obtained is obtained, and a DC voltage value at this time is applied to any of the electrodes, and the specific DC is applied. The voltage step can also be used. Further, the first electrode is an upper electrode, and the second electrode is a lower electrode to be processed, and the high-frequency power and the DC voltage for generating the plasma may be applied to the first electrode. At this time, high frequency power for ion introduction may be applied to the second electrode.

The invention provides a computer readable memory medium, which is a control program for memorizing movement on a computer, characterized in that: when the control program is implemented, the computer controls the plasma processing device to enable the electric power to be performed. Slurry etching method.

According to the invention, when a groove is formed on a film of a substrate or an interlayer insulating film formed on a substrate, high-frequency power is applied to any of the first and second electrodes to generate a plasma, and since any one of the electrodes is applied The DC voltage is such that even if the plasma is formed by the DC voltage, the plasma density is increased, and the function of increasing the etching rate is exhibited. At this time, not only the high-frequency power, but also the plasma density of the comparative center portion due to the diffusion of the plasma. When the etching gas is a negative gas, the plasma density is easily lowered, and the etching rate of the center portion is increased. And can be evenly etched.

Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

Fig. 1 is a schematic cross-sectional view showing an example of a plasma etching apparatus used in the practice of the present invention.

The plasma etching apparatus is configured as a capacitive coupling type parallel plate plasma etching apparatus, for example, a reaction chamber (processing container) 10 having a substantially cylindrical shape composed of aluminum whose surface is anodized. The reaction chamber 10 is secured to ground.

At the bottom of the reaction chamber 10, a cylindrical inductor support 14 is disposed via an insulating plate 12 made of ceramic or the like. On the upper surface of the inductor support 14, for example, an inductor 16 made of aluminum is provided. . The inductor 16 constitutes a lower electrode, and a substrate to be processed, that is, a semiconductor wafer W is placed thereon.

An electrostatic chuck 18 that adsorbs and holds the semiconductor wafer W by electrostatic force is disposed on the upper surface of the inductor 16. The electrostatic chuck 18 has a structure in which an electrode 20 composed of a conductive film is sandwiched by a pair of insulating layers or insulating sheets, and the DC power source 22 is electrically connected to the electrode 20. Then, the semiconductor wafer W is adsorbed and held by the electrostatic chuck 18 by an electrostatic force such as a Coulomb force generated by a DC voltage from the DC power source 22.

In order to enhance the uniformity of etching around the electrostatic chuck 18 (semiconductor wafer W), for example, a conductive focus ring (correction ring) 24 composed of tantalum is disposed on the upper surface of the inductor 16. On the side faces of the inductor 16 and the inductor support table 14, for example, a cylindrical inner wall member 26 made of quartz is provided.

Inside the inductor support table 14, for example, a cold coal chamber 28 is provided on the circumference. The cold coal chamber is circulated and supplied with cold coal of a specific temperature, such as cooling water, through a pipe 30a, 30b through a cooling unit (not shown) provided outside, and the semiconductor crystal on the inductor can be controlled by the temperature of the cold coal. The processing temperature of the circle W.

Further, a heat transfer gas such as He gas from a heat transfer gas supply means (not shown) is supplied between the upper surface of the electrostatic chuck 18 and the back surface of the semiconductor wafer W via the gas supply line 32.

Above the inductor 16 of the lower electrode, an upper electrode 34 is disposed in parallel with the inductor 16. Then, the space between the upper and lower electrodes 34, 16 becomes a plasma generation space. The upper electrode 34 forms a surface that faces the semiconductor wafer W on the inductor 16 of the lower electrode and is in contact with the plasma generation space, that is, the opposite surface.

The upper electrode 34 is supported by the insulating shielding member 42 at the upper portion of the reaction chamber 10 to form an electrode plate 36 having a plurality of discharge holes 37 on the surface opposite to the inductor 16, and is detachably supported. The electrode plate 36 is composed of a conductive material such as a water-cooled electrode holder 38 made of an anodized aluminum, and the electrode plate 36 is preferably a low-resistance electric conductor or semiconductor having less Joule heat. As described later, from the viewpoint of strengthening the resist, a substance containing ruthenium is preferred. From this point of view, the electrode plate 36 is preferably formed of tantalum or SiC. A gas diffusion chamber 40 is provided inside the electrode support 38, and a plurality of gas flow holes 41 that communicate with the gas discharge holes 37 are extended downward from the gas diffusion chamber 40.

A gas introduction port 62 for introducing a processing gas into the gas diffusion chamber 40 is formed in the electrode support 38, a gas supply pipe 64 is connected to the gas introduction port 62, and a processing gas supply source 66 is connected to the gas supply pipe 64. The gas supply pipe 64 is provided with a mass flow controller 68 (MFC) and an on-off valve 70 from the upstream side (or FCN may be used instead of the MFC). Then, the processing gas for etching from the processing gas supply source 66 is discharged from the gas supply pipe 64 to the gas diffusion chamber 40 through the gas circulation hole 41 and the discharge hole 37, and is ejected into the plasma generation space. That is, the upper electrode 34 functions as a head for supplying a processing gas.

The first high frequency power source 48 is electrically connected to the upper electrode 34 via the integrator 46 and the power supply bar 44. The first RF power supply 48 output line a frequency above 10MH _z, for example, a high frequency power of 60MH _z. The integrator 46 has an internal impedance (or output) integrated with the load impedance of the first high-frequency power source 48, and when the plasma is generated in the reaction chamber 10, the output impedance and the load impedance of the first high-frequency power source 48 are in appearance. Consistent features. The output terminal of the integrator 46 is connected to the upper end of the power feeding bar 44.

Further, the upper electrode 34 is electrically connected to the variable DC power source 50 in addition to the first high frequency power source 48. The variable DC power supply 50 is also a dual carrier power supply. Specifically, the variable DC power supply 50 is connected to the upper electrode 34 via the integrator 46 and the power supply bar 44, and the start-up release switch 52 is used to activate the power supply. Lifting becomes possible. The polarity and current of the variable DC power supply 50. Voltage, and activation of the start release switch 52. The release is controlled by the controller 51.

As shown in FIG. 2, the integrator 46 includes a first variable capacitor 54 that is provided separately from the power supply line 49 of the first high-frequency power source 48, and a downstream side that is provided on the branch line of the power supply line 49. The variable capacitor 56 serves to perform the above functions. Further, the integrator 46 is effective to supply a DC voltage current to the upper electrode 34 (hereinafter, simply referred to as a DC voltage), and is provided with a filter 58 for trapping a high frequency from the first high frequency power source 48 (for example, , 60MH _z); and a high frequency of said second high-frequency power from the rear (e.g., 2MH _z). That is, the DC power source from the variable DC power source 50 is connected to the power supply line 49 via the coil 59. The filter 58 is composed of a coil 59 and a capacitor 60, thereby trapping a high frequency from the first high-frequency power source 48 and a high frequency from a second high-frequency power source to be described later.

Extending from the side wall of the reaction chamber 10 toward a position higher than the height position of the upper electrode 34, a cylindrical ground conductor 10a is provided, and the wall portion of the ground conductor 10a is electrically connected to the power rod 44 by the tube 44a. insulation.

The inductor 16 for the lower electrode is electrically connected to the second high frequency power supply 90 via the integrator 88. High frequency power is supplied to the lower electrode inductor 16 from the second high frequency power supply 90, and ions are introduced to the semiconductor wafer W side. Second high-frequency power supply 90 output a frequency in the range of lines to 13.56MH _z 300kH _z sum of, for example, the output of high frequency power 2MH _z. The integrator 88 has an internal (or output) impedance integrated load impedance to the second high-frequency power supply 90, and when the plasma is generated in the reaction chamber 10, the internal impedance and the load impedance of the second high-frequency power supply 90 are applied. Become a consistent feature.

34 without the upper electrode system (e.g. 60MH _z) from the first frequency by the RF power supply 48 is electrically connected to the high-frequency from the second high-frequency power supply 90 (e.g. 2MH _z) towards the ground through the low-pass filter 92 (LPF). The low pass filter 92 (LPF) Although LR filter or LC filter composed of preferred, but also only one wire, from a high frequency electric wire 49 (60MH _z) supplied considerable resistance, So it is also possible to end here. In addition, the sensor lower electrode 16 is electrically connected to the high-frequency line from the first high-frequency power supply 48 (60MH _z) toward the ground by the high-pass filter 94 (HPF).

An exhaust port 80 is provided at the bottom of the reaction chamber 10, and the exhaust port 84 is connected to the exhaust device 84 via the exhaust pipe 82. The exhaust unit 84 has a vacuum pump such as a turbo molecular pump, and the inside of the reaction chamber 10 can be decompressed to a desired degree of vacuum. Further, a carry-in port 85 of the semiconductor wafer W is provided on the side wall of the reaction chamber 10, and the carry-in port 85 can be opened and closed by the gate valve 86. Further, along the inner wall of the reaction chamber 10, an attachment shielding portion 11 for preventing adhesion of an etching by-product (adhesion) to the reaction chamber 10 is detachably provided. That is, the deposit shielding portion 11 constitutes a reaction chamber wall. Further, the deposit shielding portion 11 may be provided on the outer circumference of the inner wall member 26. An exhaust plate 83 is provided between the deposit shielding portion 11 on the reaction chamber wall side of the reaction chamber 10 and the deposit shielding portion 11 on the inner wall member 26 side. It is also preferable to use a ceramic material such as Y ₂ O ₃ covering the aluminum material as the deposit shielding portion 11 and the exhaust plate 83.

A conductive member (GND block) 91 connected to the ground line DC is provided at a portion of substantially the same height as the wafer W constituting a portion of the reaction chamber wall of the deposit shielding portion 11, thereby exhibiting abnormal discharge prevention. effect.

Each component of the plasma processing apparatus is configured to be connected to the control unit 95 and controlled (entire control unit). Further, the control unit 95 is connected to a keyboard including a keyboard for inputting an operation of a command for managing a plasma processing device, or a display for displaying a state of operation of the plasma processing device. Interface 96.

Further, the control unit 95 is connected to a control program for realizing various processes performed by the plasma processing device under the control of the control unit 95, and a program for performing processing in each component of the plasma processing device in accordance with the processing conditions. That is, the memory portion 97 of the menu is stored. The menu can also be stored in a hard disk or a semiconductor memory, and can be mounted at a specific position of the memory unit 97 in a state in which it can be stored in a memory medium that can be read by a portable computer such as a CDROM or a DVD.

Then, if necessary, the controller 95 performs an arbitrary menu from the memory unit 97 by an instruction from the user interface 96, and performs desired processing in the plasma processing apparatus under the control of the control unit 95. .

Next, a plasma etching method according to an embodiment of the present invention which is implemented by the plasma etching apparatus of this configuration will be described.

Here, as shown in FIG. 3, a copper wiring layer 102, an etching stopper film 103, an interlayer insulating film 104, a metal hard mask layer 105 for patterning trench etching, and reflection prevention are sequentially formed on the Si substrate 101. The film 106 (BARC) and the photoresist film 107 are used as a semiconductor wafer W to be processed, and the photoresist film 107 is used as an etching mask to be etched to the anti-reflection film 106 and the interlayer insulating film 104. On the way, the person who forms the partial through hole 108 is used. Then, the photoresist film 107 and the BAR anti-reflection film 106 are removed by etching from the state of FIG. 3, and the state of FIG. 4 is obtained, and the trench is etched using the metal hard mask layer 105 as an etching mask. That is, the through holes and the grooves are formed by a so-called double damascene method.

The etching stopper film 103 is made of a SiC-based material such as SiCN, and has a thickness of about 20 to 100 nm. Further, as the interlayer insulating film 104 which is the target of the trench etching of the present embodiment, a Low-k film such as a SiCO film can be applied. Of course, it may be composed of a material conventionally used such as SiO ₂ . The interlayer insulating film 104 has a thickness of about 250 to 340 nm. The material constituting the metal hard mask layer 105 is exemplified by TiN having a thickness of about 15 to 45 nm. The organic phase of the anti-reflection film 106 is a mainstream (BARC) and has a thickness of about 20 to 100 nm. The photoresist film 107 is an ArF resist and has a thickness of about 100 to 400 nm.

In the etching of the trench, first, the gate valve 86 is opened, and the semiconductor wafer W having the above-described structure is carried into the reaction chamber 10 via the carry-in port 85, and placed on the inductor 16. Then, the processing gas for etching the interlayer insulating film 104 is supplied from the processing gas supply source 66 to the gas diffusion chamber 40 at a specific flow rate, and is supplied into the reaction chamber 10 through the gas circulation hole 41 and the discharge hole 37, and by The exhaust device 84 exhausts the gas in the reaction chamber 10, and the pressure therein is set to, for example, a set value in the range of 2.7 to 40 Pa. Further, the temperature is about 20 to 50 ° C, for example, 40 ° C, and the wafer temperature is about 20 to 100 ° C, for example, about 60 ° C.

As the processing gas for etching the interlayer insulating film 104 composed of the Low-k film, various kinds of conventionally used gases can be used, and for example, a gas containing (C _x F _y ) is exemplified. Typically, it is possible to use an addition of CF ₄ gas, a single gas or to add an Ar gas, a He gas or the like here, and more preferably an Ar gas or an O ₂ gas in a C ₄ F ₈ gas or a C ₅ F ₈ gas.

In the state where the etching gas is introduced into the reaction chamber 10, the high-frequency electric potential for plasma generation is applied to the upper electrode 34 from the first high-frequency power source 48 at a specific power, and the second high-frequency power source 90 is applied. The lower electrode inductor 16 is applied with a high frequency for ion introduction at a specific power. Then, a specific DC voltage is applied to the upper electrode 34 from the variable DC power source 50. Further, a DC voltage is applied from the DC power source 22 of the electrostatic chuck 18 to the electrode 20 of the electrostatic chuck 18, and the semiconductor wafer is fixed to the inductor 16.

The processing gas discharged from the discharge hole 37 formed in the electrode plate 36 of the upper electrode 34 is plasma-charged in the overall discharge between the upper electrode 34 generated by the high-frequency power and the inductor 16 of the lower electrode. The interlayer insulating film 104 of the semiconductor wafer W is trench-etched by the radical or ion generated by the plasma using the metal hard mask layer 105 as an etching mask.

At this time, the upper electrode 34 is supplied with a high frequency region (e.g., above 10MH _z) frequency power, high density plasma can therefore be in the best state, but even at lower pressure conditions, also High density plasma can be formed. Further, in the case where plasma is formed, the DC voltage of a specific polarity and magnitude is applied to the upper electrode 34 from the variable DC power source 50, so that the plasma etching rate can be controlled. Thereby, trench etching with good in-plane uniformity can be performed.

According to this etching, as shown in Fig. 5, the etching stopper film 109 is formed in the interlayer insulating film 104, and at the same time, the portion of the partial via hole 108 is also etched to form the via hole 108' which reaches the etching stopper film 103.

Then, the etching stopper film 103 is etched under specific conditions and penetrates the via hole 108'. Then, according to the regulation, metal such as copper is buried in the through hole 108' and the groove 109.

Then, it is explained that the etching rate is controlled by applying such a direct current voltage.

By applying a DC voltage to the upper electrode 34, not only high-frequency power but also a plasma can be formed by the applied DC voltage. Therefore, the plasma density is increased and the etching rate is increased. This is because when a negative DC voltage is applied to the upper electrode 34, it is difficult for electrons to enter the upper electrode, and electron elimination is suppressed, and when ions accelerate into the upper electrode, electrons come out of the electrode, and the electrons have a plasma potential and an applied voltage. The difference in value, high-speed acceleration and ionization of neutral gas (plasma), increase electron density (plasma density).

Further, when the plasma is formed, when a DC voltage is applied from the variable DC power source 50 to the upper electrode 34, the plasma density is increased, so that the plasma density at the center portion can be increased. In particular, when the pressure in the reaction chamber 10 is relatively high and the etching gas used is a negative gas, the plasma density in the central portion of the reaction chamber 10 tends to be low, and thus, by the upper electrode 34 By applying a DC voltage, the plasma density at the center portion can be increased, and by controlling the voltage value of the DC voltage, the etching rate can be controlled to perform uniform etching.

In particular, when etching such a trench, the in-plane uniformity of the depth is very important, and an etching stopper film or the like cannot be provided in the properties to control the depth thereof, and the etching process itself is required to have an extremely high in-plane uniformity. Sexuality, but by controlling this applied DC voltage, the desired etch uniformity can be obtained.

In order to effectively exert such an effect, the DC voltage applied to the upper electrode 34 is preferably in the range of -400 to -1500V.

When performing the plasma etching method of the present embodiment, first, the semiconductor wafer for testing is subjected to trench etching under specific conditions according to the plasma etching apparatus of Fig. 1, and then the semiconductor wafer is taken out from the plasma etching apparatus. When the inspection is performed by the inspection device, the interlayer insulating film is etched in advance to form a trench, and a DC voltage value at which etching uniformity is obtained is obtained, and the DC voltage value at this time is applied to the upper electrode for etching. The etching process can be performed quickly and correctly. As the wafer for this test, one or two or more wafers of the first batch can be used.

Next, the results of actually confirming the effects of the method of the present invention will be described. First, a SiO ₂ film is formed on a germanium substrate, and the cladding etching is performed. The etching conditions at this time are as follows.

Pressure: 13.3Pa (100mTorr) RF power (upper 60MH _z / lower portion 2 MH _z): 300 / 300W DC voltage: -500V, -600V, -650V process gas C ₄ F ₈ gas: 30mL / min (sccm) CF 4 Gas: 40 mL/min (sccm) N ₂ gas: 90 mL/min (sccm) Ar gas: 750 mL/min (sccm) O ₂ gas: 5 mL/min (sccm) Time: 60 sec Temperature sensor: 60 ° C Wafer: 50 °C

After the etching, the result of the distribution of the etching rate was obtained from the amount of residual film, and the result shown in Fig. 6 was obtained. That is, when the DC voltage is -500 V, the etching rate tends to become higher from the center toward the edge portion, and becomes uniform in the plane at a substantially etch rate of -600 V, and vice versa when it becomes -650 V. The rate has a tendency to become higher. Therefore, a DC voltage is applied to the upper electrode, and the etching rate can be controlled by controlling the voltage thereof, and it is confirmed that uniform etching can be performed. Then, as is clear from Fig. 6, when the DC voltage is -600 V, the uniformity of the etching rate is optimized. Further, the actual etching uniformity depends on the thickness distribution of the film to be etched, and therefore, the etching rate must have uniform conditions, and is not limited to uniform etching.

Then, the conditions are changed to perform the same etching. The conditions at this time are expressed as follows.

Pressure: 8.0Pa (60mTorr) RF power (upper 60MH _z / lower portion 2 MH _z): 300 / 150W DC voltage: -500V, -600V, -700V process gas C ₄ F ₈ gas: 10mL / min (sccm) CF 4 Gas: 112 mL/min (sccm) Ar gas: 150 mL/min (sccm) O ₂ gas: 6 mL/min (sccm) Time: 60 sec Temperature sensor: 60 ° C Wafer: 40 ° C

The result of the distribution of the etching rate from the residual film amount after the etching, as shown in Fig. 7, shows the same tendency as in Fig. 6. That is, when the DC voltage is -500 V, the etching rate from the center toward the edge portion tends to become higher, and when it is -600 V, the etching rate at the center rises and the uniformity is good, and conversely, when it becomes -700 V. The etching rate at the center tends to become higher. Therefore, even if the conditions are changed, it is confirmed that the same tendency is indicated.

Then, actually, as shown in FIG. 3 described above, the BAR anti-reflection film 106 and the interlayer insulating film 104 are etched using the photoresist film 107 as an etching mask, and after the local via holes 108 are formed, the polishing is performed. The BAR anti-reflection film 106 and the photoresist film 107 are removed, and the state of FIG. 4 is performed, and trench etching is performed. The conditions are as follows.

Pressure: 13.3Pa (100mTorr) RF power (upper 60MH _z / lower portion 2 MH _z): 300 / 300W DC voltage: -500V the process gas C ₄ F ₈ gas: 30mL / min (sccm) CF 4 gas: 40mL / min ( Sccm) N ₂ gas: 90 mL/min (sccm) Ar gas: 750 mL/min (sccm) O ₂ gas: 5 mL/min (sccm) Time: 100 sec Temperature sensor: 40 ° C Wafer: 60 ° C

After the etching, the depth of the groove was obtained from a scanning electron microscope (SEM) photograph at 9 o'clock as shown in Fig. 8 of the semiconductor wafer. As a result, the groove depth at each point is as follows.

No. 1: 272 nm No. 2: 264 nm No. 3: 264 nm No. 4: 272 nm No. 5: 276 nm No. 6: 272 nm No. 7: 256 nm No. 8: 274 nm No. 9: 266 nm

Thus, the unevenness of the depth of the trench etching is 20 nm, which is a significant improvement over the conventional 70 to 90 nm.

According to the above, when the trench is formed on the semiconductor wafer by plasma etching, a DC voltage is applied to the upper electrode 34, and by controlling the voltage value, the etching rate can be made uniform in the plane, and it is confirmed that the trench can be improved. In-plane uniformity of the etch depth.

Further, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, an example of a double damascene structure is shown, but it can be realized even in a general mosaic structure. Further, although the case where the trench is formed in the interlayer insulating film is shown, it is not limited to the interlayer insulating film, and the trench may be formed in another film. Further, it is not limited to the case where a film is formed on the substrate, and a groove may be formed in the substrate itself.

Further, the apparatus to which the present invention is applied is not limited to those shown in Fig. 1, and various types shown below may be used. For example, as shown in FIG. 9, the sensor lower electrode 16, the first high-frequency power source 48 'is applied to the plasma generating high frequency power of, for example, 60MH _z, and the second high-frequency power supply 90' is applied to the ion attracting a high frequency power of, for example, under the section 2 2MH _z-frequency type plasma etching apparatus is applied. As shown in the figure, by connecting the variable DC power source 166 to the upper electrode 234 and applying a specific DC voltage, the same effects as those of the above embodiment can be obtained.

Further, at this time, as shown in FIG. 10, the DC power source 168 may be connected to the inductor 16 of the lower electrode, and a DC voltage may be applied to the inductor 16.

Further, as shown in Fig. 11, the upper electrode 234' is grounded via the reaction chamber 10, and the high-frequency power source 170 is connected to the lower electrode inductor 16, and the high-frequency power source 170 can also be applied to apply plasma. Forming a plasma etching apparatus in the form of high frequency power of, for example, 13.56 MH _Z. At this time, as shown in the figure, the inductor 16 of the lower electrode is connected to the variable DC power source 172 by applying a specific DC voltage. The same effects as those of the above embodiment were obtained.

Further, as shown in Fig. 12, the upper electrode 234' which is the same as Fig. 11 is grounded by the reaction chamber 10, and the high frequency power source 170 is connected to the inductor 16 of the lower electrode, and electricity is applied from the high frequency power source 170. In the etching apparatus in the form of high frequency power for slurry formation, a variable DC power source 174 may be applied to the upper electrode 234'.

10. . . Reaction chamber (processing vessel)

16. . . Sensor (lower electrode)

34. . . Upper electrode

44. . . Electric bar

46, 88. . . Integrator

48. . . First high frequency power supply

50. . . Variable DC power supply

51. . . Controller

52. . . Start release switch

66. . . Process gas supply

84. . . Exhaust

90. . . Second high frequency power supply

91. . . GND block

101. . . Si substrate

102. . . Copper wiring layer

103. . . Etch barrier film

104. . . Interlayer insulating film

105. . . Metal hard mask layer

106. . . Anti-reflection film

107. . . Photoresist film

108. . . Partial through hole

108'. . . Through hole

109. . . Trench

W. . . Semiconductor wafer (substrate)

Fig. 1 is a schematic cross-sectional view showing an example of a plasma etching apparatus used in the practice of the present invention.

Fig. 2 is a structural view of an integrator connected to a first high-frequency power source in the plasma etching apparatus of Fig. 1.

Fig. 3 is a cross-sectional view showing a state in which a local via hole is formed in a semiconductor wafer used in an embodiment of the present invention by etching.

Fig. 4 is a view showing a structure of a semiconductor wafer in a state in which a BARC and a photoresist film are polished from a state of a partial via hole in the third drawing of the stroke.

Fig. 5 is a schematic view showing a state in which an interlayer insulating film is etched to form a trench by this embodiment.

Fig. 6 is a view showing an example of an in-plane division of an etching rate of an oxide film when the applied DC voltage is changed.

Fig. 7 is a view showing another example of the in-plane division of the etching rate of the oxide film when the applied DC voltage is changed.

Figure 8 is a diagram of the position on a semiconductor wafer where the depth of the trench is actually measured after trench etching.

Fig. 9 is a schematic view showing an example of a plasma etching apparatus of another form which can be applied to the practice of the present invention.

Figure 10 is a cross-sectional view showing an example of a plasma etching apparatus of another form which can be applied to the practice of the present invention.

Fig. 11 is a schematic view showing an example of a plasma etching apparatus of another form which can be applied to the practice of the present invention.

Fig. 12 is a cross-sectional view showing an example of a plasma etching apparatus of another form which can be applied to the practice of the present invention.

W. . . Semiconductor wafer (substrate)

10. . . Reaction chamber

10a. . . Grounding conductor

11. . . Attachment shelter

12. . . Insulation board

14. . . Sensor support

16. . . Lower electrode

18. . . Electrostatic chuck

20. . . electrode

twenty two. . . DC power supply

twenty four. . . Focus ring

26. . . Inner wall member

28. . . Cold coal room

30a, 30b. . . Piping

32. . . Gas supply line

34. . . Upper electrode

36. . . Electrode plate

37. . . Gas discharge hole

38. . . Electrode support

40. . . Gas diffusion chamber

41. . . Gas circulation hole

42. . . Insulating shielding member

44. . . Electric bar

44a. . . cylinder

46. . . Integrator

48. . . First high frequency power supply

50. . . Variable DC power supply

51. . . Controller

52. . . Start release switch

62. . . Gas inlet

64. . . Gas supply pipe

66. . . Gas supply

68. . . Mass flow controller

70. . . Switch valve

80. . . exhaust vent

82. . . exhaust pipe

83. . . Exhaust plate

84. . . Exhaust

85. . . Move into the exit

86. . . gate

88. . . Integrator

90. . . Second high frequency power supply

91. . . Conductive member (GND block)

92. . . Low pass filter (LPF)

94. . . High pass filter (HPF)

95. . . Control department

96. . . user interface

97. . . Memory department

Claims (7)

A plasma etching method for forming a trench and a via hole in an interlayer insulating film of a SiCO-based Low-k film formed on a substrate, characterized by comprising: forming a trench etching on the interlayer insulating film a metal hard mask layer, forming an etching mask for local via etching on the interlayer insulating film formed on the metal hard mask layer, etching to the interlayer insulating film, and forming a local pass in the interlayer insulating film a step of removing the etching mask; and a substrate having an interlayer insulating film on which the partial via is formed is placed in a processing container provided so that the upper electrode and the lower electrode face up and down, and the substrate is placed on the substrate a step of disposing a lower electrode of the conductive focus ring composed of ruthenium; a step of introducing a fluorocarbon (CxFy) gas for etching into the processing container; applying a high-frequency voltage to the upper electrode to generate electricity a step of applying a high frequency power for ion introduction to the lower electrode, and applying a range of -400 to -1500 V to the upper electrode by a variable direct current power source The DC voltage is a step of forming a trench and a via hole in the interlayer insulating film formed by the local via hole. The plasma etching method of claim 1, wherein the metal hard mask layer is TiN. A plasma etching method according to claim 1 or 2, An etching stopper film is formed under the interlayer insulating film, and the trench is formed in the middle of the interlayer insulating film, and the via hole is formed to reach the etching stopper film. A plasma etching method according to claim 1 or 2, wherein the object to be processed for testing is previously performed: determining a DC voltage value at which uniformity of in-plane etching of a desired etching can be obtained, and DC at this time A voltage value is applied to the aforementioned upper electrode to apply the aforementioned specific DC voltage. The plasma etching method of claim 4, wherein the object to be processed for the test is a SiO ₂ film formed on a substrate. The plasma etching method according to claim 1 or 2, wherein the variable DC power source transmits a high frequency from a high frequency voltage applied to the upper electrode, and a high frequency applied from the lower electrode a high frequency filter of voltage connected to a power supply line of a high frequency voltage applied to the upper electrode; by controlling a voltage value of a negative DC voltage applied to the upper electrode in a range of -400 to -1500 V, The etching rate at the time of forming the trench and the via hole in the interlayer insulating film formed with the partial via hole is uniform in the plane of the substrate. A computer-readable memory medium is a control program that memorizes movements on a computer, and is characterized in that: when the control program is implemented, the computer controls the plasma processing device so that the patent application range can be made to A plasma etching method according to any one of the six items.