TWI405171B - Video display device capable of compensating for display defects - Google Patents

Abstract

A video display device capable of compensating for varous display defects using compensation data and having a simple circuit configuration is disclosed. The video display device includes comprising: liquid crystal panel for displaying an image through a pixel matrix; a data driver for outputting data to data lines of the liquid crystal display panel; a gate driver for driving the gate lines of the liquid crystal display panel; a timing controller for receiving compensated data, uncompensated data and synchronizing signals to output a gate control signal to the gate driver and to output both resultant data and a data control signal to the data driver; a memory for storing information on point defect information on the liquid crystal display panel, and at least one of horizontal and vertical line defects of the liquid crystal display panel of the liquid crystal display panel; and a data compensation circuit for receiving display data and synchronizing signals, and outputting compensated data to the timing controller based on the information in the memory and uncompensated data to the timing controller.

Description

Video display device with ability to compensate for display defects

The present invention relates to a display device, and more particularly to a video display device having the ability to compensate for display defects. Although embodiments of the present invention are suitable for a wide range of applications, it is particularly suitable to use compensation data to enhance display quality.

Recently, for video display devices, flat display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode have been generally used. ; OLED) and other display devices. Such a video display device is submitted to an inspection process during manufacture to check for display defects that may be present on the display panel. When the display panel is detected to have a defect, a repair process is performed to repair the defective portion of the display panel. However, there may be display defects that cannot be repaired by the repair process.

The deviation of the exposure amount of the overlap exposure in the multiple exposure operation of the exposure apparatus used in the thin film pattern forming process or the color difference of the plurality of lenses used in the exposure apparatus is the main cause of the display defect. In particular, variations in exposure amount cause variations in the width of the thin film pattern, resulting in variations in parasitic capacitance in the thin film transistor, height deviation of the column spacers for maintaining the desired liquid crystal gap, and/or signal display. The deviation of the parasitic capacitance. This deviation leads to display defects in luminance chromatic aberration. These display defects caused by the deviation of the exposure amount are displayed on the display panel in accordance with the scanning direction of the exposure device, and become vertical lines or horizontal lines. However, even if possible It is also difficult to completely eliminate the display defects of these vertical or horizontal line shapes through the improvement of the process technology.

Display defects can also be displayed in the form of point defects in the defective pixels containing foreign matter. Although these defective pixels are submitted to the repair process, they can still contain point defects while in the repaired state. For example, when a defective pixel in the dark pixel form is repaired through a repair process, the dark pixel will be displayed in a white image in the form of a black dot defect. In addition, when the repair process is completed, the pixels that are repaired in the dark pixel form are linked to the adjacent normal pixels, because the data supplied to the normal pixels must be evenly distributed to the repair pixels. Due to the shortage of data charges, the linked pixels are shown as point defects.

For this reason, compensation methods for display defects of circuits have recently been proposed to solve display defects that cannot be eliminated by the physical repair process. However, when a horizontal line data compensation circuit is used to solve a display device having a vertical line display defect, the circuit compensation method of the prior art has a problem, and vice versa, when a vertical line data compensation circuit is applied to a display device having a horizontal line display defect. There is a problem. This is because the horizontal and vertical display defects due to the deviation of the exposure amount are different from each other in terms of luminance distribution and defect position information.

The circuit compensation method of the prior art has not been able to obtain adaptive addition and subtraction compensation values in accordance with the brightness of the associated defect region. The problem is that it is difficult to quantify and systematically compensate the defect area by a method, for example, assuming that the defect area is dark, The medium defect area is compensated for brightness such that the defect area is brighter than the normal area around the defect area, or when the defect area is bright, the normal area is compensated for brightness, so that the normal area becomes brighter. Therefore, the video display device of the prior art requires a data compensation circuit capable of obtaining adaptive addition and subtraction compensation values according to the position of the associated defect region, and can be applied to a video display device having horizontal line display defects and having vertical line display defects. The video display device does not need to consider the type of display defect. In addition, it is desirable that the data compensation circuit has a simple configuration to reduce costs.

Accordingly, embodiments of the present invention provide a video display device capable of compensating for display defects, thereby substantially obviating one or more problems due to limitations and disadvantages of the prior art.

It is an object of embodiments of the present invention to provide a video display device having the ability to compensate for various display defects, using compensation data and having a simple circuit configuration.

The other advantages, objects, and features of the invention will be set forth in part in the description which follows, It is understood or can be derived from the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the <RTIgt;

It will be understood that the general description of the invention as described above and the subsequent The detailed description of the present invention is intended to be illustrative and illustrative of the invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers are used throughout the drawings to refer to the same or equivalent parts.

The "Fig. 1" shows a liquid crystal display device having the ability to compensate for display defects in a representative embodiment of the present invention. The liquid crystal display device shown in "Fig. 1" includes a data compensation circuit 105 and a timing controller 104. The liquid crystal display device further includes a data driver 101 and a gate driver 102, the function of which is to drive the liquid crystal panel 103. The data compensation circuit can be implemented in conjunction with the timing controller 104 in the form of a semiconductor wafer.

The data compensation circuit 105 receives the data Re, Ge, and Be input from the outside of the liquid crystal display device, and receives a plurality of synchronization signals Vsync, Hsync, DE, and DCLK. The data compensation circuit 105 stores information for a typical defect area in the memory, such as a regular horizontal line or a regular vertical line, including position information, gray scale information, and compensation data for a typical defect area. The memory also stores information about the defect area, including location information, grayscale information, and compensation data for the point defect area. The data compensation circuit 105 compensates for the material to be displayed on the typical defect area by the information for the typical defect area, and outputs the compensated data. The data compensation circuit 105 performs data compensation under the condition that the typical defect area is divided into a main area and a boundary area. (first compensation). Thereafter, under the condition that the compensation data of the typical defect area is spatially and temporally dispersed according to the frame rate control (FRC) dithering method, the data compensation circuit 105 finely compensates the data of the typical defect area using the compensation data ( Second compensation). The data compensation circuit 105 also compensates the data of the point defect area using the information of the point defect area, and outputs the compensated data (third compensation). Then, the data compensation circuit 105 supplies the compensated data together with the synchronization signals Vsync, Hsync, DE and DCLK to the implementation controller, wherein the compensated data is the data Rc, Gc and Bc. The data compensation circuit 105 also supplies the data to be displayed on the normal area to the timing controller 104 without compensating for this data. The detailed configuration of the data compensation circuit 105 will be described later.

The timing controller 104 arranges the data Rc, Gc, and Bc input from the data compensation circuit 105, and outputs the resultant data to the data driver 101. Using the synchronization signals Vsync, Hsync, DE, and DCLK, the timing controller 104 generates a data control signal DDC to control the driving timing of the data driver 101 and the gate control signal GDC to control the driving timing of the gate driver 102. Then, the timing controller 104 outputs the data control signal DDC and the gate control signal GDC.

In response to the data control signal DDC from the timing controller 104, the data driver 101 uses the gamma voltage to convert the digital data received from the timing controller 104, that is, the data Rc, Gc, and Bc, into analog data. The data driver 101 outputs analog data to the data lines of the liquid crystal panel 103. In response to the gate control signal GDC from the timing controller 104, the gate driver 102 sequentially drives the gate lines of the liquid crystal panel 103.

The liquid crystal panel 103 displays an image through a pixel matrix in which a plurality of pixels are arranged on the pixel matrix. Using the combination of red, green and blue sub-pixels, the light transmittance is adjusted according to the arrangement of the data signals through the arrangement of the liquid crystals, and each pixel exhibits a desired color. Each sub-pixel includes a thin film transistor (TFT) coupled to a gate line 17 and a data line 16. Each sub-pixel further includes a liquid crystal capacitor Clc and a storage capacitor Cst coupled in parallel to the thin film transistor. The liquid crystal capacitor Clc is charged by using a differential voltage between the data signal supplied to the pixel electrode through the thin film transistor and the common voltage Vcom supplied to the common electrode to drive the liquid crystal according to the charging voltage, thereby adjusting the transmittance of the subpixel . Due to the manufacturing process used, the liquid crystal panel 103 may include a typical defect area and a point defect area of a horizontal or vertical line shape, and the defect area displays data compensated by the data compensation circuit 105. As a result, the difference in luminance between the normal area and the defective area can be avoided, and thus the display quality can be enhanced.

At the same time, the information of the typical defect area and the information of the point defect area which should be stored in advance in the memory of the data compensation circuit 105 are set as follows.

Display defects can be classified into typical defects and point defects, where typical defects are usually displayed regularly in the form of horizontal lines or vertical lines, mainly caused by deviations in exposure amount, which are usually irregular due to the intervention of inclusions. Displayed. In video display devices, such typical defects and point defects are detected in the inspection program. Then, set the compensation data for the typical defect detected and the compensation data for the detected defect. The set compensation data is stored in the memory of the data compensation circuit 105.

In the brightness inspection program of the video display device, when a typical defect in the form of a horizontal line or a vertical line is detected, each of the boundary areas is set according to the type of the typical defect detected and the pollution distribution range of the typical defect area. The width of a subdivision boundary area and the location information for each boundary area. In addition, the degree of contamination of a typical defect area, that is, the difference in brightness or color difference between the normal area and the defective area is measured. Thereafter, the compensation data is set to compensate for the measured luminance difference and color difference.

For example, in the inspection program, the regular vertical line defect area shown in "Fig. 2" or the regular horizontal line defect area shown in "Fig. 3" can be detected as a typical defect of the display device. As shown in Fig. 4, each vertical line defect area can be divided into a main area C1 and a boundary area SG1 and SG2, wherein the main area C1 extends in the vertical direction while displaying fixed brightness, and the boundary areas SG1 and SG2 are symmetrically arranged. The gradually varying brightness is simultaneously exhibited at the opposite sides of the main area C1. As shown in Fig. 5, each horizontal line defect area can be divided into a main area C1 and a boundary area SG1 and SG2, wherein the main area C1 extends in the horizontal direction while displaying a fixed brightness, and the boundary areas SG1 and SG2 are symmetrically arranged. The opposite sides of the main area C1 simultaneously exhibit gradually changing brightness. Each of the boundary regions SG1 and SG2 of each defective region corresponds to a region where the luminance of the main region C1 overlaps with the luminance of the normal region adjacent to the defective region. Each of the boundary regions SG1 and SG2 may be divided into a plurality of boundary regions such that a boundary region of the boundary region SG1 or SG2 is symmetric with respect to a boundary region of the main region C1 and another boundary region SG2 or SG1. When each of the boundary regions SG1 and SG2 is close to the main region C1, each of the boundary regions SG1 and SG2 displays brightness which gradually approaches the brightness of the main region C1, when When each of the boundary areas SG1 and SG2 is close to the normal area, the brightness which gradually approaches the brightness of the normal area is displayed.

The position information of the main area C1 is set in accordance with the start position of the main area C1 and the width of the main area C1. On the other hand, the position information of the boundary areas SG1 and SG2 is automatically set in accordance with the position information of the main area C1, the number of subdivided boundary areas included in each of the boundary areas SG1 and SG2, and the width of each subdivision boundary area. According to the width of the main area C1 and the corresponding compensation data of the main area C1, the number of subdivision boundary areas included in each of the boundary areas SG1 and SG2 and the width of each subdivision boundary area may be within a prescribed range without deviating from the dither pattern. The interior is adjusted to allocate compensation data spatially and temporally.

The compensation data a1 of the main area C1 of the typical defect area is set to compensate for the luminance difference between the main area C1 and the normal area. The compensation data of each of the symmetrically arranged boundary regions SG1 and SG2, that is, the compensation data segments b1 to e1, are automatically set to be gradually reduced in accordance with the order of b1, c1, d1, and e1. Meanwhile, as shown in "Fig. 6," the liquid crystal display device exhibits different gamma voltage characteristics in different gray scale ranges A, B, C, and D. Therefore, each of the compensation data segments a1 to e1 of the typical defect region is set in accordance with different grayscale regions A, B, C, and D exhibiting different gamma characteristics to have different compensation values. Further, the compensation data pieces a1 to e1 of the typical defect area can be set in accordance with the position of the typical defect area to have different compensation values.

Therefore, the information of the typical defects detected in the inspection program, that is, the position information of the typical defects detected, and the position of the typical defects are optimized for each gray scale range. The compensation data, as well as the grayscale range information indicating the grayscale range, are stored in the memory.

In the inspection program, the operation of the checkpoint defect area is also performed. For the detected point defect area, the position information and the best compensation data are set. The set position information and compensation data are stored in the memory. That is to say, the compensation data of the point defect area is optimized for each gray scale range according to the degree of display defect of the point defect area, and the method used is the same as the compensation data method of the optimized vertical or horizontal line defect area used above. The optimized compensation data is then stored in memory. The gray scale information used to represent the gray scale range is also stored in the memory of the display device.

For example, in the inspection program, when a defective defective pixel due to the intervention of the inclusion is detected, the repair operation is performed by separating the bright defective pixel from the relevant signal line, thereby becoming a dark drawing. The prime 10 is coupled to the normal pixel 11 adjacent to the dark pixel 10 through the link pattern 12, as shown in Fig. 7. In this example, the dot defect can be displayed by the link pixel 13, wherein the link pixel 13 contains the normal pixel 11 and the dark pixel 10 which are linked. This is because the data supplied to the normal pixel 11 must even be assigned to the dark pixel 10 linked to the normal pixel 11 to fill the normal pixel 11, so that it is associated with other normal pixels 14 that are not linked to other pixels. In comparison, the data fill amount of the normal pixel 11 is reduced. In order to compensate for the point defect caused by the reduction of the data filling amount, the luminance difference value or the color difference value between the normal pixel and the link pixel 13 is measured, that is, the luminance difference value between the point defect area and the normal area or Color difference. Thereafter, compensation data capable of compensating for the measured luminance difference value or color difference value is set. According to the location of the point defect, the compensation data for the point defect area is also The grayscale range is optimized. The optimized compensation data, together with the location information and grayscale range information of the defect, is stored in the memory.

The "Fig. 8" is a data compensation circuit of the liquid crystal display device of the first embodiment of the present invention. As shown in FIG. 8, the data compensation circuit 105 includes: a memory 40 for storing typical defect information and point defect information; and a first compensator 30 for compensating for a typical defect information stored in the memory 40. The data of the defect area Re, Ge and Be, and the output data Rm1, Gm1 and Bm1 as the compensated data; the second compensator 160, by the frame rate control flutter method, distributes Rm1, Gm1 and Bm1 in space and time, It is used to finely compensate the data Rm1, Gm1, and Bm1 output from the first compensator 30; and the third compensator 170 compensates the material of the point defect area using the point defect information stored in the memory 40. The third compensator 170 is coupled to the second compensator 160. For the data of the normal area, the data compensation circuit 105 outputs the data without any data compensation.

As described above, the memory 40 stores typical defect information of a typical defect area having defects such as vertical line defects and/or horizontal line defects, and the typical defect information includes position information PD1, gray scale range information GD1, and compensation information CD1. The location information PD1 of each typical defect area includes the start position information and the end position information of the defect area, which are respectively represented by the corresponding numbers of the pixels. For example, the position information PD1 of each typical defect area includes a pixel number, which respectively indicates the start position information and the end position information of the subdivision area of each of the main area and the typical defect area included in the typical defect area. . Compensation data CD1 is used to compensate for defective areas and The difference in brightness or color difference between normal areas. The compensation data CD1 is stored after classification according to the corresponding gray scale range and the position of the corresponding defect area. The compensation data CD1 of each typical defect area contains a compensation value which is optimized for the main area of the typical defect area and the subdivision area of each of the typical defect areas, respectively. The gray scale range information GD1 includes a plurality of gray scale range information divided according to the gamma characteristic. The memory 40 also stores point defect information, and the point defect information includes position information PD2 of the point defect area, gray scale range information GD2, and compensation data CD2.

The data compensation circuit 105 further includes a bit expander 20 for expanding the bits of the input data R, G, and B received from the outside of the liquid crystal display device, and supplying the data of the expanded bit to the first compensation. 30. For example, the bit expander 20 adds 3 bits ("000") to 8 bits of input data as low order bits to expand the bits of the input data to 11 bits of data. The bit expander 20 supplies 11 bit data, that is, data Re, Ge, and Be to the first compensator 30.

The first compensator 30 compensates the input data Re, Ge, and Be using the typical defect information PD1, GD1, and CD1 stored in the memory 40, and outputs the compensated data, wherein the input materials Re, Ge, and Be are displayed in a vertical Above the typical defect area of defects such as line defects or horizontal line defects. The first compensator 30 performs data compensation by adding the compensation data PD1 corresponding to the data of the typical defect area to the data of the typical defect area or subtracting the data of the typical defect area. For the data of the normal area, the first compensator 30 outputs the data without any data compensation.

Use frame rate control flutter method to distribute data in space and time Rm1, Gm1 and Bm1, the second compensator 160 finely compensates the compensated data Rm1, Gm1 and Bm1 output by the first compensator 30. When the compensation data for each boundary region in the typical defect region is spatially and temporally allocated according to the frame rate control dithering method, the luminance difference value of the boundary region is finely compensated. For example, the second compensator 160 spatially and temporally distributes the compensation data supplied to the low-order bit portion of the data Rm1, Gm1, and Bm1 output by the first compensator 30 using the dither pattern. As a result, the difference in luminance between the typical defective area and the normal area can be finely compensated.

The third compensator 170 compensates the data Rm2, Gm2, and Bm2 using the point defect information PD2, GD2, and CD2 stored in the memory 40, wherein the data Rm2, Gm2, and Bm2 will be displayed above the point defect area. For the data of the normal area, the third compensator 170 outputs the data without any data compensation.

The "Fig. 9" is a schematic view of the first compensator 30 and the memory 40 shown in Fig. 8. As shown in FIG. 9, the first compensator 30 includes a vertical line compensator 70 and a horizontal line compensator 80, so that the first compensator 30 can be applied to a display device having a vertical line display defect or having a horizontal line display defect. The display device is independent of the type of display defect. The first compensator 30 also includes a multiplexer (MUX) 90 for selecting the output of the vertical line compensator 70 or the output of the horizontal line compensator 80 for vertical line defects or horizontal line defects in accordance with typical defects detected.

The memory 40 includes a first memory 42V coupled to the vertical line compensator 70 and storing vertical line defect information; and a second memory 42H coupled to the horizontal line compensation 80 stores horizontal line defect information. The first memory 42V includes: an electrically-erasable programmable read only memory (EEPROM) 44V for storing position information PD1V, grayscale range information GD1V, and compensation data of a vertical line defect area. CD1V; and a register 46V for temporarily storing the data PD1V, GD1V and CD1V stored in the electrically erasable stylized read-only memory 44V, and supplying the temporarily stored data to the vertical line compensator 70. The second memory 42H includes an electrically rewritable stylized read-only memory 44H for storing position information PD1H of the horizontal line defect area, gray scale range information GD1H, and compensation data CD1H; and a register 46H for temporarily The storage rewritable data PD1H, GD1H, and CD1H stored in the stylized read-only memory 44H, and supplies the temporarily stored data to the horizontal line compensator 80. The two electrically rewritable stylized read-only memories 44V and 44H can be implemented by a single electrically rewritable stylized read-only memory. In addition, the two register registers 46V and 46H can also be implemented by a single register. At the position of the electrically rewritable stylized read-only memory 44V and 44H, an extended display identification data ROM (EDIDROM) can also be used for storing, for example, the resolution of the display device. News. In this example, the partially extended display identification material read-only memory can be appropriately assigned the function of electrically rewritable stylized read-only memory. One of the electrically rewritable stylized read-only memories 44V and 44H can also store control information CS at its particular address. The control information CS includes: typical defect direction information, which is used to indicate that the defect type of a typical defect area is a vertical line defect or a horizontal line defect; a typical defect The compensation demand/no demand information is used to indicate whether there is a typical defect area, thereby indicating whether the compensation of the typical defect area is required; and the point defect compensation requirement/no demand information is used to indicate whether the compensation of the point defect area is required. For example, in a byte allocated for the control information CS, the elements of the 3-bit data may represent three pieces of information. At the same time, the three select pin values included in the timing controller 104 can set the control information CS in which the data compensation circuit 105 is combined.

To compensate for the input data Re, Ge, and Be to be displayed above the vertical line defect area, the vertical line compensator 70 includes a gray scale determiner 72, a position determiner 74, a compensation data selector 76, and a calculator 78.

The gray scale determiner 72 analyzes the gray scale levels of the input data Re, Ge, and Be, and selects the input data Re, Ge, and Be from the gray scale range information GD1V read from the first memory 42V according to the analyzed gray scale level. Corresponding to the gray scale range information, and outputting the selected gray scale range information to the compensation data selector 76. For example, the grayscale range information GD1V may include three grayscale range information segments corresponding to three grayscale ranges divided by 256 grayscale ranges according to gamma characteristics, for example, the first grayscale range is from 30 to 70, and the second The gray scale ranges from 71 to 150, and the third gray scale ranges from 151 to 250. The gray scale determiner 72 selects gray scale range information including gray scale levels of the input data Re, Ge, and Be from the three gray scale range information segments, and outputs the selected gray scale range information.

Using at least one of the vertical sync signal Vsync, the horizontal sync signal Hsync, the data enable signal DE, and the dot clock DCLK, the position determiner 74 determines the input data. The position of the pixels in the horizontal direction of Re, Ge, and Be. For example, the position determiner 74 determines the horizontal pixel position of the input data Re, Ge, and Be while counting the pulse of the dot clock DCLK during the energizing period of the data enable signal DE. Then, the position determiner 74 compares the determination horizontal pixel position of the input data Re, Ge, and Be with the vertical line defect area position information PD1V read from the first memory 42V to detect whether the defective area is a vertical line defect area. . When the detection area is detected as the vertical line defect area, the position determiner 74 selects the corresponding position information of the defective area from the position information PD1V, and outputs the selected position information to the compensation data selector 76.

The compensation data selector 76 selects the corresponding compensation data of each of the input data Re, Ge, and Be from the compensation data CD1V read from the first memory 42V in response to the gray scale range information and position determination selected by the gray scale determiner 72. The location information selected by the device 74. In other words, the compensation data selector 76 selects the compensation data corresponding to the position information of the position determiner 74 from the corresponding gray scale range selected in accordance with the gray scale range information of the gray scale determiner 72, and outputs the selected compensation data. When the position information indicates the main area of the vertical line defect area, the compensation data for compensating the main area is selected and output. On the other hand, when the position information indicates the subdivision area of the boundary area of the vertical line defect area, the compensation data for compensating the subdivision area is selected and output.

By adding or subtracting the associated compensation data outputted from the compensation data selector 76 for each of the input data Re, Ge, and Be, the calculator 78 compensates the input data Re, Ge, and Be to be displayed above the vertical line defect area, and outputs Compensation data. For example, by adding or subtracting compensation data to the 11-bit input data Re, Ge, and Be The corresponding 8-bit compensation data outputted in the selector 76, the calculator 78 compensates each of the input data Re, Ge, and Be, and outputs the compensated data.

To compensate for the input data Re, Ge, and Be to be displayed above the horizontal line defect area, the horizontal line compensator 80 includes a gray scale determiner 82, a position determiner 84, a compensation material selector 86, and a calculator 88.

The gray scale determiner 82 analyzes the gray scale levels of the input data Re, Ge, and Be, and selects the input data Re, Ge, and Be from the gray scale range information GD1H read from the second memory 42H according to the analyzed gray scale level. Corresponding to the gray scale range information, and outputting the selected gray scale range information to the compensation data selector 86.

At least one of the position determiners 84 determines the pixel positions of the input data Re, Ge, and Be in the vertical direction using the vertical sync signal Vsync, the horizontal sync signal Hsync, the data enable signal DE, and the dot clock DCLK. For example, the position determiner 84 determines the vertical pixel positions of the input data Re, Ge, and Be, and simultaneously counts the pulses of the horizontal sync signal Hsync in the period in which the vertical sync signal Vsync and the data enable signal DE are energized. Then, the position determiner 84 compares the determined vertical pixel position of the input data Re, Ge, and Be with the horizontal line defect area position information PD1H read from the second memory 42H to detect whether the defective area is a horizontal line defect area. When the detection area is detected as the horizontal line defect area, the position determiner 84 selects the corresponding position information of the defective area from the position information PD1H, and outputs the selected position information to the compensation data selector 86.

The compensation data read by the compensation data selector 86 from the second memory 42H The corresponding compensation data of each of the input data Re, Ge, and Be is selected in the CD1H in response to the grayscale range information selected by the grayscale determiner 82 and the positional information selected by the position determiner 84. When the position information indicates the main area of the horizontal line defect area, the compensation data for compensating the main area is selected and output. On the other hand, when the position information indicates the subdivision area of the boundary area of the horizontal line defect area, the compensation material for compensating the subdivision area is selected and output.

By adding or subtracting the associated compensation data output by the compensation data selector 86 for each of the input data Re, Ge, and Be, the calculator 88 compensates the input data Re, Ge, and Be to be displayed above the horizontal line defect area, and the output is Compensation information.

The multiplexer 90 selects the output data of the vertical line compensator 70 or the output data of the horizontal line compensator 80 in response to the typical defect direction information contained in the control information CS. That is, when the typical defect direction information indicates a vertical line defect, the multiplexer 90 selectively outputs the output data of the vertical line compensator 70. On the other hand, when the typical defect direction information indicates a horizontal line defect, the multiplexer 90 selectively outputs the output data of the horizontal line compensator 80.

Therefore, the first compensator 30 compensates the input data Re, Ge, and Be having typical defect regions such as vertical line defects or horizontal line defects in response to the control information CS, and outputs the compensated data.

The "10th figure" is the second compensator 160 shown in "Fig. 8". As shown in FIG. 10, the second compensator 160 includes a frame determiner 162, a pixel position determiner 164, a flutter value selector 166, and an adder 168.

The frame determiner 162 counts the pulses of the vertical sync signal Vsync selected from the plurality of sync signals Vsync, Hsync, DE, and DCLK supplied from the first compensator 30 to detect the number of frames. The frame determiner 162 outputs information indicating the number of detected frames to the jitter value selector 166.

Using at least one of the sync signals Vsync, Hsync, DE, and DCLK, the pixel position determiner 164 detects the pixel positions of the input data Rm1, Gm1, and Bm1. For example, the pixel position determiner 164 determines the horizontal pixel position of the input data Rm1, Gm1, and Bm1, and simultaneously counts the pulse of the dot clock DCLK in the energizing period of the data enable signal DE, and determines the input data Rm1, Gm1, and Bm1. The vertical pixel position, while counting the pulse of the horizontal synchronization signal Hsync in the period in which the vertical sync signal Vsync and the data enable signal DE are both enabled. The pixel position determiner 164 outputs information indicating the position of the detected pixel to the jitter value selector 166.

The compensation data applied in the first compensator 30, that is, the corresponding gray level of each low order bit of the output data Rm1, Gm1, and Bm1 of the first compensator 30, the frame number information output by the frame determiner 162, and the drawing are used. The pixel position information output by the prime position determiner 164, the jitter value selector 166 selects the desired jitter values Dr, Dg, and Db from the plurality of wobbling patterns.

The dither value selector 166 includes a plurality of dither patterns previously stored by the designer in the dither value selector 166. For example, as shown in "11A", "11B", "11C" and "11D", the jitter value selector 166 stores a plurality of dither patterns each having a matrix size of 8x32. According to 0, 1/8, 2/8, 3/8, The grayscale levels of 4/8, 5/8, 6/8, 7/8, and 1 are respectively arranged to include a gradually increasing number of pixels having a "1" (black) jitter value (the grayscale level is The dither pattern of 1 is not shown). The tremor pattern is stored in the form of a look-up table. Each pixel of each dither pattern has a jitter value of "1" (black) or "0" (white). The grayscale level of each dither pattern is determined according to the number of pixels having a "1" dither value. For each grayscale level, a plurality of dither patterns are stored, wherein the dither patterns differ for pixel positions having different "1" dither values for different frames. That is, a plurality of dither patterns are stored, wherein the dither pattern is respectively for a plurality of different frames FRAME1 to FRAME8 depending on the position of the pixel having the "1" dither value. In other words, the dither value selector 166 stores a plurality of different dither patterns for each grayscale level and each frame. The size of the dither pattern and the position of the pixel having a "1" dither value in each dither pattern may vary according to the designer's needs. Since the compensation data applied to the typical defect area in the first compensator 30 is spatially and temporally distributed using the above-described dither pattern, it is possible to finely compensate the luminance difference value of the typical defect area.

Each of the data Rm1, Gm1, and Bm1 output by the first compensator 30 includes 11 bits, and the dither value selector 166 selects a dither value using the 3-bit low order bit in each of the 11-bit data, and outputs the remaining 8-bit to adder 168. In this example, the 3-bit data is the data portion to which the compensation data is supplied in the first compensator 30. The 3-bit data portion corresponding to the normal area is set to "000". The jitter value selector 166 selects a wobbling pattern from the wobbling patterns shown in "11A", "11B", "11C", and "11D", and the dither pattern corresponds to each input. The gray scale level represented by the low order 3 bits of the data Rm1, Gm1, and Bm1 and the frame number information output by the frame determiner 162. Then, using the pixel position information from the pixel position determiner 164, the dither value selector 166 selects 1-bit dither values Dr, Dg, and Db from the selected dither pattern, the 1-bit dither values Dr, Dg, and Db. Corresponding to the pixel positions of the input data Rm1, Gm1 and Bm1. The dither value selector 166 outputs the selected dither values Dr, Dg, and Db to the adder 168.

The adder 168 increments each of the flutter values Dr, Dg, or Db selected by the flutter value selector 166 to the high order bit 8 bits of the corresponding data Rm1, Gm1, and Bm1 from which the low order bit 3 bits are separated. Then, the adder 168 outputs the result data as the data Rm2, Gm2, and Bm2.

Therefore, the second compensator 160 spatially and temporally distributes the compensated data portions of the data Rm1, Gm1, and Bm1 output by the first compensator 30 using the frame rate control flutter method to more finely compensate the luminance difference of the typical defect regions. Value, thereby preventing degradation of display quality caused by compensation data.

The "Fig. 12" is a schematic view of the third compensator 170 shown in Fig. 8. As shown in FIG. 12, the third compensator 170 includes a gray scale determiner 172, a position determiner 174, a compensation data selector 176, and a calculator 178. Each of the defect information PD2, GD2, and CD2 for compensating the point defect area is stored in one of the first and second memories 42V and 42H.

The gray scale determiner 172 analyzes the gray scale levels of the input data Rm2, Gm2, and Bm2 of the link pixels to be supplied to the point defect area, according to the gray scale level of the analysis, Selecting gray scale range information of the input data Rm2, Gm2, and Bm2 from the gray scale range information GD2 read from one of the first and second memories 42V and 42H, and outputting the selected gray scale range information to the compensation data selection 176.

The position determiner 174 determines the pixel positions of the input data Rm2, Gm2, and Bm2 using at least one of the vertical sync signal Vsync, the horizontal sync signal Hsync, the data enable signal DE, and the dot clock DCLK input from the external system. For example, the position determiner 174 determines the horizontal pixel position of the input data Rm2, Gm2, and Bm2, and simultaneously counts the pulse of the midpoint clock DCLK of the energizing period of the data enable signal DE, and determines the vertical drawing of the input data Rm2, Gm2, and Bm2. The prime position simultaneously counts the pulse of the horizontal sync signal Hsync in the period in which the vertical sync signal Vsync and the data enable signal DE are both enabled. Then, the pixel position determiner 174 compares the determined pixel positions of the input data Rm2, Gm2, and Bm2 with the point defect position information PD2 read from one of the first and second memories 42V and 42H to detect this. Whether the detection area is a point defect area. When the detection area is detected as a point defect area, the position determiner 174 outputs information for indicating the position of the pixel to the compensation material selector 176.

The compensation data selector 176 selects the corresponding compensation data of each of the input data Rm2, Gm2, and Bm2 from the compensation data CD2 read from the first memory 42V and the second memory 42H in response to the gray selected by the grayscale determiner 172. The range information and the position information selected by the position determiner 174. The compensation data selector 176 then outputs the selected compensation material.

The calculator 178 adds the compensation data output from the compensation data selector 176 to the input data Rm2, Gm2, and Bm2, or subtracts the compensation data output from the compensation data selector 176 from the input data Rm2, Gm2, and Bm2, and outputs the result data. .

Therefore, the third compensator 170 compensates the materials Rm2, Gm2, and Bm2 of the point defect area, and outputs the compensated data.

As apparent from the above description, in the data compensation circuit of the first embodiment of the present invention, the luminance difference of the typical defect region is compensated by selecting one of the outputs of the vertical line compensator 70 and the horizontal line compensator 80, and the vertical line compensator 70 The horizontal line compensator 80 uses the separate memories 42V and 42H, respectively, in accordance with the associated typical defect direction information. In the data compensation circuit of the first embodiment of the present invention, the luminance difference value of the boundary region of the typical defect region is spatially and temporally distributed using the second compensator 160 to the data of the first compensator 30 applied to the typical defect region. The compensation data is finely compensated. In addition, the luminance difference value of the point defect area can also be compensated using the third compensator 170.

Fig. 13 is a data compensation circuit of the liquid crystal display device of the second embodiment of the present invention. As shown in Fig. 13, the data compensation circuit includes: a memory for storing typical defect information PD1, CD1 and GD1 and point defect information PD2, CD2 and GD2; the first compensator 110 is stored using the memory 100 The defect information PD1, CD1, and GD1 compensates the data Re, Ge, and Be of the typical defect area, and outputs the data Rm1, Gm1, and Bm1 as compensated data; the second compensator 160, Using the frame rate control flutter method, the data Rml, Gml, and Bml output by the first compensator 110 are finely compensated by distributing the data Rml, Gml, and Bml in space and time; and the third compensator 170 uses the memory The point defect information PD2, CD2, and GD2 stored in 100 compensates for the defect area information.

The first compensator 110 shown in Fig. 13 is different from the first compensator 30 shown in Fig. 9, because the vertical line compensator 120 and the horizontal line compensator 140 of the first compensator 110 share a memory with each other. Body 100.

Since the display panel is divided into a type that generates a vertical line defect and a type that generates a horizontal line defect, according to the scanning direction of the exposure device, the display device using the display panel corresponding to the two types only uses the vertical line defect information and the horizontal line defect information. one. Therefore, according to an embodiment of the present invention, the parameters used in the vertical line defect information and the parameters used in the horizontal line defect information are unified, and the vertical line defect information or the horizontal line defect information is stored in a single for the vertical line defect information and the horizontal line defect information. The same address of the memory 100. After accessing the same address of the single memory 100, although the vertical line compensator 120 and the horizontal line compensator 140 are driven in parallel, the data compensated by the vertical line compensator 120 or the data compensated by the horizontal line compensator 140 is in accordance with the display device. Typical defects are output as vertical line defects or horizontal line defects. As a result, the data compensation circuit of the embodiment of the present invention can reduce the number of uses of the memory as compared with the example in which the vertical line compensator 120 and the horizontal line compensator 140 respectively use independent memories. Using a single memory may reduce memory compared to the case where vertical line defect data and horizontal line defect information are stored separately at different addresses. Capacity.

The memory 100 includes: an electrically rewritable stylized read-only memory for storing typical defect information PD1, CD1 and GD1 and point defect information PD2, CD2 and GD2; and a temporary memory for temporarily storing the electrically erasable Programmatically read only the data stored in the memory and output the temporarily stored data. The parameters used in the vertical line defect area and the parameters used in the horizontal line defect area can be unified. Further, the vertical line defect area information or the horizontal line defect area is stored in the same address of the memory 100 for the vertical line defect data and the horizontal line defect information. For example, the address information PD1 of each of the vertical line defect area and the horizontal line defect area is represented by the corresponding number of pixels. Typical defect direction information for determining whether a typical defect of a defective area is a vertical line defect or a horizontal line defect is stored in a special address of the memory 100. Typical defect direction information can also be represented using the select pins of the timing controller in which the data compensation circuits are combined. For example, typical defect direction information can be set to '0' to indicate a vertical line defect, which can be set to '1' to indicate a horizontal line defect. The typical defect direction information corresponds to "0", and the address information PD1 stored in the memory 100 is set using the number of pixels allocated in the horizontal line resolution range to respectively indicate the position of the vertical line defect area. On the other hand, the typical defect direction information corresponds to "1", and the address information PD1 stored in the memory 100 is set using the number of pixels allocated in the vertical line resolution range to respectively indicate the position of the horizontal line defect area. In other words, according to the typical defect direction information set in the memory 100, the position information PD1 of the typical defect area indicates the position of the vertical line defect area or the position of the horizontal line defect area.

At the same time, the typical defect area can be displayed in a state brighter than the normal area as shown in "Fig. 14", as shown in "Fig. 15", which is darker than the normal area, or as shown in Fig. 16. Both the bright defect area and the dark defect area shown are represented as states of a typical defect area. The compensation data for displaying the defect is added to or subtracted from the input data to compensate for the brightness according to the display defect corresponding to the bright defect area or the dark defect area. For this reason, in accordance with the order of typical defect regions, luminance information for indicating whether a typical defect region corresponds to a bright defect or a dark defect is stored in the memory 100 for a typical defect region. In other words, the control information CS1 including the brightness information of each typical defect area and the order information of the typical defect area is stored in a special position of the memory 100 to classify the typical defect area as a defect area brighter than the normal area or more than the normal area. Dark defect areas, as shown in Figure 14, Figure 15, and Figure 16. For example, the 3-bit of a byte allocated for the control information CS1 indicates the information of the order of the associated typical defect area, and the 1-bit of the assigned byte represents the brightness information, and the brightness information is used to indicate that the associated typical defect is Bright or dark defects.

In addition, the type of defect used to represent a typical defect area is typical defect direction information of a vertical line defect or a horizontal line defect, and a typical defect compensation area/no demand information indicating whether a typical defect area exists to indicate whether it is necessary to compensate for a typical defect area. And the point defect compensation demand/no demand information for indicating whether the point defect area needs to be compensated can be stored at the same address as the control information CS2. For example, the bits of the 3-bit data in a byte allocated for the control information CS2 may be Indicates three pieces of information.

At the same time, the control information CS1 and CS2 can be set through the selection pin values included in the timing controller 104, and the data compensation circuit 105 is combined therein.

The data Re, Ge, and Be of the bit expansion elements of the bit expander 20 shown in "Fig. 8" are input to the first compensator 110. Using the typical defect information PD1, GD1 and CD1 stored in the memory 100, the first compensator 110 compensates the input data Re, Ge, and Be to be displayed over the typical defect area of the vertical line or the typical defect area of the horizontal line, and the output is compensated. data. In other words, the first compensator 110 compensates the main region C1 included in the typical defect region and the input data Re, Ge, and Be of the boundary regions SG1 and SG2 in response to the typical defect information PD1, CD1, and GD1 in the memory 100, and outputs Compensation data. For the input data of the normal area, the first compensator 110 outputs the data without any data compensation.

In detail, the first compensator 110 includes: a vertical line compensator 120 that uses the position information PD1 in the memory 100 as the position information of the vertical line defect area to compensate the input data Re, Ge, and Be, and outputs the compensated data; The compensator 140 uses the position information PD1 of the memory 100 as the position information of the horizontal line defect area for compensating the input data Re, Ge, and Be, and outputs the compensated data; and the multiplexer 160 is included in the control information CS2. The typical defect direction information is used to select the output data of the vertical line compensator 120 or the output data of the horizontal line compensator 140. The first compensator 110 drives the vertical line compensator 120 and the horizontal line compensator 140 in parallel, wherein the vertical line compensator 120 and the horizontal line compensator 140 share each other The memory 100 performs vertical line compensation and horizontal line compensation for the input data Re, Ge, and Be at the same time. Then, the first compensator 110 selects the output data of the vertical line compensator 120 or the output data of the horizontal line compensator 140 through the multiplexer 160, and outputs the selected data.

The vertical line compensator 120 includes a gray scale determiner 122, a position determiner 124, a compensation data selector 126, an adder 128, a subtractor 130, and multiplexers 132 and 134.

The gray scale determiner 122 analyzes the respective gray scale levels of the input data Re, Ge, and Be, and selects the correspondence of the input data Re, Ge, and Be from the gray scale range information GD1 read from the memory 100 according to the analyzed gray scale level. Gray scale range information, and the selected gray scale range information is output to the compensation data selector 126.

Using at least one of the vertical sync signal Vsync, the horizontal sync signal Hsync, the data enable signal DE, and the dot clock DCLK, the position determiner 124 determines the pixel positions of the input data Re, Ge, and Be in the horizontal direction. For example, the position determiner 124 determines the horizontal pixel position of the input data Re, Ge, and Be, and simultaneously counts the pulse of the midpoint clock DCLK of the energizing period of the data enable signal DE. Then, the position determiner 124 compares the determination horizontal pixel position of the input data Re, Ge, and Be with the vertical line defect area position information PD1 read from the memory 100 to detect whether the defective area is a vertical line defect area. When the defective area is detected as the vertical line defect area, the position determiner 124 selects the corresponding position information of the defective area from the position information PD1, and outputs the selected position information to the compensation data selector 126.

The compensation data selector 126 reads the compensation data CD1 from the memory 100. The corresponding compensation data of each input data Re, Ge and Be is selected in response to the gray scale range information selected by the gray scale determiner 122 and the position information selected by the position determiner 124. In other words, the compensation data selector 126 selects compensation information corresponding to the position information of the position determiner 124 and the corresponding gray scale range selected in accordance with the gray scale range information of the gray scale determiner 122, and outputs the selected compensation data. When the position information indicates the main area of the vertical line defect area, the compensation data for compensating the main area is selected and output. On the other hand, when the position information indicates the subdivision area of the boundary area of the vertical line defect area, the compensation data for compensating the subdivision area is selected and output.

The adder 128 adds the compensation data output from the compensation data selector 126 to the input data Re, Ge, and Be, and outputs the resultant data. The subtracter 130 subtracts the compensation data output from the compensation data selector 126 from the input data Re, Ge, and Be, and outputs the resultant data.

In accordance with the brightness of the typical defective area, the multiplexer 134 selects the output data of the adder 128 or the output data of the subtractor 130, and outputs the selected material. In accordance with the sequence of typical defect regions, the multiplexer 132 sequentially outputs luminance information of a typical defect region to control the multiplexer 134, wherein the multiplexer 134 selects the output data of the adder 128 or the output data of the subtractor 130. The typical defect area luminance information is stored in the memory 100 together with the typical defect area order information as the control information CS1. The control information CS1 read from the memory 100 is repeatedly supplied to the multiplexer 132 in accordance with the number of typical defective areas. The multiplexer 132 selects the control information CS1, and The selected control information CS1 to multiplexer 134 is supplied, wherein the control information CS1 corresponds to the order of the vertical line defect areas detected by the position determiner 124, that is, the vertical line defect area order Vm. Therefore, in accordance with the luminance information contained in the control information CS1 supplied from the multiplexer 132, the multiplexer 134 selects the output of the adder 128 or the output of the subtractor 130, and supplies the selected output to the multiplexer 156.

The horizontal line compensator 140 includes a gray scale determiner 142, a position determiner 144, a compensation data selector 146, an adder 148, a subtractor 150, and multiplexers 152 and 154. The horizontal line compensator 140 has the same circuit configuration as the vertical line compensator 120 except for the position determiner 144.

The gray scale determiner 122 analyzes the respective gray scale levels of the input data Re, Ge, and Be, and selects the correspondence of the input data Re, Ge, and Be from the gray scale range information GD1 read from the memory 100 according to the analyzed gray scale level. Gray scale range information, and the selected gray scale range information is output to the compensation data selector 146.

Using at least one of the vertical sync signal Vsync, the horizontal sync signal Hsync, the data enable signal DE, and the dot clock DCLK, the position determiner 144 determines the pixel positions of the input data Re, Ge, and Be in the vertical direction. For example, the position determiner 144 determines the vertical pixel position of the input data Re, Ge, and Be, and simultaneously counts the pulse of the horizontal synchronization signal Hsync in the period in which both the vertical synchronization signal Vsync and the data enable signal DE are energized. Then, the position determiner 144 compares the vertical pixel positions of the determined input data Re, Ge, and Be with the typical defect area position information PD1 read from the memory 100 to detect whether the defective area is a typical defective area. when When the defective area is detected as a typical defective area, the position determiner 144 selects the corresponding position information of the defective area from the position information PD1, and outputs the selected position information to the compensation data selector 146.

The compensation data selector 146 selects the corresponding compensation data of each of the input data Re, Ge, and Be from the compensation data CD1 read by the memory 100 in response to the grayscale range information selected by the grayscale determiner 142 and the position determiner 144. Location information.

The adder 148 adds the compensation data output from the compensation data selector 146 to the input data Re, Ge, and Be, and outputs the resultant data. The subtracter 150 subtracts the compensation data output from the compensation data selector 146 from the input data Re, Ge, and Be, and outputs the resultant data.

In accordance with the luminance information of the typical defective area included in the control information CS1, the multiplexer 154 selects the output data of the adder 148 or the output data of the subtractor 150, and outputs the selected data.

The multiplexer 132 selects the control information CS1 read from the memory 100 in accordance with the order of the typical defect areas detected by the position determiner 144, that is, the typical defect area order Hm, and supplies the selected control information CS1 to the multiplexer 154. Therefore, the multiplexer 154 can select the output of the adder 148 or the output of the subtractor 150 in accordance with the luminance information contained in the control information CS1 supplied from the multiplexer 152. The multiplexer 154 then supplies the selected output to the multiplexer 156.

The multiplexer 156 selects the output data of the vertical line compensator 120 or the output data of the horizontal line compensator 140 in response to the typical defect direction included in the control information CS2. News. That is, when the typical defect direction information indicates a vertical line defect, the multiplexer 156 selectively outputs the output data of the vertical line compensator 120. On the other hand, when the typical defect direction information indicates a horizontal line defect, the multiplexer 156 selectively outputs the output data of the horizontal line compensator 140.

Therefore, using the typical defect area information PD1, CD1, and GD1 stored in the single memory 100, the first compensator 110 compensates the input data Re, Ge, and Be of a typical defect area having a vertical line defect or a horizontal line defect, and outputs the compensation data. .

The second compensator 170 finely compensates the compensation data Rm1, Gm1, and Bm1 output by the first compensator 110 by distributing the data Rm1, Gm1, and Bm1 in space and time using the frame rate control flutter method. Since the compensation data of the boundary region of each typical defect region is spatially and temporally distributed according to the frame rate control flutter method, the luminance difference value of each boundary region is finely compensated.

Using the point defect information PD2, GD2, and CD2 stored in the memory 100, the third compensator 180 compensates the data Rm2, Gm2, and Bm2 to be displayed above the point defect area. Corresponding to the data of the normal area, the third compensator 170 outputs the data without any data compensation.

As apparent from the above description, in the data compensation circuit according to the second embodiment of the present invention, it is possible to compensate the luminance difference of the typical defect region by selecting one of the outputs of the vertical line compensator 120 and the horizontal line compensator 140 in accordance with the associated typical defect direction information. The values, the vertical line compensator 120 and the horizontal line compensator 140 share a single memory 100 with each other while reducing the capacity of the memory 100. The information of the second embodiment of the present invention is supplemented In the compensation circuit, the brightness difference value of the typical defect area may be appropriately compensated by performing the addition or subtraction of the compensation data according to the typical defect area as the bright defect area or the dark defect area.

Fig. 17 is a data compensation circuit of a liquid crystal display device of a third embodiment of the present invention. As shown in FIG. 17, the data compensation circuit includes: a memory 100 for storing typical defect information PD1, CD1 and GD1 and point defect information PD2, CD2 and GD2; and a first compensator 220 for using the memory 100 The stored typical defect information PD1, CD1 and GD1 are used to compensate the data Re, Ge and Be of the typical defect area, and the output data Rm1, Gm1 and Bm1 are used as compensation data; the second compensator 160 uses the frame rate control flutter method, By distributing the data Rm1, Gm1, and Bm1 in space and time for finely compensating the data Rm1, Gm1, and Bm1 output by the first compensator 220; and, the third compensator 170, using the point defect stored in the memory 100 The information PD2, CD2 and GD2 compensates for the compensation data of the defect area. The third compensator 170 is coupled to the second compensator 160.

The first compensator 220 shown in Fig. 17 is different from the first compensator 110 shown in Fig. 13 because the first compensator 220 has a single compensator configuration for performing horizontal or vertical line defects. Data compensation.

The memory 100 includes: an electrically rewritable stylized read-only memory storing typical defect information PD1, CD1 and GD1 and point defect information PD2, CD2 and GD2; and a temporary memory for temporarily storing the electrically rewritable program Read only the data stored in the memory and output the temporarily stored data. For vertical line curve area information and The horizontal line defect area information, the vertical line defect area information or the horizontal line defect area information are stored at the same address of the memory 100. The control information CS1 including the brightness information of the typical defect area together with the sequence information of the typical defect area can also be stored in the memory 100. In addition, the type of defect used to represent a typical defect area is typical defect direction information of a vertical line defect or a horizontal line defect, and a typical defect compensation area/no demand information indicating whether a typical defect area exists to indicate whether it is necessary to compensate for a typical defect area. And the point defect compensation demand/no demand information for indicating that the oath needs the point defect area can be stored in the memory 100 as the control information CS2.

The data Re, Ge, and Be of the bit expansion of the bit expander 20 shown in "Fig. 8" are input to the first compensator 220. Using the typical defect information PD1, GD1 and CD1 accessed in the memory 100, the first compensator 220 compensates the input data Re, Ge, and Be to be displayed on the typical defect area of the vertical line or the typical defect area of the horizontal line, and outputs the output. Compensation information. In other words, the first compensator 220 compensates the main region C1 included in the typical defect region and the input data Re, Ge, and Be of the boundary regions SG1 and SG2 in response to the typical defect information PD1, GD1, and CD1 of the memory 100, and the output is Compensation information. For the input data of the normal area, the first compensator 220 outputs the data without any data compensation.

The first compensator 220 includes a gray scale determiner 222, a position determiner 224, a compensation data selector 226, an adder 228, a subtractor 230, and multiplexers 232 and 234.

The gray scale determiner 222 analyzes the respective gray scale levels of the input data Re, Ge, and Be, According to the gray scale level of the analysis, the corresponding gray scale range information of the input data Re, Ge, and Be is selected from the gray scale range information GD1 read by the memory 100, and the selected gray scale range information is output to the compensation data selector 126.

Using at least one of the vertical sync signal Vsync, the horizontal sync signal Hsync, the data enable signal DE, and the dot clock DCLK, the position determiner 224 determines the pixel positions of the input data Re, Ge, and Be in the horizontal direction or the vertical direction.

In detail, as shown in FIG. 18, the position determiner 224 includes: a first position determiner 322 for determining a pixel address of the input data Re, Ge, and Be in the horizontal direction; and a second position determiner 324 a pixel address for determining the input data Re, Ge, and Be in the vertical direction; and a multiplexer for selecting the output of the first position determiner 322 or the second position determination according to the typical defect direction information included in the control information CS2. The output of the 324.

The first position determiner 322 determines the horizontal pixel address of the input data Re, Ge, and Be, and simultaneously counts the pulse of the dot clock DCLK in the energizing period of the data enable signal DE. Then, the first position determiner 322 compares the horizontal pixel positions of the determined input data Re, Ge, and Be with the typical defect area position information PD1 read in the memory 100 to detect whether the defective area is a typical defective area. When the defective area is detected as a typical defective area, the first position determiner 322 selects the corresponding position information of the defective area from the position information PD1, and outputs the selected position information to the multiplexer 326.

The second position determiner 324 determines the vertical pixels of the input data Re, Ge, and Be. The position is simultaneously counted by the horizontal synchronization signal Hsync during the period in which the vertical sync signal Vsync and the data enable signal DE are both enabled. Then, the second position determiner 324 compares the vertical pixel positions of the determined input data Re, Ge, and Be with the typical defect area position information PD1 read from the memory 100 to detect whether the defective area is a typical defective area. When the defective area is detected as a typical defective area, the second position determiner 324 selects the position information for the defective area from the position information PD1, and outputs the selected position information to the multiplexer 326.

The multiplexer 326 supplies the typical defect area position information input by the first position determiner 322 or the second position determiner 324 to the compensation data selector 226 in accordance with the typical defect reversal information contained in the control information CS2.

The compensation data selector 226 selects the corresponding compensation data of each of the input data Re, Ge, and Be from the compensation data CD1 read from the memory 100 in response to the grayscale range information and the position determiner 224 selected by the grayscale determiner 222. Location information selected.

The adder 228 adds the compensation data output from the compensation data selector 226 to the input data Re, Ge, and Be, and outputs the resultant data. The subtracter 230 subtracts the compensation data output from the compensation data selector 226 from the input data Re, Ge, and Be, and outputs the resultant data.

The multiplexer 234 selects the output of the adder 228 or the output of the subtractor 230 in accordance with the brightness of the typical defective area, and supplies the selected data to the second compensator 160.

In accordance with the sequence of typical defect regions, multiplexer 232 sequentially outputs luminance information of a typical defect region to control multiplexer 234, wherein multiplexer 234 selects an adder The output of 228 or the output of subtractor 230. The typical defect area luminance information is stored in the memory 100 together with the typical defect area order information as the control information CS1. The control information CS1 read from the memory 100 is repeatedly supplied to the multiplexer 232 in accordance with the number of typical defective areas. The multiplexer 232 selects the corresponding control information CS1 of the order of the typical defect areas detected by the position determiner 224, that is, the typical defect area sequence M, and supplies the selected control information CS1 to the multiplexer 234. Therefore, in accordance with the brightness information of the control information CS1 supplied from the multiplexer 232, the multiplexer 234 selects the output of the adder 228 or the output of the subtractor 230, and supplies the selected output to the second compensator 160.

Therefore, using the typical defect area information PD1, CD1, and GD1 stored in the single memory 100, the first compensator 220 compensates the input data Re, Ge, and Be of a typical defect area having a vertical line defect or a horizontal line defect, and the output is compensated. data of.

Using the frame rate control flutter method, the second compensator 160 finely compensates the compensated data Rm1, Gm1, and Bm1 output by the first compensator 220 by distributing the data Rm1, Gm1, and Bm1 in space and time. When the compensation data for the boundary region of each typical defect region is spatially and temporally distributed according to the frame rate control dithering method, the luminance difference value of each boundary region is finely compensated.

Using the point defect information PD2, GD2, and CD2 stored in the memory 100, the third compensator 170 compensates the data Rm2, Gm2, and Bm2 to be displayed above the point defect area. For the data of the normal area, the third compensator 170 outputs no funds. Material compensation information.

As apparent from the above description, in the data compensation circuit of the third embodiment of the present invention, the first compensator 220 having a single compensator configuration is compensated for using the typical defect information PD1, CD1 and GD1 stored in the memory 100. The input data Re, Ge, and Be of the typical defect area of the line defect or the horizontal line defect, and output the compensated data. Therefore, the data compensation circuit of the third embodiment of the present invention can reduce the capacity of the memory 100 while compensating the data of various typical defect areas in accordance with the direction data of the typical defect area having vertical line defects or horizontal line defects. Because the first compensator 220 in the data compensation circuit of the embodiment of the present invention has a unified compensator configuration, it does not need to be divided into a vertical line compensator and a horizontal line compensator, which may reduce the size of the associated logic circuit, thereby reducing manufacturing costs.

Meanwhile, the data compensation circuit of each of the above embodiments of the present invention can be applied not only to a liquid crystal display device but also to other video display devices such as an organic light emitting diode and a plasma display device.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

10‧‧‧Dark pixels

11‧‧‧Normal pixels

12‧‧‧ Link pattern

13‧‧‧ Linked pixels

14‧‧‧Other normal pixels

20‧‧‧ bit expander

30‧‧‧First compensator

40‧‧‧ memory

42V‧‧‧ first memory

42H‧‧‧Second memory

44V, 44H‧‧‧ electric rewritable stylized read-only memory

46V, 46H‧‧‧ register

70‧‧‧Vertical line compensator

72‧‧‧Gray scale determiner

74‧‧‧Location determiner

76‧‧‧Compensation data selector

78‧‧‧Calculator

80‧‧‧Horizontal line compensator

82‧‧‧Gray scale determiner

84‧‧‧Location determiner

86‧‧‧Compensation data selector

88‧‧‧Calculator

90‧‧‧Multiplexer

100‧‧‧ memory

101‧‧‧Data Drive

102‧‧‧gate driver

103‧‧‧LCD panel

104‧‧‧Timing controller

105‧‧‧Data compensation circuit

110‧‧‧First compensator

120‧‧‧Vertical line compensator

122‧‧‧Gray scale determiner

124‧‧‧Location determiner

126‧‧‧Compensation data selector

128‧‧‧Adder

130‧‧‧Subtractor

132, 134‧‧‧ multiplexers

140‧‧‧Horizontal line compensator

142‧‧‧Gray scale determiner

144‧‧‧Location determiner

146‧‧‧Compensation data selector

148‧‧‧Adder

150‧‧‧Subtractor

152, 154‧‧‧ multiplexers

156‧‧‧Multiplexer

160‧‧‧Second compensator

162‧‧‧Box determinator

164‧‧‧ pixel position determiner

166‧‧‧vibration value selector

168‧‧‧Adder

170‧‧‧ Third compensator

172‧‧‧Gray scale determiner

174‧‧‧Location determiner

176‧‧‧Compensation data selector

178‧‧‧Calculator

220‧‧‧First compensator

222‧‧‧Gray scale determiner

224‧‧‧Location determiner

226‧‧‧Compensation data selector

228‧‧‧Adder

230‧‧‧Subtractor

232, 234‧‧‧ multiplexers

322‧‧‧First position determiner

324‧‧‧Second position determiner

326‧‧‧Multiplexer

1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention; and FIG. 2 is a schematic view showing a vertical line defect region displayed on a liquid crystal panel; Figure 3 is a schematic view showing a horizontal line defect area displayed on the liquid crystal panel; Fig. 4 is a schematic view showing a vertical line defect area shown in Fig. 2 in an enlarged state; and Fig. 5 is a third figure shown in Fig. 3. A schematic diagram showing a horizontal line defect area in an enlarged state; FIG. 6 is a gamma characteristic diagram of the output voltage according to the input data; FIG. 7 is a schematic diagram showing a point defect area displayed on the liquid crystal panel; A block diagram of a data compensation circuit according to a first embodiment of the present invention; a block diagram of the memory and the first compensator shown in FIG. 8; and a block diagram of the first compensator shown in FIG. a block diagram of the second compensator; FIGS. 11A to 11D are schematic diagrams showing a plurality of dither patterns stored in the dither value selector shown in FIG. 10; and FIG. 12 is a diagram shown in FIG. a block diagram of a third compensator; FIG. 13 is a block diagram of a data compensating circuit according to a second embodiment of the present invention; and FIG. 14 is a schematic view showing a bright typical defect area displayed on a liquid crystal panel; Shown as a typical darkness on the LCD panel A schematic view area; FIG. 16 shows a bright region and a dark defect defect area on the liquid crystal panel are shown in a schematic view state; FIG. 17 shown in a block diagram of the compensation circuit of the embodiment of the information of the third embodiment of the present invention; And Fig. 18 is a block diagram showing the position determiner shown in Fig. 17.

20‧‧‧ bit expander

30‧‧‧First compensator

40‧‧‧ memory

160‧‧‧Second compensator

170‧‧‧ Third compensator

Claims (18)

A video display device having the capability of compensating for display defects, comprising: a liquid crystal panel for displaying an image through a pixel matrix; a data driver for outputting data to the data line of the liquid crystal display panel; and a gate driver a gate line for driving the liquid crystal display panel; a timing controller for receiving the compensated data, the uncompensated data, and the synchronization signal to output a gate control signal to the gate driver and outputting the result Data and a data control signal to the data driver; a memory for storing information relating to at least one of a point defect on the liquid crystal display panel and a horizontal and vertical line defect of the liquid crystal display panel, and The information stored in the memory includes at least one of position information, gray scale information, compensation data and direction information of the horizontal and vertical line defects of the liquid crystal display panel; and a data compensation circuit for receiving the display data and the synchronization signal And outputting the compensated data to the timing controller according to the information in the memory and Uncompensated data is sent to the timing controller, wherein the data compensation circuit comprises: a vertical line compensator for compensating for one vertical line defect of the liquid crystal display panel; and a horizontal line compensator for compensating the liquid crystal display panel a horizontal line defect; and a multiplexer for selecting one of the vertical line compensator and the horizontal line compensator to output in accordance with the direction information from the memory. A video display device having the capability of compensating for display defects, as described in claim 1, wherein the information further includes sequence information and brightness information about the defect. The video display device as claimed in claim 1, wherein the information comprises position information, gray scale information and compensation data above the point defect area of the liquid crystal display panel. The video display device of claim 1, wherein the horizontal line compensator and the vertical line compensator receive the display material and compensate according to the defect having a main area and a boundary area. And outputting a first compensation signal. The video display device with the capability of compensating for display defects as described in claim 4, further comprising a fine compensator for receiving the first compensation signal, and controlling the wobbling method according to a frame rate according to space and time. The first compensation signal is distributed to compensate, and the compensated data is output. The video display device as claimed in claim 5, wherein the first compensator comprises: a frame determiner for counting pulses of a vertical sync signal to detect the number of frames; a pixel position determiner, wherein at least one of the synchronization signals is used to determine pixel position information of the first compensation signal; and a jitter value selector uses the first compensation signal and the frame of the frame determiner The number and the pixel position information output by the pixel position determiner select a flutter value; and an adder for increasing the flutter value of the flutter value selector to the first compensation signal, and then outputting the result data. The video display device with the capability of compensating display defects as described in claim 1 of the patent application further includes a point defect compensator for receiving display data, compensating according to the point defect information in the memory, and outputting the compensated data. . The video display device with the capability of compensating for display defects according to claim 7, wherein the point defect compensator comprises: a gray scale determiner for analyzing a link pixel to be supplied to one of the defect regions The grayscale level of the display data, the grayscale range information of the display data is selected from the memory, and a selected grayscale range information is outputted; and a position determiner uses at least one of the synchronization signals to display the data. Determining a pixel position and outputting pixel information; a compensation data selector, selecting compensation of the memory output according to the selected gray scale range information of the gray scale determiner and the pixel information of the position determiner And a calculator, adding the output of the compensation data to the display data or subtracting the compensation data from the display data to output the result data. A video display device having the capability of compensating for display defects as described in claim 1 wherein the vertical and horizontal line compensators each comprise: a gray scale determiner for analyzing each gray scale level of the display data to be supplied to one of the link defects of the one-point defect area, selecting corresponding gray scale range information of the display data from the memory, and outputting a selection Gray level range information; a position determiner, using at least one of the synchronization signals to determine a pixel position of the display data, and outputting pixel information; a compensation data selector, according to the selection of the gray level determiner Gray scale range information and the pixel information of the position determiner, selecting compensation data outputted by the memory; an adder for increasing the output of the compensation data to the display data to output the result data; a subtractor for Subtracting the compensation data from the display data to output result data; a first multiplexer sequentially outputting the brightness information of a typical defect area according to an order of the defects stored in the memory; and a second a multiplexer, selecting the output result data of the adder and the output result data of the subtractor according to the brightness information, and outputting the selected result data A video display device having the capability of compensating for display defects, comprising: a liquid crystal display panel for displaying an image through a pixel matrix; and a data driver for outputting data to the data line of the liquid crystal display panel; a gate driver for driving a gate line of the liquid crystal display panel; a timing controller for receiving the compensated data, the uncompensated data, and the synchronization signal to output a gate control signal to the gate driver and Outputting result data and a data control signal to the data driver; a memory for storing information of a defect of the liquid crystal display panel; a compensator for compensating according to the information of the memory and the at least one synchronization signal a defect of the liquid crystal display panel; a multiplexer selects an output according to the defect as a vertical line defect or a horizontal line defect to output a first compensation signal; and a fine compensator receives the first compensation signal Further, according to the frame rate control flutter method, the compensated data is output to the timing controller according to the first compensation signal compensation distributed in space and time. The video display device as claimed in claim 10, wherein the fine compensator comprises: a frame determiner for counting a pulse of a vertical sync signal to detect the number of frames; a position determining device for determining pixel position information of the first compensation signal by using at least one of the synchronization signals; a jitter value selector for using the first compensation signal, the number of the frame of the frame determiner, and The pixel position information output by the pixel position determiner selects a jitter value; An adder is configured to increase the jitter value of the jitter value selector to the first compensation signal, and then output the result data. The video display device with the capability of compensating display defects as described in claim 10 of the patent application further includes a point defect compensator for receiving display data, compensating according to the point defect information in the memory, and outputting the compensated data. The video display device with the capability of compensating for display defects according to claim 12, wherein the point defect compensator comprises: a gray scale determiner for analyzing a link pixel to be supplied to one of the defect regions Each grayscale level of the display data, selecting a grayscale range data for displaying data from the memory, and outputting a selected grayscale range information; a position determiner for determining the display by using at least one of the synchronization signals a pixel position of the data, and outputting pixel information; a compensation data selector for selecting the gray scale range information according to the gray scale determiner and the pixel information of the position determiner to select the compensation of the memory output And a calculator, adding the output of the compensation data to the display data or subtracting the compensation data from the display data to output the result data. A video display device having the capability of compensating for display defects according to claim 10, wherein the vertical and horizontal line compensators each comprise: a gray scale determiner for analyzing a link to be supplied to one of the defect regions Selecting the grayscale level of the displayed data, and selecting the display data from the memory Corresponding to gray scale range information, and outputting a selected gray scale range information; a position determiner, using at least one of the sync signals to determine a pixel position of the display data, and outputting pixel information; a compensation data selector And selecting, according to the selected gray scale range information of the gray scale determiner, the pixel information of the position determiner for selecting compensation data output by the memory; and an adder for increasing the output of the compensation data to the Displaying data to output result data; a subtractor for subtracting the compensation data from the display data to output result data; a first multiplexer sequentially, in accordance with one of the defects stored in the memory, sequentially And outputting the brightness information of the typical defect area; and a second multiplexer, selecting the output result data of the adder and the output result data of the subtractor according to the brightness information, and outputting the selected result data. A video display device having the capability of compensating for display defects, comprising: a liquid crystal display panel for displaying an image through a pixel matrix; a data driver for outputting data to the data line of the liquid crystal display panel; and a gate driver a gate line for driving the liquid crystal display panel; a timing controller for receiving compensated data, uncompensated data, and the same a step signal for outputting a gate control signal to the gate driver and outputting the result data and a data control signal to the data driver; a memory for storing information of a defect of the liquid crystal display panel; a gray scale determination And a grayscale level of the display data to be supplied to a defect area, selecting corresponding grayscale range information of the display data from the memory, and outputting a selected grayscale range information; a position determiner And determining a pixel position of the display data, and outputting pixel information; a compensation data selector, selecting the compensation data to be outputted by the memory according to the selected grayscale range information and the pixel information; An adder for increasing the output of the compensation data to the display data to output the first result data; a subtractor for subtracting the compensation data from the display data to output the second result data; The device outputs brightness information in sequence according to one of the defects stored in the memory; and a second multiplexer selects the first node according to the brightness information The results of one of the second data and information, and outputs the selected data as a result of a signal to be compensated. A video display device having the capability of compensating for display defects as described in claim 15 wherein the position determiner comprises: a first position determiner for determining one of the pixel position information of the display data in a horizontal direction; a second position determiner for determining the pixel position information of the display data in a vertical direction; And selecting a pixel position information of one of the first position determiner and the second position determiner according to the defect direction information of the memory. The video display device with the capability of compensating for display defects as described in claim 15 further includes a fine compensator for receiving the compensated signal, and controlling the dithering method according to a frame rate according to spatial and temporal distribution. The result data of the selection is compensated and the compensated data is output. The video display device with the capability of compensating for display defects as described in claim 1 further includes a defect compensator for receiving display data, compensating according to the point defect information in the memory, and outputting the compensated data.