TWI404417B - Sync slicer and sync slicing method - Google Patents

Abstract

An exemplary embodiment of the present invention provides a sync slicer which includes a filter module, a level detector and a level comparator. The filter module processes a video input to generate a filter output, and includes a first filter circuit for receiving the video input and performing an infinite impulse response (IIR) filtering upon the video input. The level detector is coupled to the filter module for receiving the filter output and referring to the filter output to generate a slicer level corresponding to a sync signal component. The level comparator is coupled to the filter module and the level detector for receiving the filter output and the slicer level and comparing the slicer level and the filter output to generate a sliced sync output.

Description

Synchronous signal intercepting device and synchronous signal intercepting method

The present invention relates to signal interception processing, and more particularly to a synchronous signal interception including an output of an Infinite Impulse Response (IIR) filter to determine a cutoff level and generate a synchronous signal cutoff output. Apparatus and method.

In general, the analog processing of analog TV signals mainly relies on horizontal sync (HSYNC) and vertical sync (VSYNC). The signal transmission of each scan line will contain a horizontal sync signal, however, vertical. The sync signal will only be generated once for each field. Please refer to FIG. 1 , which is a waveform diagram of a conventional composite video signal. As shown, the sync tip is the lowest voltage level in the composite video signal and has a differential voltage of 300 mV from the reference black level. In general, analog TV The decoder often uses the technique of sync slicing to determine the starting position of the horizontal sync signal component of the signal transmission of each scan line in the composite video signal. For example, the reference black level level is first found. The horizontal synchronization level is then used as the intercept level by referring to the intermediate level of the black level and the horizontal synchronization level to intercept the composite video signal to separate the horizontal synchronization signal component from the composite video signal. A subsequent synchronization circuit (eg, a phase-locked loop) produces a horizontal synchronization clock.

However, there are some interferences in the analog analog TV signals received, such as white noise and co-channel interference. Therefore, the actual composite video signal does not have the picture shown in Figure 1. The ideal waveform is subject to interference and waveform distortion. Therefore, how to determine the appropriate chopping level to obtain an accurate synchronous signal cutoff output becomes an important issue in the design of synchronous signal chopping.

Accordingly, it is an object of the present invention to provide a synchronous signal chopping apparatus and method including an output using infinite impulse response filtering to determine a chopping level and generate a synchronous signal chopping output to solve the above problems.

According to an embodiment of the invention, a synchronous signal clipping device is disclosed. The synchronous signal intercepting device comprises a filtering module, a chopping level detector and a comparator. The filter module processes a video input to generate a filtered output, and includes a first filter circuit for receiving the video input and performing an infinite impulse response filtering process on the video input. The chopping level detector is coupled to the filter module for receiving the filtered output, and determining a cutoff level corresponding to a sync signal component according to the filtered output. The comparator is coupled to the chopping level detector and the filter module for receiving the filtered output and the chopping level, and comparing the chopping level with the filtered output to generate a synchronous signal cut Wave output.

According to an embodiment of the present invention, a synchronization signal intercepting method is further disclosed. The synchronous signal intercepting method includes: processing a video input to generate a filtered output, comprising: performing an infinite impulse response filtering process on the video input; determining, according to the filtered output, a cutoff criterion corresponding to a synchronous signal component Bits; and comparing the chopping levels to the filtered output to produce a synchronous signal cutoff output.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is described as being coupled to a second device, it is meant that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device by other means or connection means.

Please refer to FIG. 2, which is a schematic diagram of a first embodiment of a synchronous signal clipping device according to the present invention. The synchronous signal clipping device 200 includes, but is not limited to, a filtering module 202, a chopping level detector 204, and a comparator 206. The filter module 202 is configured to process a video input (eg, sampled data of the composite video signal) S_IN to generate a filtered output S_OUT. In this embodiment, the filter module 202 includes at least a first filter circuit 208 that receives the video input. S_IN, and an infinite Impulse Response (IIR) filtering process is performed on the video input S_IN to generate a filtered output S_OUT. In other words, the first filter circuit 208 can be implemented by using an architecture of an infinite impulse response filter. The chopping level detector 204 is coupled to the filter module 202 for receiving the filtered output S_OUT from the filter module 202, and determining a cutoff level corresponding to a synchronous signal component according to the filtered output S_OUT (slicer level) In the present embodiment, the synchronization signal component is a horizontal synchronization signal component. However, this is for illustrative purposes only and is not a limitation of the present invention. In addition, the comparator 206 is coupled to the chopping level detector 204 and the filtering module 202 for receiving the filtered output S_OUT and the chopping level SL, and comparing the chopping level SL with the filtered output S_OUT to generate a synchronization. The signal cutoff output is Sliced_SYNC. The main technical feature of the present invention is that the filter module 202 is not the comparator 206 and the chopping level detector 204, that is, the filter module 202 is used to generate the filtered output S_OUT for subsequent circuits (including the comparator 206 and the cutoff). The wave level detector 204) is used. Furthermore, in one implementation of the present invention, the comparator 206 and the chopping level detector 204 can be implemented by any conventional circuit architecture, so For the sake of brevity of the description, the descriptions of the comparator 206 and the chopping level detector 204 are omitted here. The circuit and operation of the filter module 202 will be described in detail below.

As described above, the first filter circuit 208 in the filter module 202 is configured to perform an infinite impulse response filtering process. Therefore, in this embodiment, the first filter circuit 208 processes the input data in a recursive manner (also That is, S_IN), in other words, the filtered output S_OUT generated by the first filter circuit 208 and the currently received input data (such as the current data of the composite video signal) and the previously received input data (such as a composite video signal before a data) In this embodiment, the first filter circuit 208 uses a weighted average operation to implement an infinite impulse response filtering process. However, this is for illustrative purposes only, and is not a limitation of the present invention. The first filter circuit 208 can also be implemented by other infinite impulse response systems without departing from the inventive spirit of the present invention, and these design variations are also within the scope of the present invention. As shown in FIG. 2, the first filter circuit 208 of the filter module 202 includes, but is not limited to, a first multiplication unit 210, a second multiplication unit 212, an addition unit 214, a storage unit 216, and a Weight value setting unit 218. The first multiplication unit 210 is configured to multiply each piece of data (for example, each sample value of the composite video signal) in the video input S_IN by a first weight value W(0≦W≦1) to generate a first multiplication output M1. . The second multiplying unit 212 is coupled to the storage unit 216 for multiplying each piece of data in the processing result D_IIR stored in the storage unit 216 (for example, each sample value processed by weighted averaging) by a second weight value ( 1-W) to generate a second multiplication output M2. The adding unit 214 is coupled to the first multiplying unit 210, the second multiplying unit 212, and the storage unit 216 for summing the first multiplication output M1 and the second multiplication output M2 to generate an addition output M3, where M3=M1*W +M2*(1-W), and the addition output M3 is written to the storage unit 216 to update each of the corresponding data in the processing result D_IIR stored in the storage unit 216.

In this embodiment, the addition output M3 generated by the addition unit 214 is directly used as the filtered output S_OUT of the filter module 202 (ie, S_OUT=M3), in addition to being written back to the storage unit 216 for data update; The unit 216 is a line buffer having a buffer depth equal to a total number of predetermined sampling points of one scan line. Therefore, under ideal conditions, each time a sample line of the scan line is input, the storage unit 216 will just store the line. The sampled data of the scan lines are processed by an infinite impulse response filtering process. In addition, since the line buffer is an element that is originally provided in the analog TV decoder, the first filter circuit 208 can utilize the existing line buffer as the required storage unit 216, thereby saving the practical requirements. Hardware cost.

Please refer to FIG. 3, which is a schematic diagram of the first filter circuit 208 performing an infinite impulse response filtering process. It is assumed that in the time period T ₀ ~ T ₁ , the filter module 202 receives the sample data D0 of the first scan line in the first picture one by one, and the sample data D0 is directly written into the storage unit 216 to be stored as the storage unit 216. The initial processing result is D_IIR ₀ , that is, D_IIR ₀ = D ₀ . From time T2, each piece of data (sample value) in the sample data D1 of the second scan line in the first picture is first input to the first filter circuit 208 one by one, and the first sample in the sample data D1 is received. In the value, the first filter circuit 208 reads the corresponding processed oversampled value in the initial processing result D_IIR ₀ from the storage unit 216, and generates a new processed oversampled value to the storage via the infinite impulse response filtering process described above. The unit 216, and the subsequent sample values in the sampled data D1 are similarly subjected to infinite impulse response filtering processing one by one. Therefore, in the period T ₁ to T ₂ , the first filter circuit 208 can be regarded as based on the initial processing result D_IIR ₀ and sampling. The data D1 performs an infinite impulse response filtering process, so at time T ₂ , the storage unit 216 stores the updated processing result D_IIR ₁ . Similarly, in the period T ₂ to T ₃ , the first filter circuit 208 can be regarded as performing an infinite impulse response filtering process based on the processing result D_IIR ₁ and the next sample data D1. Therefore, at time T ₃ , the storage unit 216 stores The updated processing result is D_IIR ₂ . Since the skilled person can easily understand the subsequent operation after reading the above description, it will not be further described herein.

The first filter circuit 208 performs an infinite impulse response filtering process on the video input S_IN, and then inputs the filtered output S_OUT (that is, the filtered processed video input S_IN) generated by the infinite impulse response filtering process to a subsequent circuit (for example, clipping) The level detector 204 and the comparator 206), therefore, for the cut level detector 204 and the comparator 206, since the filtered video input S_IN can input the unwanted interference component of the original video input S_IN (for example, white noise and co-channel interference, etc.) are effectively filtered or attenuated, so that the cutoff level SL determined by the cut-off level detector 204 and the synchronous signal generated by the comparator 206 can be greatly increased. The wave outputs the accuracy of the Sliced_SYNC, which in turn improves the final picture quality.

Please note that in the embodiment, the first filter circuit 208 is further provided with a weight value setting unit 218 coupled to the first multiplication unit 210 and the second multiplication unit 212 for using one of the signal characteristics of the video input S_IN. The first weight value W and the second weight value (1-W) are set. For example, the weight value setting unit 218 dynamically adjusts the first based on the signal-to-noise ratio (SNR) of the video input S_IN. The weight value W and the second weight value (1-W), therefore, when the signal input S_IN is relatively high (the degree of interference of the video input S_IN is less serious), the weight value setting unit 218 increases the first weight. The value W and the second weight value (1-W) are lowered. On the other hand, when the signal input S_IN is relatively low (the degree of interference of the video input S_IN is serious), the weight value setting unit 218 decreases the first. The weight value W and the second weight value (1-W) are raised, in other words, the first weight value W is positively correlated with the signal-to-noise ratio, and the second weight value (1-W) is negatively correlated with the signal-to-noise ratio.

According to the above description, the setting of the weight value setting unit 218 can cause the first weight value W and the second weight value (1-W) to be dynamically adjusted according to the actual signal quality of the video input S_IN itself, so that the first filtering is performed. The circuit 208 can have a better infinite impulse response filtering performance. However, the weight value setting unit 218 can be an optional component, for example, in another embodiment, if it is in a particular operating environment. The actual signal quality of the video input S_IN is very stable, and the first filter circuit 208 can omit the weight value setting unit 218, and only use a set of preset first weight value W and second weight value (1-W). And this design change is also within the scope of the invention.

FIG. 4 is a flow chart of the first embodiment of the synchronous signal chopping method of the present invention. The flow shown in Fig. 4 is applied to the synchronous signal clipping device 200 shown in Fig. 2. Further, if substantially the same result is obtained, the steps are not necessarily performed in the order shown in Fig. 4. The operation of the first embodiment of the synchronous signal chopping method of the present invention can be summarized as follows:

Step 402: Receive a video input (for example, sampling data of the composite video signal).

Step 404: Perform an infinite impulse response filtering process (such as weighted averaging processing) on the video input to generate a filtered output.

Step 406: Determine a cutoff level corresponding to a synchronization signal component (for example, a horizontal synchronization signal component) according to the filtered output.

Step 408: Compare the cutoff level with the filtered output to generate a synchronous signal cutoff output. Next, returning to step 404 to continue processing the video input using the infinite impulse response filtering process.

Since the skilled person can easily understand the operation details of each step after reading the above technical contents of the synchronous signal intercepting device 200, the related description will not be repeated here.

In the above embodiment, the storage unit 216 is a line buffer whose buffer depth is equal to the total number of predetermined sampling points of one scan line. Therefore, under ideal conditions, each time a sample of the scan line is input, the storage unit 216 will The sample data of the scan line is stored as a result of the infinite impulse response filtering process. However, if the scan line period of the video input S_IN is unstable (for example, the source of the video input S_IN is a cassette recorder ( Videocassette recorder (VCR), which is often limited by the characteristics of the reading mechanism, causing the scan line period to be unstable or causing changes (for example, the source of the video input S_IN is not a standard video output), so it is below the same sampling frequency. The total number of actual sampling points of a scan line is not equal to the total number of predetermined sampling points (that is, the buffer depth of the line buffer). In this case, the video input S_IN and the processing result D_IIR cannot be aligned, but the filter module may be caused. The signal quality of the filtered output S_OUT (ie, the filtered video input S_IN) generated by 202 is deteriorated, therefore, The present invention further discloses an adaptive filtering processing mechanism that dynamically selects an appropriate filtering processing method according to a judgment criterion.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a second embodiment of a synchronous signal clipping device according to the present invention. The synchronization signal intercepting device 500 includes, but is not limited to, a filtering module 502 and a chopping level detector 204 and a comparator 206 shown in FIG. 2, wherein the filtering module 502 is shown in FIG. In addition to the first filter circuit 208, a second filter circuit 508, a multiplexer 510, and a control circuit 512 are further included. Since the functions and operations of the first filter circuit 208, the chopping level detector 204 and the comparator 206 have been described in detail above, they will not be further described herein. For the second filter circuit 508, it similarly receives the video input S_IN, but performs a predetermined filtering process on the video input S_IN, and the predetermined filtering process is different from the infinite impulse response filtering process performed by the first filter circuit 208. For example, the predetermined filtering process is a simple low-pass filtering process. Therefore, the second filtering circuit 508 inputs multiple pieces of data corresponding to the same scanning line in the video input S_IN (for example, the same scanning line in the composite video signal) The plurality of sample values are used for the averaging operation to output the average value. However, this is for illustrative purposes only and is not a limitation of the present invention. That is, in other embodiments, the predetermined filtering process may also adopt other types. The filtering operation, broadly speaking, can be applied to the second filter circuit 508 as long as it is different from the inventive spirit of the invention, as long as it is different from the processing mechanism of the infinite impulse response filtering process used by the first filter circuit 208. These changes in design are within the scope of the invention.

In addition, the multiplexer 510 has a plurality of inputs 埠N1, N2 coupled to the first filter circuit 208 and the second filter circuit 508, a control 埠N3, and an output 埠N4, wherein the output 埠N4 is used to output the filter mode. The filtered output of group 502 is S_OUT. The control circuit 512 is coupled to the control unit 3N3 for generating a selection signal SEL to the control unit 3N3 for controlling the output of the first filter circuit 208 by the multiplexer 510 (that is, the addition unit 214 shown in FIG. 2). The output of the addition output M3) or the second filter circuit 508 (e.g., the result of the low pass filtering process) M3' is passed to the output 埠N4 as the filtered output S_OUT.

As shown in FIG. 5, the comparator 206 inputs the synchronous signal cutoff output Sliced_SYNC to a clock generating device (eg, phase locked loop) 501 for processing to generate a synchronous clock (eg, horizontal sync clock) CLK_SYNC, and controls Circuit 512 generates selection signal SEL based on the period of synchronous clock CLK_SYNC. For example, under a default operating state, the control circuit 512 generates a selection signal SEL to control the multiplexer 510 to pass the output M3 of the first filter circuit 208 to the output 埠N4 as the filtered output S_OUT, In other words, the filter module 502 presets to use the first filter circuit 208. However, when the control circuit 512 subsequently detects that the period of the synchronization clock CLK_SYNC is different from the ideal value of one of the scan line periods, or detects the synchronization clock CLK_SYNC If the difference between the period and the ideal value (phase difference) exceeds the allowable error range, the control circuit 512 immediately controls the multiplexer 510 to select the output M3' of the second filter circuit 508 by adjusting the selection signal SEL to Output 埠N4 as the filtered output S_OUT.

Please note that the control circuit 512 can also generate the selection signal SEL according to the statistical result of the period of the synchronization clock CLK_SYNC. For example, when the control circuit 512 detects the average period of the synchronization clock CLK_SYNC (which can be measured in a period of time) The measured result of the measured period length is calculated as the difference between the ideal value of one of the scan line periods or the difference between the average period of the synchronized clock CLK_SYNC and the ideal value (phase difference) exceeds the allowable error range. The control circuit 512 controls the multiplexer 510 to select the output M3' of the second filter circuit 508 to be output to the output SN4 as the filtered output S_OUT by the adjustment of the selection signal SEL, and this design change is also The scope of the invention.

In addition, if the filter module 502 is currently switched to the use of the second filter circuit 508, the control circuit 512 subsequently detects that the period/average period of the synchronization clock CLK_SYNC is the same as the ideal value of the scan line period or the period of the synchronization clock CLK_SYNC. If the difference between the average period and the ideal value (phase difference) falls within the allowable error range, the multiplexer 510 can be controlled to select the output M3' of the second filter circuit 508 to the output 埠N4 by selecting the signal SEL. As the filtered output S_OUT, the filter module 502 returns to use the preset first filter circuit 208 at this time.

Figure 6 is a flow chart of a second embodiment of the method for synchronizing signal synchronization according to the present invention. The flow shown in Fig. 6 is applied to the synchronous signal clipping device 500 shown in Fig. 5. Further, if substantially the same result is obtained, the steps are not necessarily performed in the order shown in Fig. 6. The operation of the second embodiment of the synchronous signal chopping method of the present invention can be summarized as follows:

Step 602: Receive a video input (for example, sampling data of the composite video signal).

Step 604: Perform an infinite impulse response filtering process (such as weighted averaging processing) on the video input to generate a filtered output.

Step 606: Determine a cutoff level corresponding to a synchronization signal component (for example, a horizontal synchronization signal component) according to the filtered output.

Step 608: Compare the cutoff level with the filtered output to generate a synchronous signal cutoff output.

Step 610: According to whether the period/average period of the synchronization clock CLK_SYNC is different from the ideal value of the scan line period or whether the difference (phase difference) between the period/average period of the synchronization clock CLK_SYNC and the ideal value exceeds the allowable error range. A determination is made as to whether switching to a predetermined filtering process (e.g., low pass filtering process) other than the infinite impulse response filtering process is performed, and if so, step 612 is performed, otherwise, returning to step 604 to continue employing the infinite impulse response filtering process.

Step 612: Perform a predetermined filtering process on the video input to generate the filtered output.

Step 614: Determine the chopping level according to the filtered output.

Step 616: Compare the cutoff level with the filtered output to generate the synchronous signal cutoff output.

Step 618: Whether the period/average period of the synchronization clock CLK_SYNC is equal to the ideal value of the scan line period or whether the difference between the period/average period of the synchronization clock CLK_SYNC and the ideal value (phase difference) falls within an allowable error range. To determine whether it is necessary to reply to use the infinite impulse response filtering process, if yes, proceed to step 604, otherwise, return to step 612 and continue to use the predetermined filtering process.

Since the skilled person can easily understand the operation details of each step after reading the above technical contents of the synchronous signal intercepting device 500, the related description will not be repeated here.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

200, 500. . . Synchronous signal interceptor

202, 502. . . Filter module

204. . . Chopping level detector

206. . . Comparators

208. . . First filter circuit

210. . . First multiplication unit

212. . . Second multiplication unit

214. . . Addition unit

216. . . Storage unit

218. . . Weight value setting unit

402~408, 602~618. . . step

501. . . Clock generating device

508. . . Second filter circuit

510. . . Multiplexer

512. . . Control circuit

S_IN. . . Video input

S_OUT. . . Filtered output

SL. . . Chopping level

Sliced_SYNC. . . Synchronous signal cutoff output

M1. . . First multiplication output

M2. . . Second multiplication output

M3. . . Addition output

M3’. . . Output of the second filter circuit

N1, N2. . . Input 埠

N3. . . Control

N4. . . Output埠

D_IIR, D_IIR ₀ ~ D_IIR ₃ . . . process result

D0~D4. . . Sampling data

T ₀ ~T ₅ . . . time

W. . . First weight value

1-W. . . Second weight value

CLK_SYNC. . . Synchronous clock

Figure 1 is a waveform diagram of a conventional composite video signal.

FIG. 2 is a schematic diagram of a first embodiment of a synchronous signal clipping device according to the present invention.

FIG. 3 is a schematic diagram showing the first filter circuit performing an infinite impulse response filtering process.

FIG. 4 is a flow chart of the first embodiment of the synchronous signal chopping method of the present invention.

FIG. 5 is a schematic diagram of a second embodiment of a synchronous signal clipping device according to the present invention.

Figure 6 is a flow chart of a second embodiment of the method for synchronizing signal synchronization according to the present invention.

200. . . Synchronous signal interceptor

202. . . Filter module

204. . . Chopping level detector

206. . . Comparators

208. . . First filter circuit

210. . . First multiplication unit

212. . . Second multiplication unit

214. . . Addition unit

216. . . Storage unit

218. . . Weight value setting unit

S_IN. . . Video input

S_OUT. . . Filtered output

SL. . . Chopping level

Sliced_SYNC. . . Synchronous signal cutoff output

M1. . . First multiplication output

M2. . . Second multiplication output

M3. . . Addition output

W. . . First weight value

1-W. . . Second weight value

Claims (20)

A synchronous signal clipping device includes: a filtering module for processing a video input to generate a filtered output, the filtering module comprising: a first filtering circuit, receiving the video input, and the video The input performs an Infinite Impulse Response (IIR) filtering process; a chopping level detector is coupled to the filtering module for receiving the filtered output, and determining a corresponding one according to the filtered output a chopping level of the synchronization signal component; and a comparator coupled to the chopping level detector and the filtering module for receiving the filtered output and the chopping level, and comparing the chopping The level and the filtered output are used to generate a sync signal cutoff output. The synchronous signal clipping device of claim 1, wherein the synchronous signal component is a horizontal synchronization signal component. The synchronous signal clipping device of claim 1, wherein the first filter circuit comprises: a storage unit; and a first multiplication unit that multiplies each data in the video input by a first weight a value for generating a first multiplication output; a second multiplication unit coupled to the storage unit for multiplying each of the data stored in the storage unit by a second weight value to generate a first a multiplication output; and an addition unit coupled to the first multiplication unit, the second multiplication unit, and the storage unit for summing the first multiplication output and the second multiplication output to generate an addition output, and The addition output is written to the storage unit to update each of the corresponding data in the processing result stored by the storage unit. The synchronous signal clipping device of claim 3, wherein the storage unit is a line buffer having a buffer depth equal to a total number of predetermined sampling points of one scan line. The synchronous signal clipping device of claim 3, wherein the first filtering circuit further comprises: a weight value setting unit coupled to the first multiplication unit and the second multiplication unit for The video input has a signal characteristic to set the first weight value and the second weight value. The synchronous signal clipping device of claim 5, wherein the signal characteristic is a signal to noise ratio. The synchronous signal clipping device of claim 6, wherein the first weight value is positively correlated with the signal-to-noise ratio, and the second weight value is negatively correlated with the signal-to-noise ratio. The synchronous signal clipping device of claim 1, wherein the filtering module further comprises: a second filtering circuit that receives the video input and performs a predetermined filtering process on the video input, wherein the The predetermined filtering process is different from the infinite impulse response filtering process performed by the first filter circuit; a multiplexer having a control port, an output port, and a plurality of input ports respectively coupled to the first and second filters a circuit, wherein the output is configured to output the filtered output of the filter module; and a control circuit coupled to the control port for generating a selection signal to the control port to control the multiplexer to The output of the first filter circuit or the output of the second filter circuit is passed to the output port. The synchronous signal clipping device of claim 8, wherein the comparator inputs the synchronous signal cutoff output to a clock generating device for processing to generate a synchronous clock, and the control circuit is based on the The period of the clock is synchronized to generate the selection signal. The synchronous signal clipping device of claim 9, wherein the control circuit generates the selection signal according to a statistical result of a period of the synchronization clock. A synchronous signal intercepting method includes: processing a video input to generate a filtered output, comprising: performing an Infinite Impulse Response (IIR) filtering process on the video input; determining a correspondence according to the filtered output. a cutoff level of a sync signal component; and comparing the cutoff level to the filtered output to produce a sync signal cutoff output. The synchronous signal clipping method according to claim 11, wherein the synchronous signal component is a horizontal synchronization signal component. The synchronous signal clipping method of claim 11, wherein the infinite impulse response filtering process comprises: multiplying each piece of data in the video input by a first weight value to generate a first multiplication output; Multiplying each of the processing results stored in a storage unit by a second weight value to generate a second multiplication output; and summing the first multiplication output and the second multiplication output to generate an addition output, and The addition output is written to the storage unit to update each of the corresponding data in the processing result stored by the storage unit. The synchronous signal chopping method of claim 13, wherein the storage unit is a line buffer having a buffer depth equal to a total number of predetermined sampling points of one scan line. The synchronous signal clipping method of claim 13, wherein the infinite impulse response filtering process further comprises: setting the first weight value and the second weight value according to a signal characteristic of the video input. The synchronous signal clipping method according to claim 15, wherein the signal characteristic is a signal-to-noise ratio. The synchronous signal clipping method according to claim 16, wherein the first weight value is positively correlated with the signal-to-noise ratio, and the second weight value is negatively correlated with the signal-to-noise ratio. The synchronous signal clipping method of claim 11, wherein the step of processing the video input to generate the filtered output further comprises: performing a predetermined filtering process on the video input, wherein the predetermined filtering process is different from The infinite impulse response filtering process; and selecting an output of the infinite impulse response filter or an output of the predetermined filtering process as the filtered output. The synchronous signal clipping method according to claim 18, wherein the synchronous signal cutoff output is further processed by a clock generation process to generate a synchronous clock, and the output of the infinite impulse response filter or the predetermined filtering process is selected. The step of outputting the output as the filtered output includes selecting an output of the infinite impulse response filter or an output of the predetermined filtering process based on a period of the synchronization clock. The synchronous signal clipping method according to claim 19, wherein the step of outputting the output of the infinite impulse response filter or the output of the predetermined filtering process based on the period of the synchronization clock includes: according to the synchronization The statistical result of the period of the pulse is selected to output the output of the infinite impulse response filter or the output of the predetermined filtering process.