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TWI402515B - Signal testing apparatus - Google Patents

Signal testing apparatus Download PDF

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Publication number
TWI402515B
TWI402515B TW98100681A TW98100681A TWI402515B TW I402515 B TWI402515 B TW I402515B TW 98100681 A TW98100681 A TW 98100681A TW 98100681 A TW98100681 A TW 98100681A TW I402515 B TWI402515 B TW I402515B
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switch
contact
test
switches
interface
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TW98100681A
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Chinese (zh)
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TW201027088A (en
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Fa-Sheng Huang
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Hon Hai Prec Ind Co Ltd
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Description

訊號測試裝置Signal test device

本發明係關於一種訊號測試裝置,特別係關於一種主機介面之訊號測試裝置。The invention relates to a signal testing device, in particular to a signal testing device for a host interface.

主機介面一般包括DVI(Digital Visual Interface,即數位視頻)介面、VGA(Video Graphics Array,視頻圖形陣列)介面、USB(Universal Serial Bus,通用串列匯流排)介面及HDMI(High Definition Multimedia Interface,高清晰度多媒體介面)等。為保證與該等主機介面相連之外部設備正常使用,需要對該等主機介面之電氣性能進行訊號完整性測試。先前技術中對該等主機介面之測試一般是將主機介面待測引腳輸出之訊號引到一專用之測試裝置上,利用探棒(比如示波器之兩個探針)對主機介面之待測引腳輸出之訊號進行量測。由於在測試過程中需要更改主機介面待測引腳輸出之訊號,比如更改主機VGA介面之輸出訊號以更改監視器之解析度,故需要重複插拔測試裝置及監視器與VGA介面之連接。重複插拔浪費時間、減少了主機介面與探棒之使用壽命、以及容易導致探棒與主機介面之測試點接觸不良而影響測試精度等。The host interface generally includes a DVI (Digital Visual Interface) interface, a VGA (Video Graphics Array) interface, a USB (Universal Serial Bus) interface, and an HDMI (High Definition Multimedia Interface). Sharpness multimedia interface). In order to ensure the normal use of external devices connected to these host interfaces, signal integrity testing is required for the electrical performance of these host interfaces. In the prior art, the test of the host interface is generally to direct the signal outputted by the host interface to be tested to a dedicated test device, and the probe (such as the two probes of the oscilloscope) is used to test the host interface. The signal output from the foot is measured. Since it is necessary to change the output signal of the host interface to be tested during the test, such as changing the output signal of the host VGA interface to change the resolution of the monitor, it is necessary to repeatedly plug and unplug the test device and the connection between the monitor and the VGA interface. Repeated insertion and removal wastes time, reduces the service life of the host interface and the probe, and easily leads to poor contact between the probe and the test interface of the host interface, which affects the test accuracy.

鑒於以上內容,有必要提供一種訊號測試裝置,不需要重複插拔外部設備及測試裝置以交換與主機介面之連接。In view of the above, it is necessary to provide a signal testing device that does not require repeated insertion and removal of external devices and test devices to exchange connections with the host interface.

一種訊號測試裝置,包括:A signal testing device comprising:

複數二選一開關,每一二選一開關包括一靜態觸點、一第一動態觸點及一第二動態觸點,該等二選一開關之靜態觸點對應與一主機介面之複數待測引腳相連,該等二選一開關之第一動態觸點對應與一外設介面之複數引腳相連,該主機介面之複數待測引腳對應適配於該外設介面之複數引腳;A plurality of switches are selected, each of the two switches includes a static contact, a first dynamic contact and a second dynamic contact, and the static contacts of the two switches are corresponding to a plurality of host interfaces The first dynamic contact of the two selected switches is connected to a plurality of pins of a peripheral interface, and the plurality of pins to be tested of the host interface are corresponding to the complex reference of the peripheral interface. foot;

一多選一開關,包括複數動態觸點及一靜態觸點,該多選一開關之每一動態觸點分別與一二選一開關之第二動態觸點對應相連;以及a plurality of switches, including a plurality of dynamic contacts and a static contact, each of the dynamic contacts of the plurality of switches being respectively associated with a second dynamic contact of a switch; and

一測試端,包括一第一測試點及一第二測試點,該第一測試點與該多選一開關之靜態觸點相連,該第二測試點接地;a test end includes a first test point and a second test point, the first test point is connected to the static contact of the multi-select switch, and the second test point is grounded;

當每一二選一開關之靜態觸點與其第一動態觸點相連時,該主機介面之待測引腳與該外設介面之引腳對應連接;當每一二選一開關之靜態觸點與其第二動態觸點相連時,該主機介面之每一待測引腳分別與該多選一開關之一動態觸點對應相連,透過將該多選一開關之靜態觸點選擇性地與其一動態觸點相連來測試該主機介面之對應待測引腳輸出之訊號。When the static contact of each of the two switches is connected to the first dynamic contact, the pin to be tested of the host interface is connected with the pin of the peripheral interface; when each of the two switches selects a static contact When connected to the second dynamic contact, each of the pins to be tested of the host interface is respectively connected to one of the dynamic contacts of the multi-select switch, and the static contact of the multi-select switch is selectively connected thereto. Dynamic contacts are connected to test the signal output from the host interface corresponding to the pin to be tested.

前述訊號測試裝置透過該等二選一開關控制該主機介面與外設介面之連接,並透過多選一開關選擇測試該主機介面之一待測引腳輸出之訊號,避免了測試裝置與外部設備之重複插拔以及示波器探針在測試端上之重複插拔,延長主機介面及示波器探針之使用壽命,縮短測試時間,提高測試精度。The signal testing device controls the connection between the host interface and the peripheral interface through the two selection switches, and selects a signal for testing the output of one of the host interfaces through the multi-selection switch, thereby avoiding the test device and the external device. Repeated insertion and removal and repeated insertion and removal of the oscilloscope probe on the test end extend the life of the host interface and the oscilloscope probe, shorten the test time, and improve the test accuracy.

請參閱圖1,本發明訊號測試裝置之較佳實施方式包括一主機介面連接器100、一外設介面連接器200、一第一開關S1、一第二開關S2、一第三開關S3、一第四開關S4、一第五開關S5、一第一電阻R1、一第二電阻R2、一第三電阻R3、一第四電阻R4以及一測試端J1。Referring to FIG. 1 , a preferred embodiment of the signal testing device of the present invention includes a host interface connector 100 , a peripheral interface connector 200 , a first switch S1 , a second switch S2 , a third switch S3 , and a first switch S1 . The fourth switch S4, the fifth switch S5, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a test terminal J1.

該主機介面連接器100用於連接一主機介面101。該外設介面連接器200用於連接與該主機介面101相適配之一外部設備之介面(簡稱外設介面)201。本實施例中,該主機介面連接器100有八個引腳P11~P18,其分別對應與該待測主機介面101之八個引腳P21~P28相連。該外設介面連接器200有八個引腳T11~T18,其分別對應與該外設介面201之八個引腳T21~T28相連。本實施例中該主機介面101之引腳P21~P24為待測引腳,即需要對該主機介面101之待測引腳P21~P24進行訊號完整性測試。The host interface connector 100 is used to connect to a host interface 101. The peripheral interface connector 200 is used to connect an interface of an external device (referred to as a peripheral interface) 201 that is compatible with the host interface 101. In this embodiment, the host interface connector 100 has eight pins P11~P18, which are respectively connected to the eight pins P21~P28 of the host interface 101 to be tested. The peripheral interface connector 200 has eight pins T11~T18, which are respectively connected to the eight pins T21~T28 of the peripheral interface 201. In this embodiment, the pins P21~P24 of the host interface 101 are pins to be tested, that is, the signal integrity tests of the pins P21~P24 to be tested on the host interface 101 are required.

該第一開關S1至第四開關S4均為一二選一開關,比如一單刀雙擲開關。該第一開關S1至第四開關S4均包括一靜態觸點1、一第一動態觸點2、一第二動態觸點3。該第五開關S5為一多選一開關,比如一單刀多擲開關,本實施例中該第五開關S5為一四選一開關,其包括一個靜態觸點A及四個動態觸點A1~A4。該第一開關S1至第四開關S4之靜態觸點1分別與該主機介面連接器100之引腳P11~P14相連。該第一開關S1至第四開關S4之第一動態觸點2分別與該外設介面連接器200之引腳T11~T14相連,該第一開關S1至第四開關S4之第二動態觸點3分別與該第五開關S5之四個動態觸點A1~A4相連。該第一電阻R1至第四電阻R4之一端分別與該第一開關S1至第四開關S4之第二動態觸點3相連,該第一電阻R1至第四電阻R4之另一端均接地。該第一電阻R1至第四電阻R4均為終結電阻,用於防止該主機介面101之待測引腳P21~P24輸出之訊號反射。該第五開關S5之靜態觸點A與該測試端J1之一第一測試點P1相連,該測試端J2之一第二測試點P2接地。該測試端J1為一具有兩針頭之插件。該待測主機介面101不需要測試之其他引腳P25~P28與該外設介面201之對應引腳T25~T28透過該主機介面連接器100以及外設介面連接器200正常連接。The first switch S1 to the fourth switch S4 are both a switch and a switch, such as a single pole double throw switch. The first switch S1 to the fourth switch S4 each include a static contact 1, a first dynamic contact 2, and a second dynamic contact 3. The fifth switch S5 is a multi-select switch, such as a single-pole multi-throw switch. In the embodiment, the fifth switch S5 is a four-select switch, which includes a static contact A and four dynamic contacts A1~ A4. The static contacts 1 of the first switch S1 to the fourth switch S4 are respectively connected to the pins P11 to P14 of the host interface connector 100. The first dynamic contact 2 of the first switch S1 to the fourth switch S4 are respectively connected to the pins T11~T14 of the peripheral interface connector 200, and the second dynamic contact of the first switch S1 to the fourth switch S4 3 is respectively connected to the four dynamic contacts A1~A4 of the fifth switch S5. One ends of the first resistors R1 to R4 are respectively connected to the second dynamic contacts 3 of the first switch S1 to the fourth switch S4, and the other ends of the first resistors R1 to R4 are grounded. The first resistor R1 to the fourth resistor R4 are termination resistors for preventing signal reflection of the output pins P21~P24 of the host interface 101. The static contact A of the fifth switch S5 is connected to one of the first test points P1 of the test terminal J1, and the second test point P2 of the test terminal J2 is grounded. The test end J1 is a plug with two needles. The other pins P25~P28 of the host interface 101 to be tested do not need to be tested and the corresponding pins T25~T28 of the peripheral interface 201 are normally connected through the host interface connector 100 and the peripheral interface connector 200.

當該第一開關S1至第四開關S4之靜態觸點1均對應與其第二動態觸點3相連時,該主機介面101之待測引腳P21~P24之訊號傳輸給該第五開關S5之四個動態觸點A1~A4,此時,該第五開關S5之靜態觸點A選擇性地與其四個動態觸點A1~A4連接即可選擇測試該主機介面101之待測引腳P21~P24輸出之訊號,比如選擇測試該主機介面101之待測引腳P21輸出之訊號,則將該第五開關S5之靜態觸點A與第一動態觸點A1連通。之後,將一示波器之正負探針分別連接到該測試端J1之第一測試點P1、第二測試點P2上以對該主機介面101之待測引腳P21輸出之訊號進行訊號完整性測試。When the static contacts 1 of the first switch S1 to the fourth switch S4 are connected to the second dynamic contact 3, the signals of the pins P21 to P24 of the host interface 101 are transmitted to the fifth switch S5. Four dynamic contacts A1~A4. At this time, the static contact A of the fifth switch S5 is selectively connected to the four dynamic contacts A1~A4 to select the test pin P21 of the host interface 101. The signal outputted by the P24, for example, the signal outputted by the test pin P21 of the host interface 101 is selected, and the static contact A of the fifth switch S5 is connected to the first dynamic contact A1. Then, the positive and negative probes of an oscilloscope are respectively connected to the first test point P1 and the second test point P2 of the test terminal J1 to perform signal integrity test on the signal outputted by the pin P21 of the host interface 101.

當需要更改該主機介面101之待測引腳P21輸出之訊號,比如透過更改一與該外設介面201相連之監視器之解析度從而更改該主機介面101之待測引腳P21輸出之訊號時,則將該第一開關S1至第四開關S4之靜態觸點1及第一動態觸點2連通,從而使得該主機介面101之待測引腳P21~P24透過主機介面連接器100及外設介面連接器200與該外設介面201之對應引腳T21~T24連接,此時,該主機介面101與外設介面201可正常使用。之後,即可透過更改該監視器之解析度來改變該主機介面101之待測引腳P21輸出之訊號。完成更改之後,再將該第一開關之靜態觸點1與其第二動態觸點3連通,此時即可對該主機介面101之待測引腳P21輸出之訊號進行檢測。When it is necessary to change the signal outputted by the pin P21 of the host interface 101, for example, by changing the resolution of a monitor connected to the peripheral interface 201 to change the signal outputted by the pin P21 of the host interface 101. The static contact 1 of the first switch S1 to the fourth switch S4 and the first dynamic contact 2 are connected, so that the pins P21~P24 of the host interface 101 pass through the host interface connector 100 and peripherals. The interface connector 200 is connected to the corresponding pins T21~T24 of the peripheral interface 201. At this time, the host interface 101 and the peripheral interface 201 can be used normally. After that, the signal outputted by the pin P21 of the host interface 101 can be changed by changing the resolution of the monitor. After the change is completed, the static contact 1 of the first switch is connected to the second dynamic contact 3, and the signal outputted by the pin P21 of the host interface 101 can be detected.

前述訊號測試裝置透過該第一開關S1至第四開關S4控制該主機介面101與外設介面201之連接,並透過該第五開關S5選擇測試該主機介面101之一待測引腳輸出之訊號,避免了測試裝置與外部設備之重複插拔以及示波器探針在測試端J1上之重複插拔,延長主機介面101及示波器探針之使用壽命,縮短測試時間,提高測試精度。The signal testing device controls the connection between the host interface 101 and the peripheral interface 201 through the first switch S1 to the fourth switch S4, and selects a signal for testing the output of the pin to be tested of the host interface 101 through the fifth switch S5. The repeated insertion and removal of the test device and the external device and the repeated insertion and removal of the oscilloscope probe on the test end J1 are avoided, the service life of the host interface 101 and the oscilloscope probe is prolonged, the test time is shortened, and the test accuracy is improved.

綜上所述,本發明符合發明專利要件,爰依法提出專利申請。惟,以上所述者僅為本發明之較佳實施例,舉凡熟悉本案技藝之人士,在爰依本發明精神所作之等效修飾或變化,皆應涵蓋於以下之申請專利範圍內。In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

100...主機介面連接器100. . . Host interface connector

101...主機介面101. . . Host interface

200...外設介面連接器200. . . Peripheral interface connector

201...外設介面201. . . Peripheral interface

S1-S4...二選一開關S1-S4. . . Two-choice switch

S5...多選一開關S5. . . Select one switch

R1-R4...電阻R1-R4. . . resistance

J1...測試端J1. . . Test side

P11-P18...主機介面連接器引腳P11-P18. . . Host interface connector pin

P21-P28...主機介面引腳P21-P28. . . Host interface pin

T11-T18...外設介面連接器引腳T11-T18. . . Peripheral interface connector pin

T21-T28...外設介面引腳T21-T28. . . Peripheral interface pin

1...二選一開關之靜態觸點1. . . Static contact of two switches

2、3...二選一開關之動態觸點2, 3. . . Dynamic selection of two switches

A...多選一開關之靜態觸點A. . . Select one of the static contacts of a switch

A1-A4...多選一開關之動態觸點A1-A4. . . Multiple selection of a dynamic contact

圖1係本發明訊號測試裝置之較佳實施方式之電路圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a preferred embodiment of a signal testing device of the present invention.

100...主機介面連接器100. . . Host interface connector

101...主機介面101. . . Host interface

200...外設介面連接器200. . . Peripheral interface connector

201...外設介面201. . . Peripheral interface

S1-S4...二選一開關S1-S4. . . Two-choice switch

S5...多選一開關S5. . . Select one switch

R1-R4...電阻R1-R4. . . resistance

J1...測試端J1. . . Test side

P11-P18...主機介面連接器引腳P11-P18. . . Host interface connector pin

P21-P28...主機介面引腳P21-P28. . . Host interface pin

T11-T18...外設介面連接器引腳T11-T18. . . Peripheral interface connector pin

T21-T28...外設介面引腳T21-T28. . . Peripheral interface pin

1...二選一開關之靜態觸點1. . . Static contact of two switches

2、3...二選一開關之動態觸點2, 3. . . Dynamic selection of two switches

A...多選一開關之靜態觸點A. . . Select one of the static contacts of a switch

A1-A4...多選一開關之動態觸點A1-A4. . . Multiple selection of a dynamic contact

Claims (7)

一種訊號測試裝置,包括:複數二選一開關,每一二選一開關包括一靜態觸點、一第一動態觸點及一第二動態觸點,該等二選一開關之靜態觸點對應與一主機介面之複數待測引腳相連,該等二選一開關之第一動態觸點對應與一外設介面之複數引腳相連,該主機介面之複數待測引腳對應適配於該外設介面之複數引腳;一多選一開關,包括複數動態觸點及一靜態觸點,該多選一開關之每一動態觸點分別與一二選一開關之第二動態觸點對應相連;以及一測試端,包括一第一測試點及一第二測試點,該第一測試點與該多選一開關之靜態觸點相連,該第二測試點接地;當每一二選一開關之靜態觸點與其第一動態觸點相連時,該主機介面之待測引腳與該外設介面之引腳對應連接;當每一二選一開關之靜態觸點與其第二動態觸點相連時,該主機介面之每一待測引腳分別與該多選一開關之一動態觸點對應相連,透過將該多選一開關之靜態觸點選擇性地與其一動態觸點相連來測試該主機介面之對應待測引腳輸出之訊號。A signal testing device includes: a plurality of selective switches, each of the two switches includes a static contact, a first dynamic contact and a second dynamic contact, and the static contact of the two selected switches Corresponding to a plurality of pins to be tested connected to a host interface, the first dynamic contact of the two switches is connected to a plurality of pins of a peripheral interface, and the plurality of pins to be tested of the host interface are correspondingly adapted to a plurality of pins of the peripheral interface; a plurality of switches, including a plurality of dynamic contacts and a static contact, each dynamic contact of the multiple-selection switch and a second dynamic contact of the switch Correspondingly connected; and a test end comprising a first test point and a second test point, the first test point being connected to the static contact of the multi-select switch, the second test point being grounded; When the static contact of a switch is connected to the first dynamic contact, the pin to be tested of the host interface is connected with the pin of the peripheral interface; when the static contact of each of the two switches is connected with the second dynamic contact When the points are connected, each of the host interfaces is to be tested. Are selected from one of a plurality of the movable contact connected to the corresponding switch via a switch selected from the plurality of stationary contact a movable contact selectively coupled therewith to test the host corresponding to the test signal output pin of the interface. 如申請專利範圍第1項所述之訊號測試裝置,其中每一二選一開關之第二動態觸點還分別透過一電阻接地。The signal testing device of claim 1, wherein the second dynamic contact of each of the two switches is also grounded through a resistor. 如申請專利範圍第1項所述之訊號測試裝置,其中該二選一開關之靜態觸點是透過一主機介面連接器與該主機介面之待測引腳相連。The signal testing device of claim 1, wherein the static contact of the two switches is connected to the pin to be tested of the host interface through a host interface connector. 如申請專利範圍第1項所述之訊號測試裝置,其中該二選一開關之第一動態觸點是透過一外設介面連接器與該外設介面之引腳相連。The signal testing device of claim 1, wherein the first dynamic contact of the two-select switch is connected to a pin of the peripheral interface through a peripheral interface connector. 如申請專利範圍第1項所述之訊號測試裝置,其中該二選一開關為單刀雙擲開關。The signal testing device of claim 1, wherein the two-selection switch is a single-pole double-throw switch. 如申請專利範圍第1項所述之訊號測試裝置,其中該多選一開關為單刀多擲開關。The signal testing device of claim 1, wherein the multi-selection switch is a single-pole multi-throw switch. 如申請專利範圍第1項所述之訊號測試裝置,其中該測試端為一具有兩個針頭之插件,其兩個針頭分別作為該第一測試點及第二測試點。The signal testing device of claim 1, wherein the test end is an insert having two needles, and the two needles serve as the first test point and the second test point, respectively.
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TW200630672A (en) * 2005-02-25 2006-09-01 Au Optronics Corp System and method for display testing
US20070016729A1 (en) * 2005-07-12 2007-01-18 Correale Anthony Jr Cache organization for power optimized memory access
TW200844462A (en) * 2006-12-13 2008-11-16 Renesas Tech Corp Method of on-chip current measurement and semiconductor IC

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TW200630672A (en) * 2005-02-25 2006-09-01 Au Optronics Corp System and method for display testing
US20070016729A1 (en) * 2005-07-12 2007-01-18 Correale Anthony Jr Cache organization for power optimized memory access
TW200844462A (en) * 2006-12-13 2008-11-16 Renesas Tech Corp Method of on-chip current measurement and semiconductor IC

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