TWI402511B - Peak detector - Google Patents
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- TWI402511B TWI402511B TW99125543A TW99125543A TWI402511B TW I402511 B TWI402511 B TW I402511B TW 99125543 A TW99125543 A TW 99125543A TW 99125543 A TW99125543 A TW 99125543A TW I402511 B TWI402511 B TW I402511B
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- 239000003990 capacitor Substances 0.000 claims description 60
- 238000001514 detection method Methods 0.000 claims description 4
- 238000003079 width control Methods 0.000 description 6
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Description
本發明係有關於一種偵測電路，特別係有關於一種使該偵測電路輸出端可同步儲存輸出端之電壓峰值訊號之峰值偵測電路。 The invention relates to a detecting circuit, in particular to a peak detecting circuit for enabling a voltage peak signal of an output end of the detecting circuit to be synchronously stored.
習知峰值偵測器200，如中華民國公告專利第468050號所示，請參閱第2圖，該峰值偵測器200係具有一輸入訊號端210、一比較器220、一及閘230、一輸入觸發器240、一閘極寬度控制區塊250、至少一電流源260、至少一開關270及一電容器280，該輸入訊號端210係可產生一輸入訊號，該比較器220之一正極端221及該輸入觸發器240係電性連接該輸入訊號端210，該閘極寬度控制區塊250係電性連接該輸入觸發器240，該及閘230之一端係電性連接該比較器220之一輸出端223，該及閘230之另一端係電性連接該閘極寬度控制區塊250，該第一開關260係電性連接該電容器280或該第一電流源270及該及閘230，該第二開關261係電性連接該第二電流源271或該閘極寬度控制區塊250及該電容器280，該峰值偵測器200係藉由該及閘230控制該第一開關260及該閘極寬度控制區塊250控制該第二開關261以決定該電容器280之充電或放電動作，惟，由該電容器280之輸出波形可得知，該偵測器仍造成該輸入訊號之訊號衰減，因此該電容器280之輸出訊號無法有效精確獲得該輸入訊號之電壓峰值。 For example, as shown in FIG. 2, the peak detector 200 has an input signal terminal 210, a comparator 220, a gate 230, and a gate detector 200. The input flip-flop 240, the gate width control block 250, the at least one current source 260, the at least one switch 270, and a capacitor 280, the input signal terminal 210 can generate an input signal, and the positive terminal 221 of the comparator 220 The input trigger 240 is electrically connected to the input signal terminal 210. The gate width control block 250 is electrically connected to the input flip-flop 240. One end of the AND gate 230 is electrically connected to one of the comparators 220. The output terminal 223 is electrically connected to the gate width control block 250. The first switch 260 is electrically connected to the capacitor 280 or the first current source 270 and the gate 230. The second switch 261 is electrically connected to the second current source 271 or the gate width control block 250 and the capacitor 280. The peak detector 200 controls the first switch 260 and the gate by the gate 230 The pole width control block 250 controls the second switch 261 to determine the capacitance The charging or discharging operation of the device 280, however, can be known from the output waveform of the capacitor 280, the detector still causes the signal attenuation of the input signal, so the output signal of the capacitor 280 cannot effectively obtain the voltage of the input signal. Peak.
一種峰值偵測電路，其包含一電壓訊號輸入端、一第一比較器、一第一電容、一第一開關、一第二開關、一第一重置訊號端、一第三開關、一第二比較器、一第四開關、一正反器、一第二重置訊號端、一第二電容及一第五開關，該電壓訊號輸入端係用以提供一電壓輸入訊號，第一比較器係電性連接該電壓訊號輸入端，該第一電容具有一第一電壓端，該第一電容係電性連接該第一比較器，該第一開關係電性連接該電壓訊號輸入端及該第一比較器或該第一電容，該第二開關係電性連接該第一電容及該第一比較器，該第一重置訊號端係電性連接該第二開關，該第三開關係電性連接該第二開關及該第一重置訊號端，該第二比較器係電性連接該第三開關，該第四開關係電性連接該第一比較器、該第一電容及該第二開關或該第二比較器及該第三開關，該正反器係電性連接該第二比較器，該第二重置訊號端係電性連接該正反器，該第二電容係具有一第二電壓端，該第二電容係電性連接該第二比較器，該第五開關係電性連接該第三開關、該第二比較器之一端及該正反器或該第二比較器之另一端及該第二電容，其中該第一比較器係用以控制該第一開關之切換動作，該第一重置訊號端係用以控制該第二開關、該第三開關及該第四開關之切換動作，該正反器係用以控制該第五開關之切換動作。本發明係藉由該第四開關及該第五開關之切換動作，可使得該第一電壓端及該第二電壓端可同步儲存該電壓訊號之電壓峰值，此外，藉由該第二比較器之比較功能，隨後輸 入該第一電壓端之該電壓訊號之峰值若低於原先儲存於該第二電壓端之該電壓訊號之峰值，則該正反器係輸出一低電位訊號而使得該第五開關與該第二電容呈斷路狀態，反之，若隨後輸入該第一電壓端之該電壓訊號之峰值高於原先儲存於該第二電壓端之該電壓訊號之峰值，該正反器即輸出一高電位訊號而使得該第二電容可儲存更高之該電壓訊號之電壓峰值，本發明可有效避免該電壓輸入訊號儲存於該第一電壓端時，該第二電壓端之電壓輸入訊號之電壓峰值不低於該第一電壓端之電壓輸入訊號之電壓峰值。 A peak detecting circuit includes a voltage signal input terminal, a first comparator, a first capacitor, a first switch, a second switch, a first reset signal terminal, a third switch, and a first a comparator, a fourth switch, a flip-flop, a second reset signal terminal, a second capacitor and a fifth switch, wherein the voltage signal input terminal is configured to provide a voltage input signal, and the first comparator Electrically connecting the voltage signal input end, the first capacitor has a first voltage end, the first capacitor is electrically connected to the first comparator, and the first open relationship is electrically connected to the voltage signal input end and the a first comparator or the first capacitor, the second open relationship is electrically connected to the first capacitor and the first comparator, and the first reset signal end is electrically connected to the second switch, the third open relationship Electrically connecting the second switch and the first reset signal terminal, the second comparator is electrically connected to the third switch, and the fourth open relationship is electrically connected to the first comparator, the first capacitor, and the a second switch or the second comparator and the third switch, the flip-flop Electrically connecting the second comparator, the second reset signal is electrically connected to the flip-flop, the second capacitor has a second voltage end, and the second capacitor is electrically connected to the second comparator The fifth open relationship is electrically connected to the third switch, one end of the second comparator, the other end of the flip-flop or the second comparator, and the second capacitor, wherein the first comparator is used to Controlling a switching action of the first switch, the first reset signal end is configured to control a switching action of the second switch, the third switch, and the fourth switch, wherein the flip-flop is used to control the fifth switch Switching action. The switching operation of the fourth switch and the fifth switch enables the first voltage terminal and the second voltage terminal to synchronously store the voltage peak of the voltage signal, and further, by using the second comparator Comparison function, then lose If the peak value of the voltage signal entering the first voltage terminal is lower than the peak value of the voltage signal originally stored in the second voltage terminal, the flip-flop outputs a low-potential signal to cause the fifth switch and the first The second capacitor is in an open state. Otherwise, if the peak value of the voltage signal input to the first voltage terminal is higher than the peak value of the voltage signal originally stored in the second voltage terminal, the flip-flop outputs a high-potential signal. The second capacitor can store a higher voltage peak value of the voltage signal. The invention can effectively prevent the voltage input signal of the second voltage terminal from being lower than the voltage peak value when the voltage input signal is stored at the first voltage terminal. The voltage at the first voltage terminal inputs the voltage peak of the signal.
請參閱第1圖，其係本發明之一較佳實施例，一種峰值偵測電路1係包含一電壓訊號輸入端10、一第一比較器20、一第一電容30、一第一開關40、一第二開關50、一第一重置訊號端60、一第三開關70、一第二比較器80、一第四開關90一正反器100、一第二重置訊號端110、一第二電容120及一第五開關130，該電壓訊號輸入端10係用以提供一電壓輸入訊號，第一比較器20係電性連接該電壓訊號輸入端10，該第一電容30具有一第一電壓端31，該第一電容30係電性連接該第一比較器20，該第一開關40係電性連接該電壓訊號輸入端10及該第一比較器20或該第一電容30，該第二開關50係電性連接該第一電容30及該第一比較器20，該第一重置訊號端60係電性連接該第二開關50，該第三開關70係電性連接該第二開關50及該第一重置訊號端60，該第二比較器80係電性連接該第三開關70，該第四開關90係電性連接該第一比較器 20、該第一電容30及該第二開關50或該第三開關70及該第二比較器80，該正反器100係電性連接該第二比較器80，該第二重置訊號端110係電性連接該正反器100，該第二電容120係具有一第二電壓端121，該第二電容120係電性連接該第二比較器80之一端，該第五開關130係電性連接該第三開關70、該第二比較器80之一端及該正反器100或該第二比較器80之另一端及該第二電容120，其中該第一比較器20係用以控制該第一開關40之切換動作，該第一重置訊號端60係用以控制該第二開關50、該第三開關70及該第四開關90之切換動作，該正反器100係用以控制該第五開關130之切換動作。 Please refer to FIG. 1 , which is a preferred embodiment of the present invention. A peak detecting circuit 1 includes a voltage signal input terminal 10 , a first comparator 20 , a first capacitor 30 , and a first switch 40 . a second switch 50, a first reset signal terminal 60, a third switch 70, a second comparator 80, a fourth switch 90, a flip-flop 100, a second reset signal terminal 110, and a second reset signal terminal 110 a second capacitor 120 and a fifth switch 130, wherein the voltage signal input terminal 10 is configured to provide a voltage input signal, and the first comparator 20 is electrically connected to the voltage signal input terminal 10. The first capacitor 30 has a first a voltage terminal 31, the first capacitor 30 is electrically connected to the first comparator 20, the first switch 40 is electrically connected to the voltage signal input terminal 10 and the first comparator 20 or the first capacitor 30, The second switch 50 is electrically connected to the first capacitor 30 and the first comparator 20, and the first reset signal terminal 60 is electrically connected to the second switch 50. The third switch 70 is electrically connected to the second switch 70. a second switch 50 and the first reset signal terminal 60, the second comparator 80 is electrically connected to the third switch 70, the fourth switch 90 based electrically connected to the first comparator The first capacitor 30 and the second switch 50 or the third switch 70 and the second comparator 80 are electrically connected to the second comparator 80. The second reset signal terminal The 110 series is electrically connected to the flip-flop 100. The second capacitor 120 has a second voltage terminal 121. The second capacitor 120 is electrically connected to one end of the second comparator 80. The fifth switch 130 is electrically connected. The third switch 70, one end of the second comparator 80, the other end of the flip-flop 100 or the second comparator 80, and the second capacitor 120 are connected, wherein the first comparator 20 is used for controlling The switching operation of the first switch 40 is used to control the switching action of the second switch 50, the third switch 70 and the fourth switch 90, and the flip-flop 100 is used for The switching operation of the fifth switch 130 is controlled.
請再參閱第1圖，當該峰值偵測電路1處於初始位置時須作重置動作，在本實施例中，第1圖所示係為該些開關之初始位置，首先，該第一重置訊號端60係輸入高電位、該第二重置訊號端110輸入低電位，該第一重置訊號端60之高電位係可使得該第二開關50及該第三開關70切換至接地，該第四開關90維持關閉，該第二重置訊號端110之低電位係可使該第五開關130維持初始位置，由於該第二開關50切換至接地，因此儲存於該第一電容30之初始電壓可經由接地放電至零伏特，另外，在本實施例中，該正反器100係具有一時脈接收端101、一訊號輸出端102及一重置訊號接收端103，該第二比較器80係電性連接該時脈接收端101，該第五開關130係電性連接該訊號輸出端102，該第二重置訊號端110係電性連接該重置訊號接收端103，由於該第三開關70切換至接地，因此該 第二比較器80係輸出一低電位至該時脈接收端101而使得該訊號輸出端102輸出為零伏特，又，該峰值偵測器1係另具有一反相器140，該反相器140之一端係電性連接該第一重置訊號端60，該反相器140之另一端係電性連接該第四開關90，該第四開關90係經由該反相器140輸出一低電位而使得該第四開關90維持關閉，使得該第二電壓端121不受該第一電壓端31之放電動作影響。 Referring to FIG. 1 again, when the peak detecting circuit 1 is in the initial position, a resetting operation is required. In the embodiment, FIG. 1 is the initial position of the switches. First, the first weight The signal terminal 60 is input to the high potential, and the second reset signal terminal 110 is input to the low potential. The high potential of the first reset signal terminal 60 can cause the second switch 50 and the third switch 70 to be switched to the ground. The fourth switch 90 is kept off. The low level of the second reset signal terminal 110 can maintain the fifth switch 130 in an initial position. Since the second switch 50 is switched to ground, it is stored in the first capacitor 30. The initial voltage can be discharged to zero volts via the ground. In addition, in the embodiment, the flip-flop 100 has a clock receiving end 101, a signal output end 102 and a reset signal receiving end 103. The second comparator The 80-series is electrically connected to the clock receiving end 101, the fifth switch 130 is electrically connected to the signal output end 102, and the second reset signal end 110 is electrically connected to the reset signal receiving end 103. The three switch 70 is switched to ground, so the The second comparator 80 outputs a low potential to the clock receiving end 101 such that the signal output terminal 102 outputs zero volts. Further, the peak detector 1 further has an inverter 140, the inverter One end of the 140 is electrically connected to the first reset signal terminal 60, and the other end of the inverter 140 is electrically connected to the fourth switch 90. The fourth switch 90 outputs a low potential via the inverter 140. The fourth switch 90 is kept closed, so that the second voltage terminal 121 is not affected by the discharging action of the first voltage terminal 31.
接著，請再參閱第1圖，重置動作結束後，該第一重置訊號端60係輸出一低電位，第二重置訊號端110維持低電位，該第一重置訊號端60係使得該第二開關50及該第三開關70切換至初始位置，該第四開關90導通，此時該電壓訊號輸入端10係可提供該電壓輸入訊號，在本實施例中，該第一比較器20係具有一正極端21、一負極端22及一輸出端23，該電壓訊號輸入端10係電性連接該正極端21，該第一電容30之第一電壓端31、該第二開關50及該第四開關90係電性連接該負極端22，該第一開關40係電性連接該輸出端23，由於該電壓輸入訊號係大於該第一重置訊號端60之低電位，因此該第一比較器20之該輸出端23係可輸出一高電位訊號而使該第一開關40切換至該第一電壓端31，因此該電壓輸入訊號係輸送至該第一電容30而進行充電，在本實施例中，該第二比較器80係具有一正極端81、一負極端82及一輸出端83，該第三開關70及該第五開關130係電性連接該正極端81，該第二電容120之該第二電壓端121係電性連接該負極端82，該正反器100之該時脈接收端101係電性連接該輸出端83，當 該第四開關90導通時，該第一電壓端31係可電性連接該正極端81，由於此時該正極端81之端電壓高於該負極端82之端電壓，因此該輸出端83係可輸出一高電位而使得該正反器100之該訊號輸出端102輸出一高電位訊號，故該第五開關130可切換至該第二電壓端121，該第一電容30之該第一電壓端31係因電性連接該第二電容120之該第二電壓端121而使得該電壓輸入訊號之電壓峰值可同步儲存於該第一電容30及該第二電容120。 Next, please refer to FIG. 1 again. After the resetting operation ends, the first reset signal terminal 60 outputs a low potential, and the second reset signal terminal 110 maintains a low potential. The first reset signal terminal 60 is caused by the first reset signal terminal 60. The second switch 50 and the third switch 70 are switched to the initial position, and the fourth switch 90 is turned on. At this time, the voltage signal input terminal 10 can provide the voltage input signal. In this embodiment, the first comparator The 20 series has a positive terminal 21, a negative terminal 22 and an output terminal 23. The voltage signal input terminal 10 is electrically connected to the positive terminal 21, the first voltage terminal 31 of the first capacitor 30, and the second switch 50. The fourth switch 90 is electrically connected to the negative terminal 22, and the first switch 40 is electrically connected to the output terminal 23. Since the voltage input signal is greater than the low potential of the first reset signal terminal 60, the The output terminal 23 of the first comparator 20 can output a high potential signal to switch the first switch 40 to the first voltage terminal 31, so that the voltage input signal is sent to the first capacitor 30 for charging. In this embodiment, the second comparator 80 has a positive terminal 81, A negative terminal 82 and an output terminal 83, the third switch 70 and the fifth switch 130 are electrically connected to the positive terminal 81, and the second voltage terminal 121 of the second capacitor 120 is electrically connected to the negative terminal 82. The clock receiving end 101 of the flip-flop 100 is electrically connected to the output end 83, when When the fourth switch 90 is turned on, the first voltage terminal 31 is electrically connected to the positive terminal 81. Since the terminal voltage of the positive terminal 81 is higher than the terminal voltage of the negative terminal 82, the output terminal 83 is A high potential can be output to cause the signal output terminal 102 of the flip-flop 100 to output a high potential signal, so the fifth switch 130 can be switched to the second voltage terminal 121, and the first voltage of the first capacitor 30 The terminal 31 is electrically connected to the second voltage terminal 121 of the second capacitor 120 so that the voltage peak of the voltage input signal can be synchronously stored in the first capacitor 30 and the second capacitor 120.
請再參閱第1圖，在本實施例中，該電壓訊號輸入端10之該電壓輸入訊號於每80us即更新一次，且該第一電壓端31之端電壓係藉由該第一重置訊號端60於每80us即重複上述之重置動作，每次之重置時間持續10us，在每次重置動作前，該第二重置訊號端110係比該第一重置訊號端60提早10us提供高電位，其係使得該第五開關130可先行恢復初始位置再進行重置動作，以避免該第一電壓端31之放電動作影響該第二電壓端121，在本實施例中，隨後輸入該第一電壓端31之該電壓訊號之電壓峰值若低於原先儲存於該第二電壓端121之該電壓訊號之電壓峰值，則該第二比較器80之該正極端81電壓係因小於該負極端82電壓而使得該正反器100之該訊號輸出端102輸出一低電位訊號，因此該第五開關130係可維持初始位置，該第二電壓端121仍可維持原先儲存於該第二電容120之電壓峰值準位，相反地，隨後輸入該第一電壓端31之該電壓訊號之電壓峰值若高於原先儲存於該第二電壓端121之該電壓訊號之電壓峰值，則該第二比較器80之該正極 端81電壓係因大於該負極端82電壓而使得該正反器100之該訊號輸出端102輸出一高電位訊號，此時該第五開關130係可切換至該第二電壓端121，該第二電壓端121係因再度電性連接該第一電壓端31而使得該第二電容120可儲存更高之該電壓輸入訊號之電壓峰值。 Please refer to FIG. 1 again. In this embodiment, the voltage input signal of the voltage signal input terminal 10 is updated every 80 us, and the voltage of the first voltage terminal 31 is terminated by the first reset signal. The terminal 60 repeats the above resetting action every 80 us, and each reset time lasts 10 us. Before each resetting operation, the second reset signal terminal 110 is 10us earlier than the first reset signal terminal 60. Providing a high potential, the fifth switch 130 can first restore the initial position and then perform a resetting operation to prevent the discharge action of the first voltage terminal 31 from affecting the second voltage terminal 121. In this embodiment, the input is subsequently performed. If the voltage peak of the voltage signal of the first voltage terminal 31 is lower than the voltage peak of the voltage signal originally stored in the second voltage terminal 121, the voltage of the positive terminal 81 of the second comparator 80 is smaller than the voltage. The voltage of the negative terminal 82 causes the signal output terminal 102 of the flip-flop 100 to output a low potential signal, so that the fifth switch 130 can maintain the initial position, and the second voltage terminal 121 can still remain stored in the second The voltage peak level of the capacitor 120, If the peak voltage of the voltage signal Conversely, then the first voltage input terminal 31 is higher than the peak voltage of the voltage signal previously stored in the second end 121 of the voltage, the second comparator 80 of the positive electrode The voltage of the terminal 81 is greater than the voltage of the negative terminal 82, so that the signal output terminal 102 of the flip-flop 100 outputs a high-potential signal, and the fifth switch 130 can be switched to the second voltage terminal 121. The second voltage terminal 121 is electrically connected to the first voltage terminal 31 so that the second capacitor 120 can store a higher voltage peak of the voltage input signal.
請再參閱第1圖，該峰值偵測器1係另具有一電源供應器150、一第三重置訊號端160及一電性連接該第三重置訊號端160之第六開關170，該電源供應器150係電性連接該第一比較器20及該第二比較器80，該第六開關170係電性連接該第二比較器80之該負極端82及該第二電容120之該第二電壓端121，該第三重置訊號端160係用以控制該第六開關170之切換動作，在本實施例中，若欲進行另一電壓輸入訊號之訊號輸入動作，該第三重置訊號端160係可輸入一高電位而使得該第六開關170被切換至接地，該第二電容120係因電性連接至接地而放電至零伏特。本發明係藉由該第四開關90及該第五開關130之切換動作而使該第一電壓端31電性連接該第二電壓端121，因此該第一電容30及該第二電容120可同步儲存該電壓訊號輸入端10之該電壓輸入訊號之電壓峰值，此外，藉由該第二比較器80之比較功能，隨後輸入該第一電壓端31之該電壓輸入訊號之電壓峰值若低於原先儲存於該第二電壓端121之該電壓輸入訊號之電壓峰值，則該正反器100係輸出一低電位訊號而使得該第五開關130與該第二電容120呈斷路狀態，該第二電壓端121仍可維持原先儲存於該第二電容120之電壓峰值準位，反之，若隨後輸入該第 一電壓端31之該電壓輸入訊號之電壓峰值若高於原先儲存於該第二電壓端121之該電壓輸入訊號之電壓峰值，該正反器100即輸出一高電位訊號而使得該第二電容120可儲存更高之該電壓輸入訊號之電壓峰值，本發明可有效避免該電壓輸入訊號儲存於該第一電壓端31時，該第二電壓端121之電壓輸入訊號之電壓峰值不低於該第一電壓端31之電壓輸入訊號之電壓峰值。 Referring to FIG. 1 again, the peak detector 1 further includes a power supply 150, a third reset signal end 160, and a sixth switch 170 electrically connected to the third reset signal end 160. The power supply 150 is electrically connected to the first comparator 20 and the second comparator 80. The sixth switch 170 is electrically connected to the negative terminal 82 and the second capacitor 120 of the second comparator 80. The second voltage terminal 121 is configured to control the switching operation of the sixth switch 170. In this embodiment, if the signal input action of another voltage input signal is to be performed, the third weight is The signal terminal 160 can input a high potential such that the sixth switch 170 is switched to ground, and the second capacitor 120 is discharged to zero volts by being electrically connected to the ground. In the present invention, the first voltage terminal 31 is electrically connected to the second voltage terminal 121 by the switching operation of the fourth switch 90 and the fifth switch 130. Therefore, the first capacitor 30 and the second capacitor 120 can be Simultaneously storing the voltage peak of the voltage input signal of the voltage signal input terminal 10, and further, by the comparison function of the second comparator 80, the voltage peak value of the voltage input signal input to the first voltage terminal 31 is lower than The voltage of the voltage input signal originally stored in the second voltage terminal 121 is a peak value, and the flip-flop 100 outputs a low potential signal to cause the fifth switch 130 and the second capacitor 120 to be in an open state. The voltage terminal 121 can still maintain the voltage peak level originally stored in the second capacitor 120, and if so, enter the first If the voltage peak of the voltage input signal of a voltage terminal 31 is higher than the voltage peak of the voltage input signal originally stored at the second voltage terminal 121, the flip-flop 100 outputs a high potential signal to make the second capacitor 120 can store a higher voltage peak value of the voltage input signal, and the invention can effectively prevent the voltage input signal of the second voltage terminal 121 from being lower than the voltage peak when the voltage input signal is stored at the first voltage terminal 31. The voltage of the first voltage terminal 31 is the voltage peak of the input signal.
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。 The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
1‧‧‧峰值偵測電路 1‧‧‧ Peak detection circuit
10‧‧‧電壓訊號輸入端 10‧‧‧Voltage signal input
20‧‧‧第一比較器 20‧‧‧First comparator
21‧‧‧正極端 21‧‧‧ positive end
22‧‧‧負極端 22‧‧‧Negative end
23‧‧‧輸出端 23‧‧‧ Output
30‧‧‧第一電容 30‧‧‧first capacitor
31‧‧‧第一電壓端 31‧‧‧First voltage terminal
40‧‧‧第一開關 40‧‧‧First switch
50‧‧‧第二開關 50‧‧‧second switch
60‧‧‧第一重置訊號端 60‧‧‧First reset signal end
70‧‧‧第三開關 70‧‧‧third switch
80‧‧‧第二比較器 80‧‧‧Second comparator
81‧‧‧正極端 81‧‧‧ positive end
82‧‧‧負極端 82‧‧‧Negative end
83‧‧‧輸出端 83‧‧‧ Output
90‧‧‧第四開關 90‧‧‧fourth switch
100‧‧‧正反器 100‧‧‧Fracture
101‧‧‧時脈接收端 101‧‧‧clock receiver
102‧‧‧訊號輸出端 102‧‧‧ signal output
103‧‧‧重置訊號接收端 103‧‧‧Reset signal receiver
110‧‧‧第二重置訊號端 110‧‧‧Second reset signal end
120‧‧‧第二電容 120‧‧‧second capacitor
121‧‧‧第二電壓端 121‧‧‧second voltage terminal
130‧‧‧第五開關 130‧‧‧ fifth switch
140‧‧‧反相器 140‧‧‧Inverter
150‧‧‧電源供應器 150‧‧‧Power supply
160‧‧‧第三重置訊號端 160‧‧‧ Third reset signal end
170‧‧‧第六開關 170‧‧‧ sixth switch
200‧‧‧峰值偵測器 200‧‧‧ Peak Detector
210‧‧‧輸入訊號端 210‧‧‧Input signal end
220‧‧‧比較器 220‧‧‧ comparator
221‧‧‧正極端 221‧‧‧ positive end
222‧‧‧負極端 222‧‧‧Negative end
223‧‧‧輸出端 223‧‧‧output
230‧‧‧及閘 230‧‧‧ and gate
240‧‧‧輸入觸發器 240‧‧‧Input trigger
250‧‧‧閘極寬度控制區塊 250‧‧ ‧ gate width control block
260‧‧‧第一開關 260‧‧‧ first switch
261‧‧‧第二開關 261‧‧‧second switch
270‧‧‧第一電流源 270‧‧‧First current source
271‧‧‧第二電流源 271‧‧‧second current source
280‧‧‧電容器 280‧‧‧ capacitor
第1圖：依據本發明之第一較佳實施例，一種峰值偵測電路之電路圖。 Figure 1 is a circuit diagram of a peak detecting circuit in accordance with a first preferred embodiment of the present invention.
第2圖：習知峰值偵測電路之電路圖。 Figure 2: Circuit diagram of a conventional peak detection circuit.
1‧‧‧峰值偵測電路 1‧‧‧ Peak detection circuit
10‧‧‧電壓訊號輸入端 10‧‧‧Voltage signal input
20‧‧‧第一比較器 20‧‧‧First comparator
21‧‧‧正極端 21‧‧‧ positive end
22‧‧‧負極端 22‧‧‧Negative end
23‧‧‧輸出端 23‧‧‧ Output
30‧‧‧第一電容 30‧‧‧first capacitor
31‧‧‧第一電壓端 31‧‧‧First voltage terminal
40‧‧‧第一開關 40‧‧‧First switch
50‧‧‧第二開關 50‧‧‧second switch
60‧‧‧第一重置訊號端 60‧‧‧First reset signal end
70‧‧‧第三開關 70‧‧‧third switch
80‧‧‧第二比較器 80‧‧‧Second comparator
81‧‧‧正極端 81‧‧‧ positive end
82‧‧‧負極端 82‧‧‧Negative end
83‧‧‧輸出端 83‧‧‧ Output
90‧‧‧第四開關 90‧‧‧fourth switch
100‧‧‧正反器 100‧‧‧Fracture
101‧‧‧時脈接收端 101‧‧‧clock receiver
102‧‧‧訊號輸出端 102‧‧‧ signal output
103‧‧‧重置訊號接收端 103‧‧‧Reset signal receiver
110‧‧‧第二重置訊號端 110‧‧‧Second reset signal end
120‧‧‧第二電容 120‧‧‧second capacitor
121‧‧‧第二電壓端 121‧‧‧second voltage terminal
130‧‧‧第五開關 130‧‧‧ fifth switch
140‧‧‧反相器 140‧‧‧Inverter
150‧‧‧電源供應器 150‧‧‧Power supply
160‧‧‧第三重置訊號端 160‧‧‧ Third reset signal end
170‧‧‧第六開關 170‧‧‧ sixth switch
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99125543A TWI402511B (en) | 2010-07-30 | 2010-07-30 | Peak detector |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99125543A TWI402511B (en) | 2010-07-30 | 2010-07-30 | Peak detector |
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| TW201205087A TW201205087A (en) | 2012-02-01 |
| TWI402511B true TWI402511B (en) | 2013-07-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002233143A (en) * | 2001-01-30 | 2002-08-16 | Shindengen Electric Mfg Co Ltd | Synchronous rectifying converter |
| US20050184716A1 (en) * | 2004-02-20 | 2005-08-25 | International Rectifier Corporation | Apparatus and method for minimizing power loss associated with dead time |
| TW200824343A (en) * | 2006-11-16 | 2008-06-01 | Qualcomm Inc | Peak signal detector |
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2010
- 2010-07-30 TW TW99125543A patent/TWI402511B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002233143A (en) * | 2001-01-30 | 2002-08-16 | Shindengen Electric Mfg Co Ltd | Synchronous rectifying converter |
| US20050184716A1 (en) * | 2004-02-20 | 2005-08-25 | International Rectifier Corporation | Apparatus and method for minimizing power loss associated with dead time |
| TW200824343A (en) * | 2006-11-16 | 2008-06-01 | Qualcomm Inc | Peak signal detector |
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