TWI401515B - Method of forming pixel structure - Google Patents

Description

Method of forming a pixel structure

SUMMARY OF THE INVENTION The present invention is directed to a method of forming a pixel structure, and more particularly to a method of forming a pixel structure that is shielded above a data line (SAD).

In the manufacture of liquid crystal displays, the size of the element pixel aperture ratio directly affects the utilization of the backlight and also affects the display brightness of the panel. The main factor affecting the aperture ratio is the distance between the pixel electrode and the data line. However, when the pixel is too close to the data line, the capacitance between the pixel and the data line (Cpd) will become larger, causing the charged charge on the pixel electrode to be converted before the next frame. A cross talk is generated by transmitting different voltages to the data line.

In order to reduce the effect of stray capacitance, many methods have been studied. For example, when a stable electric field is used as a shield between the pixel electrode and the data line, the parasitic capacitance of the data line to the pixel electrode can be reduced. Hereinafter, a pixel structure having a shield electrode will be described with reference to FIGS. 1 and 2. 1 is a top view of a conventional pixel structure, and FIG. 2 is a schematic cross-sectional view of FIG. 1 taken along a section line Z-Z'. As shown in FIG. 1 and FIG. 2, the pixel structure includes a lower substrate 10, a scan line 12, a common electrode 14, a gate insulating layer 32, a channel structure 16, a data line 18, a drain electrode 20, and a passivation layer. 34. A pixel electrode 28, a connection layer 30, an upper substrate 40, a black matrix 42, a color filter 44, and a common electrode 46.

The scan line 12 and the common electrode 14 are both formed by the first conductive layer and disposed on the lower substrate 10. Wherein, each scan line 12 can extend laterally across a plurality of sub-pixel regions. Each of the scanning lines 12 has a plurality of gate electrode portions corresponding to the respective pixel regions. The common electrode 14 is disposed corresponding to three sides of each pixel region, and is not connected or crossed across the scan line 12. The gate insulating layer 32 covers the scan line 12 and the common electrode 14 in a comprehensive manner, and the channel structure 16 is disposed above the gate insulating layer 32, corresponding to each gate electrode portion of the scan line 12. The data line 18 and the drain electrode 20 are both formed by a second conductive layer disposed on the scan line 12, the common electrode 14, the gate insulating layer 32, and the channel structure 16. The data line 18 can extend longitudinally across the scan line 12. Each data line 18 has a plurality of source electrode portions, and both the source electrode portion and the drain electrode 20 are in contact with the channel structure 16 to form a structure of a thin film transistor.

The protective layer 34 covers the gate insulating layer 32, the channel structure 16, the data line 18 and the drain electrode 20, and has a contact hole 22, a contact hole 24 and a contact hole 26. Each of the pixel regions is provided with a contact hole 22 for exposing the drain electrode 20, and only one sub-pixel region of the pixel structure is provided with a contact hole 24 and a contact hole 26 for exposing the common Electrode 14. The pixel electrode 28 and the connection layer 30 are both formed of a transparent conductive layer and are disposed on the protective layer 34. The pixel electrode 28 is connected to the drain electrode 20 through the contact hole 22, and is combined with the common electrode 46 of the upper substrate 40 to control the liquid crystal layer 36. The connection layer 30 corresponds to the contact hole 24 and the contact hole 26 and is located only in the single-primary pixel region. The connection layer 30 spans the scan line 12 and penetrates the common electrode 14 of a different pixel structure through the contact hole 24 and the contact hole 26.

The black matrix 42 is located inside the upper substrate 40 and is disposed corresponding to each pixel region to shield the light leakage region. Each of the color filters 44 is also provided corresponding to each pixel region, and can have various desired colors and be imaged in accordance with the gray scale brightness provided by the sub-pixel regions.

The common electrode 14 is located below the data line 18 and serves as a shielding electrode to form a pixel structure with a shielding under the data line (SUD). Although the common electrode 14 can reduce the parasitic capacitance effect of the data line 18 on the pixel electrode 28, the pixel electrode 28 and the common electrode 14 are partially overlapped. However, in this structure, the conductive structures must have an appropriate spacing between them. More specifically, the layout of each conductive structure has the following limitations:

(1) Since both the scan line 12 and the common electrode 14 are formed by the first conductive layer, in order to consider the process yield problem, the scanning line 12 and the common electrode 14 need a certain distance between them.

(2) In order to avoid stray capacitance caused by signal coupling, a certain distance between the pixel electrode 28 and the data line 18 is required.

(3) Similarly, in order to avoid stray capacitance caused by signal coupling, a certain distance between the pixel electrode 28 and the scanning line 12 is required.

(4) Since the existence of the connection layer 30 reduces the area of the pixel electrode 28, in order to avoid a large drop in the aperture ratio, the common electrode 14 can be connected only by the connection layer 30 in a single-pixel area, that is, only in a single Make a mesh connection in the prime pixel area.

Therefore, the conventional pixel structure still requires a large area of black matrix to shield the light leakage region, so that the aperture ratio cannot be effectively reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming a pixel structure to solve the aforementioned conventional problems.

The present invention provides a method of forming a pixel structure. The method first provides a substrate on which a patterned first conductive layer is formed, including a scan line and a data line segment. Thereafter, a gate insulating layer is formed on the scan line and the data line segment. Then, a semiconductor layer is formed on the gate insulating layer, and then part of the semiconductor layer and a portion of the gate insulating layer are removed to form a channel structure, a first isolation structure and a second isolation structure, and a portion of the data line segment is exposed, wherein The channel structure and the first isolation structure partially overlap the scan line, and the second isolation structure partially overlaps the data line segment. Thereafter, a second conductive layer is formed on the data line segment, the channel structure, and the first and second isolation structures. Then, a portion of the second conductive layer is removed to form a source electrode, a drain electrode and a common electrode, wherein the common electrode portion overlaps the first and second isolation structures, the source electrode contacts the data line segment and the channel structure, and the drain electrode The electrode contacts the channel structure. Thereafter, a dielectric layer is formed on the channel structure, the source electrode, the drain electrode, and the common electrode, and the dielectric layer exposes a portion of the drain electrode. Subsequently, a pixel electrode is formed on the dielectric layer, and the pixel electrode is electrically connected to the drain electrode.

According to the above method, the present invention can produce the pixel structure of the SAD without using a translucent cover or a halftone mask. The source electrode of the second conductive layer may directly contact the data line segment of the first conductive layer as a data line for transmitting the data signal. In this way, the present invention maintains the low impedance of the data line. In addition, since the present invention can utilize the common electrode of the second conductive layer to shield the signal coupling between the pixel electrode and the data line segment of the first conductive layer, and the common electrode of the second conductive layer can be used to shield the pixel electrode from the first conductive layer. The signal coupling between the scan lines of the layer, so the invention can greatly improve the aperture ratio of the pixel structure and provide a better display effect.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The method for forming a pixel structure according to the present invention is described in detail in conjunction with the drawings, but the embodiments are not intended to limit the scope of the present invention, and the method flow description is not limited. The order of execution, any process that is recombined by method steps, and the method of achieving equal efficiency are all covered by the present invention. The drawings are for illustrative purposes only and are not drawn to the original dimensions.

Referring to FIG. 3 to FIG. 12, FIG. 3 to FIG. 12 are schematic diagrams showing a method for forming a pixel structure according to a preferred embodiment of the present invention. 3, FIG. 5, FIG. 7, FIG. 9 and FIG. 11 are schematic layout views, and FIG. 4, FIG. 6, FIG. 8, FIG. 10 and FIG. 12 are respectively FIG. 3, FIG. 5, FIG. 7, FIG. A schematic cross-sectional view taken along section line A-A', section line B-B', section line C-C' and section line D-D'. The same elements or parts in the drawings are denoted by the same symbols. In order to clearly show the layout structure of the present invention, the gate insulating layer, the dielectric layer, the first conductive layer, the second conductive layer and the transparent conductive layer of the present embodiment are all shown in a perspective manner, but actually the gate insulating layer The dielectric layer is not limited to a transparent material.

As shown in FIG. 3 and FIG. 4, a substrate 110 is first provided. The substrate 110 may define one or a plurality of pixel regions, and one or a plurality of sub-pixel regions may be further defined in each pixel region. Only one sub-pixel area is shown as a representation in the figure, and in this embodiment, each sub-pixel area on the substrate 110 may have a similar structure. Each pixel area will correspond to a color filter (not shown). With the control of the liquid crystal layer and the backlight, various gray scale brightness of a single color can be presented, and each pixel area may correspond to one or more pixels. Color filters provide richer colors with color filters of different colors.

Thereafter, a patterned first conductive layer is formed on the substrate 110. For example, the first conductive layer is completely deposited first, and then a portion of the first conductive layer is removed to form a patterned first conductive layer. The patterned first conductive layer includes a scan line 112 and a data line segment 114. Taking a pixel array as an example, the step of forming the scan line 112 and the data line segment 114 may include forming a plurality of data line segments 114 and a plurality of scan lines 112. Each of the scan lines 112 may extend laterally across a plurality of pixel regions and sub-pixel regions, and the data line segments 114 may be located on opposite sides of the scan line 112, substantially perpendicular to the scan lines 112, and corresponding to each pixel. The sides of the area. Each of the scan lines 112 may have one or a plurality of gate electrode portions corresponding to the respective pixel regions.

As shown in FIG. 5 and FIG. 6, after that, a gate insulating layer 132 is formed to completely cover the scan line 112 and the data line segment 114. Next, a semiconductor layer such as a polysilicon layer or an amorphous germanium layer is formed on the gate insulating layer 132. Thereafter, a patterned photoresist (not shown) may be formed on the semiconductor layer, partially overlapped on the scan line 112 and the data line segment 114, and the patterned photoresist is used as an etch mask for the anisotropic etching process. Removing the semiconductor layer and the gate insulating layer 132 not covered by the patterned photoresist until a portion of the data line segment 114 and the transparent region of the substrate 110 are exposed to form the channel structure 116, the first isolation structure 117 and the second isolation Structure 115. The light transmissive region corresponds to the position of the subsequently formed pixel electrode. The invention removes the gate insulating layer 132 of the light-transmitting region, and can increase the light transmittance of the light-transmitting region.

As such, the channel structure 116 , the first isolation structure 117 and the second isolation structure 115 each include a semiconductor layer and a gate insulating layer 132 . The channel structure 116 and the first isolation structure 117 are partially overlapped on the scan line 112, and the second isolation structure 115 is partially overlapped on the data line segment 114. Channel structure 116 may correspond to each gate electrode portion of scan line 112. In addition, after the channel structure 116 is formed, a further doping process may be performed on the channel structure 116 to form a source contact region S and a drain contact region D on the channel structure 116.

As shown in FIG. 7 and FIG. 8, then, a second conductive layer is formed on the data line segment 114, the channel structure 116, the first and second isolation structures 117, 115, and a portion of the second conductive layer is removed to form a source. The electrode 119, the drain electrode 120 and the common electrode 118, wherein the common electrode 118 may partially overlap the first and second isolation structures 117, 115.

After removing a portion of the second conductive layer, the source electrode 119 and the drain electrode 120 may directly contact the channel structure 116, for example, respectively contacting the source contact region S and the drain contact region D of the channel structure 116 to form a thin film transistor. The structure. The source electrode 119 can extend longitudinally across the scan line 112, and the source electrode 119 can be in direct contact to electrically connect the data line segments 114 on both sides. That is, the source electrode 119 of the second conductive layer can directly contact the data line segment 114 of the first conductive layer to form a data line for transmitting the data signal. Therefore, the present invention can maintain the low impedance of the data line, but the specific connection mode is not required. Limited to this.

The common electrode 118 is located above the data line segment 114 and the scan line 112 and can be used as a shielding electrode to form a pixel structure of the SAD. The first isolation structure 117 can electrically isolate the common electrode 118 from the scan line 112 , and the second isolation structure 115 can electrically isolate the common electrode 118 from the data line segment 114 . Taking the embodiment as an example, the common electrode 118 may form a mesh electrode structure surrounding the four sides of each sub-pixel region, but is not limited thereto. More specifically, the common electrode 118 of the present embodiment may include a first electrode strip 118a, a second electrode strip 118b, and a third electrode strip 118c. The first electrode strip 118a is parallel and partially overlapped with the scan line 112; the second electrode strip 118b is parallel to the scan line 112, and partially overlaps the scan line 112 and the pixel electrode 128, and the first electrode strip 118a and the second electrode strip 118b respectively The third electrode strip 118c is disposed parallel to the data line segment 114 and partially overlaps the data line segment 114 and the pixel electrode 128. The second conductive layer between the first, second and third electrode strips 118a, 118b, 118c is not etched away, for example, a C-shape can be utilized between the first, second and third electrode strips 118a, 118b, 118c. The second conductive layer is connected, so that the first, second and third electrode strips 118a, 118b, 118c can be connected to each other to form a mesh electrode.

As shown in FIG. 9 and FIG. 10, a dielectric layer 134 may be formed on the channel structure 116, the source electrode 119, the drain electrode 120 and the common electrode 118, and a portion of the dielectric layer 134 and a portion of the gate are removed. The insulating layer 132 forms an opening 122 in each pixel region. The dielectric layer 134 can mainly serve as a protective layer for each component to improve the reliability of the pixel structure. In addition, the dielectric layer 134 can also serve as a dielectric layer for the storage capacitor, and the opening 122 can expose a portion of the drain electrode 120.

As shown in FIG. 11 and FIG. 12, a transparent conductive layer is formed on the dielectric layer 134, and a portion of the transparent conductive layer is removed to form the pixel electrode 128. The pixel electrode 128 is connected to the drain electrode 120 through the opening 122 for aligning with the common electrode of the color filter substrate to control the liquid crystal layer.

In summary, the pixel structure formed by the present invention has the following advantages:

(1) The source electrode of the second conductive layer can directly contact the data line segment of the first conductive layer as the data line for transmitting the data signal, so the invention can not only maintain the low impedance of the data line.

(2) Since the source electrode directly contacts the data line segment and serves as the data line for transmitting the data signal, the connection of the data line does not easily affect the area of the pixel electrode, thereby maintaining the aperture ratio of the pixel structure.

(3) The signal coupling between the common electrode of the second conductive layer and the data line segment of the first conductive layer can be utilized to reduce the chance of generating stray capacitance, so the pixel electrode can be adjacent or even partially overlapped Side data segment.

(4) The signal coupling between the common electrode of the second conductive layer and the scan line of the first conductive layer can be utilized to reduce the chance of generating stray capacitance, so the pixel electrode can be adjacent or even partially overlapped Scan line on the side.

(5) The respective pixel structure or each sub-pixel structure of the present invention can directly form a mesh-like connection structure by using the common electrode, so that not only the aperture ratio can be greatly reduced, but also the reliability and the electrical transmission capability can be simultaneously improved.

(6) Because the capacitance between the common electrode and the pixel electrode of the SAD structure can be separated by only one dielectric layer, and the capacitance between the common electrode of the SUD structure and the pixel electrode is at least two dielectric layers apart, the SAD structure needs The area of the capacitor electrode plate is small.

Accordingly, the present invention can produce the pixel structure of the SAD without using a translucent cover or a halftone mask, which can greatly improve the aperture ratio of the pixel structure and provide a better display effect.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10. . . Lower substrate

12, 112. . . Scanning line

14, 46, 118. . . Common electrode

16, 116. . . Channel structure

18. . . Data line

20, 120. . . Bipolar electrode

22, 24, 26. . . Contact hole

28, 128. . . Pixel electrode

30. . . Connection layer

32, 132. . . Gate insulation

34. . . The protective layer

36. . . Liquid crystal layer

40. . . Upper substrate

42. . . Black matrix

44. . . Color filter

110. . . Substrate

114. . . Data line segment

115. . . Second isolation structure

117. . . First isolation structure

118a. . . First electrode strip

118b. . . Second electrode strip

118c. . . Third electrode strip

119. . . Source electrode

122. . . Opening

134. . . Dielectric layer

S. . . Source contact area

D. . . Bungee contact area

Figure 1 is a top view of a conventional pixel structure.

Figure 2 is a schematic cross-sectional view of Figure 1 taken along section line Z-Z'.

3 to 12 are schematic views showing a method of forming a pixel structure according to a preferred embodiment of the present invention.

112. . . Scanning line

114. . . Data line segment

115. . . Second isolation structure

116. . . Channel structure

118. . . Common electrode

119. . . Source electrode

120. . . Bipolar electrode

122. . . Opening

128. . . Pixel electrode

Claims (11)

A method for forming a pixel structure, comprising: providing a substrate; forming a patterned first conductive layer on the substrate, comprising a scan line and a data line segment; forming a gate insulation on the scan line and the data line segment Forming a semiconductor layer on the gate insulating layer; removing a portion of the semiconductor layer and a portion of the gate insulating layer to form a channel structure, a first isolation structure and a second isolation structure, and exposing a portion of the data line segment, wherein the channel structure and the first isolation structure partially overlap the scan line, and the second isolation structure partially overlaps the data line segment; the data line segment, the channel structure, the first Forming a second conductive layer on the second isolation structure; removing a portion of the second conductive layer to form a common electrode, a source electrode and a drain electrode, wherein the common electrode portion overlaps the first The second isolation structure, the source electrode contacts the data line segment and the channel structure, and the gate electrode contacts the channel structure; the channel structure, the source electrode, the 汲Electrode is formed over the common electrode dielectric layer, exposing a portion of the drain of the source electrode of the dielectric layer; forming a pixel electrode on the dielectric layer, the pixel electrode is electrically connected to the drain electrode. The method of claim 1, wherein the step of forming the scan line and the data line segment comprises forming at least two data line segments on opposite sides of the scan line. The method of claim 2, wherein the step of removing a portion of the semiconductor layer and a portion of the gate insulating layer comprises exposing each of the data line segments. The method of claim 3, wherein the source electrode contacts the data line segments across the scan line and the channel structure. The method of claim 1, wherein the removing the portion of the semiconductor layer and the portion of the gate insulating layer comprises: forming a patterned photoresist on the semiconductor layer, partially overlapping the scan line and And the non-isotropic etching process is performed to remove the semiconductor layer and the gate insulating layer not covered by the patterned photoresist to expose a portion of the data line segment. The method of claim 1, wherein the removing the portion of the semiconductor layer and the portion of the gate insulating layer comprises using the first isolation structure to isolate the scan line from the common electrode formed subsequently. The method of claim 1, wherein the removing the portion of the semiconductor layer and the portion of the gate insulating layer comprises using the second isolation structure to isolate the data line segment from the subsequently formed common electrode. The method of claim 1, wherein the channel structure, the first isolation structure and the second isolation structure each comprise the semiconductor layer and the gate insulating layer. The method of claim 1, wherein the removing the portion of the semiconductor layer and the portion of the gate insulating layer comprises exposing a light transmissive region corresponding to the subsequently formed pixel electrode. The method of claim 1, wherein the common electrode comprises: a first electrode strip parallel to the scan line, and partially overlapping the scan line with the pixel electrode; a second electrode strip, parallel On the scan line, and partially overlapping the scan line and the pixel electrode, the first and second electrode strips are respectively disposed on opposite sides of the scan line; and a third electrode strip parallel to the data line segment And partially overlapping the data line segment and the pixel electrode. The method of claim 10, wherein the removing the portion of the second conductive layer comprises retaining the second conductive layer between the first, the second and third electrode strips to The first, the second and the third electrode strips are connected to each other.