TWI499555B - A discrete graphene nanodisk as the charge storage layer for manufacturing method and memory application - Google Patents

Description

The manufacturing method and application of separate graphene nanodisk charge storage layer Recalling component

The present invention relates to a memory element, and more particularly to a charge storage film using graphene nano dots as a storage medium, and a memory element thereof.

As the semiconductor industry grows, more and more consumer electronics such as smart phones and tablets, or notebooks and PDAs that have been in development for a long time. Moreover, almost all front-end high-tech electronic products must have memory functions, so the development of memory chips has also grown significantly in recent years. Among all memory chips, the most common one is the Random Random Access Memory (DRAM), and the non-volatile flash memory (Flash). With the changes of the times, its production capacity and market generally show a growing trend.

In recent years, non-volatile memory has been widely recognized in the market. The traditional non-volatile flash memory uses a floating gate (FG) as a charge storage layer. The tunneling oxide layer is used as a tunneling layer for the carrier and blocks the carrier from being returned to the germanium substrate due to leakage. In addition, since the conventional non-volatile memory is mainly made of a polysilicon material as a floating gate, although the defect of the polysilicon itself can be provided to provide a trapping center for storing carriers, polycrystalline germanium is used. For a semiconductor material, the charge stored in the polysilicon can move within the floating gate, thus generating a leakage current in the tunnel oxide layer. In the path, all the charge stored in the floating gate is lost, which is a challenge for the characteristics, reliability and tolerance of the component.

Furthermore, since the tunneling oxide layer needs to be read and written multiple times and quickly, it is required to have superior isolation capability, so that when the non-volatile memory is read and written many times, it can still be used. The tolerability and discrete characteristics of the tunneling oxide layer maintain the storage of the charge, thereby avoiding the leakage path of all the charges stored in the floating gate through the tunneling oxide layer being completely lost due to the formation of the leakage path in the tunneling oxide layer. .

However, for the convenience of people's use, thinning and miniaturization of electronic products is a trend in the future. However, as the component size of the memory chip continues to be miniaturized, the tunneling oxide layer tends to be miniaturized, which in turn increases its defect density and leakage current, resulting in degradation of the overall memory device characteristics. That is to say, in order to miniaturize the memory wafer and use a thin tunnel oxide layer, the storage capacity of the memory element is deteriorated, and the reliability problem that comes with it becomes more and more serious.

In view of the shortcomings of the traditional polysilicon floating gate, the common non-volatile memory can be divided into two categories: one is to replace the polysilicon floating gate with a nitride with lower carrier mobility and constitute a semiconductor-oxidation. Non-volatile memory of the material-nitride-oxide-semiconductor (SONOS) structure, and the other type is a non-volatile memory of nanocrystals.

Among them, nanocrystal memory (NC) is recognized as one of the most promising memories of the next generation. Its working principle is to use nanocrystals as the location of electron storage, and multiple nanocrystals. It can be changed into a plurality of electronic storage locations to reach the threshold voltage of the modulation element. It is worth mentioning that because of each nanocrystal The bodies are separated independently, so even if the leakage is caused by the density of defects in the tunnel oxide layer, the degree of leakage is slightly lower than that of the memory element using the floating gate.

The study of nanocrystal memory has been going on for some time, and the nano-crystallites (Si-NCs) and the nano-crystallites (Ge-NCs) were first developed. Later discovered metal nanocrystal memory materials, such as gold (Au), nickel (Ni), platinum (Pt), tungsten (W) and other metal materials, the use of its energy barrier is much higher than the semiconductor material, making it good Write and erase effects. However, the process compatibility of metals is limited by the problem of diffusion after the thermal process, and overall it is still questioned on the production line.

It is an object of the present invention to provide a charge storage film. The charge storage film is applied to a memory device, and the memory device has a substrate. The charge storage film includes at least a tunnel oxide layer, a charge storage layer and a barrier oxide layer. The tunneling oxide layer is on the substrate. The charge storage layer includes a plurality of graphene nano-dots, and the graphene nano-dots are spaced apart on the tunnel oxide layer. The barrier oxide layer is used to cover the charge storage layer.

In an embodiment of the invention, the graphene nanodots are disc-shaped nanodots.

In an embodiment of the invention, the charge storage layer further comprises a plurality of insulating materials disposed between the graphene nano-dots to separate the graphene nano-dots.

In an embodiment of the invention, the insulating material is a compound that forms a carbon of a stable insulator material.

In an embodiment of the invention, both the tunneling oxide layer and the barrier oxide layer are effective insulating oxide layers.

Another object of the present invention is to provide a method of producing a charge storage film comprising at least the following steps. First, a tunneling oxide layer is formed on the substrate, and then at least one graphene layer is formed on the tunneling oxide layer. Subsequently, a metal material layer is formed on the graphene layer, and a thermal annealing process is performed to form the metal material layer to form a plurality of metal nanocrystals. Then, using the metal nanocrystals as a mask to make the graphene layer a charge storage layer, the charge storage layer comprises a plurality of graphene nano-dots, and the graphene nano-dots are spaced apart from the tunnel oxide layer on. Finally, a barrier oxide layer is formed to cover the charge storage layer.

In an embodiment of the invention, wherein said layer of metallic material is selected from any material that forms nanocrystals.

In an embodiment of the invention, the step of using the metal nanocrystals as a mask to make the graphene layer into the graphene nano-dots is performed by an etching process by using an oxygen plasma.

In an embodiment of the invention, the step of using the metal nanocrystals as a mask to make the graphene layer a charge storage layer is performed by using a fluorine plasma or a nitrogen plasma oxygen plasma.

In an embodiment of the invention, the graphene layer that is not masked by the metal nanocrystals is modified into a insulating material by a fluorine plasma or a nitrogen plasma. In one embodiment of the invention, the above fabrication method forms a plurality of graphene layers on the tunnel oxide layer.

It is still another object of the present invention to provide a memory device including at least a substrate, a charge storage film, and a control gate. Where the substrate has A source region, a drain region and a channel region, and the channel region is located between the source region and the drain region. The charge storage film is located between the substrate and the control gate, and includes a tunneling oxide layer, a charge storage layer and a barrier oxide layer. The tunneling oxide layer is located on the channel region. The charge storage layer comprises a plurality of graphene nano-dots, and the graphene nano-dots are spaced apart on the tunneling oxide layer, and the barrier oxide layer is used to cover the charge storage layer.

In an embodiment of the invention, the graphene nanodots are disc-shaped nanodots.

In an embodiment of the invention, the charge storage layer further comprises a plurality of insulating materials disposed between the graphene nano-dots to separate the graphene nano-dots.

Therefore, the advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.

Please refer to FIG. 1. FIG. 1 is a cross-sectional view showing a charge storage film according to a preferred embodiment of the present invention. Although not shown in FIG. 1, the charge storage film 100 provided by the present invention is utilized in a memory device, and the memory device has a substrate. The charge storage film 100 includes a tunneling oxide layer 10, a charge storage layer, and a barrier oxide layer 12. The tunnel oxide layer 10 is disposed on the substrate. The charge storage layer includes a plurality of graphene nano-dots 11a discretely distributed on the tunneling oxide layer 10, that is, the plurality of graphene nano-dots 11a are spaced apart from the tunneling oxide layer 10. A barrier oxide layer 12 is formed over the tunnel oxide layer 10 to cover the charge storage layer. In a preferred embodiment, the barrier oxide layer 12 is used to cover The graphene nano-dots 11a fill the voids between the graphene nano-dots 11a. Preferably, the tunneling oxide layer 10 and the barrier oxide layer 12 are effective insulating oxide layers, preferably both of which are a cerium oxide material. However, the present invention is not intended to be limited thereto.

Further, the above-described charge storage film 100 and a method of manufacturing the memory element therefor will be described later. Please refer to FIGS. 2A to 2H. FIGS. 2A to 2H are cross-sectional views showing the flow of a method for fabricating a memory device according to a preferred embodiment of the present invention.

As shown in FIG. 2A, the tunnel oxide layer 10 is first formed on the substrate 20. Preferably, the step of forming the tunneling oxide layer is performed through a thermal oxidation process. In addition, the substrate 20 is preferably a germanium substrate.

Next, as shown in FIG. 2B, at least one graphene layer 11 is formed on the tunnel oxide layer 10. Further, the above steps are preferably performed using a transfer process.

Please refer to FIGS. 4A to 4C for the first time, and FIGS. 4A to 4C are cross-sectional views showing the flow of forming a graphene layer on the tunneling oxide layer in a preferred embodiment of the present invention. As shown in FIG. 4A, the above transfer process first deposits a graphene layer 11 on a copper foil 30 by a chemical vapor deposition process, and then coats a photoresist 40 on the graphene layer 11, as shown in FIG. 4B. Shown. Subsequently, the copper foil 30 is etched by a wet etching process. At this time, the photoresist 40 and the graphene layer 11 float in the solution, and can be transferred onto the substrate 20 having the tunnel oxide layer 10 which has been prepared in FIG. However, it should be noted that the above step of transferring the graphene layer 11 to the tunneling oxide layer 10 is merely an example, The invention is not intended to be limited to this.

It is to be noted that the present invention is intended to provide a charge storage film having graphene nanodots and a memory device for use thereof. However, since the graphene material has excellent thermal stability, the graphene nanodots cannot be obtained through a thermal process. Therefore, in the present invention, the graphene layer 11 is etched by using the metal nanocrystal as a mask or the portion not shielded by the mask is modified into an insulating material, so that the graphene layer 11 becomes a charge storage layer. The detailed steps will be detailed later.

Referring to FIG. 2C, a layer of metal material 13 is plated on the graphene layer 11 by an evaporation system. Next, as shown in FIG. 2D, a thermal annealing process is performed to form the metal material layer 13 into a plurality of metal material nanocrystals 13a, that is, the graphene layer 11 is provided with a plurality of discrete metal material nanocrystals 13a. Preferably, the metal material layer 13 is preferably gold, copper or tungsten. However, the invention is not limited thereto, and only the material used for the metal material layer 13 can be converted into a nano crystal via a thermal process. The purpose of the invention.

In addition, the process temperature of the above thermal annealing process is preferably between 600 ° C and 800 ° C. Take the gold nanocrystal as an example, please refer to Figure 4 first. Figure 4 shows the relationship between the crystal density of the gold nanocrystal and the thermal annealing process temperature. As shown, the higher the temperature of the thermal annealing process, the higher the amount of heat supplied to the metal material, and the higher the density of the gold nanocrystals formed on the graphene layer 11 at this time. That is, the density of the graphene nano-dots 11a to be formed later can be adjusted by the density of the metal nanocrystals 13a here.

Please refer to both FIG. 2D and FIG. 2E, in the above preferred embodiment. After the plurality of metal nanocrystals 13a are formed, the graphene layer 11 can be etched using the metal nanocrystals 13a as a mask. After the graphene layer 11 is etched, a plurality of graphene nano-dots 11a are formed as shown in FIG. 2E. As described above, the graphene nano-dots 11a are used to store charges, and the etching step is preferably performed using oxygen plasma.

Next, as shown in Fig. 2F, the metal material nanocrystal 13a is removed. It should be noted that the graphene nano-dots 11a formed here are dish-shaped nanocrystals, and may also be referred to as graphene nanodisks.

Referring to FIG. 2G, after the metal material nanocrystal 13a is removed, the barrier oxide layer 12 is further formed on the tunnel oxide layer 10. The barrier oxide layer covers the tunnel oxide layer 10 in a comprehensive manner, that is, it covers the gap between the graphene nano-dots 11a, the graphene nano-dots 11a, and the graphene nano-dots 11a. The tunnel oxide layer 10 is on. So far, the provisioning process of the charge storage film 100 has been completed in its entirety.

Subsequently, as shown in FIG. 2H, a control gate 14 is formed on the barrier oxide layer 12 of the charge storage film 100. In addition, the substrate 20 can form a source region 20a, a drain region 20b and a channel region 20c via an ion implantation process. The channel region 20c is located between the source region 20a and the drain region 20b, and the charge storage film 100 is disposed on the channel region 20c.

However, the present invention is not intended to be limited to the above preferred embodiment. When the metal nanocrystal 13a is used as a photomask, the metal nanocrystal 13a may be shielded by a nitrogen plasma or a fluorine gas plasma. The graphene layer 11 is modified into a plurality of insulating materials. Accordingly, please refer to FIGS. 3A to 3D simultaneously, and FIGS. 3A to 3D are cross-sectional views showing the flow of a method of manufacturing a charge storage film according to another preferred embodiment of the present invention. First, as shown in Figure 3A, After forming a plurality of metal nanocrystals 13a, the metal nanocrystals 13a can be used as a photomask, and the graphene layer 11 can be subjected to nitrogen plasma or fluorine gas plasma. Next, as shown in FIG. 3B, the graphene layer 11 not shielded by the metal nanocrystal 13a is modified into a plurality of insulating materials 11b after being applied with a nitrogen plasma or a fluorine gas plasma. The materials 11b are respectively disposed between the graphene nano-dots 11a to space the graphene nano-dots 11a. Preferably, the insulating material 11b is a compound which can form a carbon of a stable insulator material, preferably a carbon nitride material or a carbon fluoride material.

Then, as shown in Fig. 3C, the metal material nanocrystal 13a is removed. It should be noted that the graphene nano-dots 11a formed here are dish-shaped nanocrystals, and may also be referred to as graphene nanodisks.

Finally, referring to FIG. 3D, after the metal material nanocrystal 13a is removed, the barrier oxide layer 12 is further formed to cover the above-mentioned charge storage layer containing a plurality of graphene nano-dots 11a and a plurality of insulating materials 11b. So far, the charge storage film 100 provided by another preferred embodiment of the present invention has been completely prepared.

Please refer to Figure 5, which shows the graph of the number of graphene layers and their work functions. As described above, the manufacturing method provided by the present invention forms at least one graphene layer 11 on the tunnel oxide layer 10, that is, more than one graphene layer 11 may be formed on the tunnel oxide layer 10 in the above step. . Basically, the use of graphene nano-dots 11a to store charge requires consideration of the work function. Using a single-layer layer of single layer graphene (SLG), that is to say, only a charge storage layer is formed later, although a good electron transfer rate can be obtained, but the work function is small (about 4.2 eV), the potential energy The depth of the well is insufficient. However, when the tunnel oxide layer 10 is provided When there are a plurality of Multi-Layer Graphene layers (MLG), that is, when a plurality of charge storage layers are formed on the tunnel oxide layer 10, the work function is also increased as shown in the figure. Therefore, depending on the requirements of the memory device, after forming the plurality of graphene layers 11 in the tunnel oxide layer 10, the graphene layers 11 can be formed by using the metal nanocrystals 13a as a mask according to the steps described above. Etching or partial modification, thereby obtaining a plurality of charge storage layers comprising a plurality of graphene nanodots 11a. At this time, the graphene nano-dots 11a are present in a vertically stacked manner in addition to the discrete distribution on the tunneling oxide layer 10.

In summary, the present invention provides a charge storage film having graphene nano-dots, a memory element thereof, and a method for fabricating the same, which utilizes the excellent thermal stability of the graphene material, and can effectively overcome the problems in the prior art. The thermal stability of the metal nanocrystals is unsatisfactory, which leads to doubts about the compatibility with subsequent processes, problems such as derivatization and diffusion, difficulty in size control, etc., and the properties of the nanocrystals can be utilized to make the memory The component has excellent charge durability and write/erase speed.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following. Within the scope of the patent application.

100‧‧‧Charge storage membrane

10‧‧‧ Tunneling Oxidation Layer

11‧‧‧graphene layer

11a‧‧‧graphene nano point

11b‧‧‧Insulation materials

12‧‧‧Block oxide layer

13‧‧‧Metal material layer

13a‧‧‧Nano crystals of metallic materials

14‧‧‧Control gate

20‧‧‧Substrate

20a‧‧‧ source area

20b‧‧‧Bungee Area

20c‧‧‧Channel area

30‧‧‧ copper foil

40‧‧‧Light resistance

1 is a cross-sectional view showing a charge storage film according to a preferred embodiment of the present invention; and FIGS. 2A to 2H are diagrams showing a memory element according to a preferred embodiment of the present invention; A cross-sectional view of a flow of a method of manufacturing a part; FIGS. 3A to 3D are cross-sectional views showing a flow of a method of manufacturing a charge storage film according to another preferred embodiment of the present invention; and FIGS. 4A to 4C are views showing a preferred embodiment of the present invention. A schematic cross-sectional view of the flow of the graphene layer on the tunneling oxide layer; Figure 5 shows the relationship between the dot density of the gold nanoparticle and the temperature of the thermal annealing process; and Figure 6 shows the relationship between the number of graphene layers and the work function.

100‧‧‧Charge storage membrane

10‧‧‧ Tunneling Oxidation Layer

11a‧‧‧graphene nano point

12‧‧‧Block oxide layer

14‧‧‧Control gate

20‧‧‧Substrate

20a‧‧‧ source area

20b‧‧‧Bungee Area

20c‧‧‧Channel area

Claims (12)

A charge storage film having a plurality of graphene disk-shaped nano-dots applied to a memory device, wherein the memory device has a substrate, and the charge storage film comprises at least: a tunneling oxide layer on the substrate; a charge storage layer comprising a plurality of graphene disk-shaped nano-dots, wherein the plurality of graphene-shaped nano-dots are spaced apart from the tunneling oxide layer; and a barrier oxide layer covering the charge storage layer. The charge storage film of claim 1, wherein the charge storage layer further comprises a plurality of insulating materials, wherein the plurality of insulating materials are respectively disposed between the plurality of graphene disk-shaped nano-dots to make the plurality of Graphene disc-shaped nano-dots are spaced apart. The charge storage film of claim 2, wherein the plurality of insulating materials are selected from the group consisting of carbon nitride materials and carbon fluoride materials. The charge storage film of claim 1, wherein the tunnel oxide layer and the barrier oxide layer are ruthenium dioxide layers. A method for fabricating a charge storage film having a plurality of graphene disk-shaped nano-dots, which is applied to a memory device, wherein the memory device has a substrate, and the manufacturing method comprises at least the following steps: forming a tunnel oxide layer On the substrate, wherein the tunneling oxide layer is a ceria layer; forming at least one graphene layer on the tunneling oxide layer; forming a metal material layer on the graphene layer; Performing a thermal annealing process to form a plurality of metal nanocrystals in the metal material layer, wherein a temperature of the thermal annealing process is between 600 ° C and 800 ° C; and the plurality of metal material nano-dots are one The photomask forms the graphene layer as a charge storage layer, wherein the charge storage layer comprises a plurality of graphene dished nano-dots, and the plurality of graphene disc-shaped nano-dots are spaced apart from the tunneling oxide layer And forming a barrier oxide layer to cover the charge storage layer, wherein the barrier oxide layer is the ruthenium dioxide layer. The method of manufacturing a charge storage film according to claim 5, wherein the metal material layer is selected from the group consisting of gold, copper, and tungsten. The method for producing a charge storage film according to claim 5, wherein the step of using the plurality of metal nanocrystals as the mask to make the graphene layer into the charge storage layer is through an oxygen The slurry is subjected to an etching process to complete. The method for manufacturing a charge storage film according to claim 5, wherein the step of using the plurality of metal nanocrystals as the mask to make the graphene layer into the charge storage layer is a fluorine-emitting battery Slurry or a nitrogen plasma oxygen plasma is used. The method of manufacturing a charge storage film according to claim 5, wherein the graphene layer not shielded by the mask is modified into an insulating material by the fluorine plasma or the nitrogen plasma. The method for fabricating a charge storage film according to claim 5, further comprising forming a plurality of the graphene layers on the tunnel oxide layer. A memory component having a plurality of graphene disk-shaped nano-dots, to The method comprises: a substrate having a source region, a drain region and a channel region, wherein the channel region is located between the source region and the drain region; a charge storage film is disposed on the substrate, and comprises a tunneling oxide layer disposed on the channel region, wherein the tunneling oxide layer is a cerium oxide layer; a charge storage layer comprising a plurality of graphene disk-shaped nano-dots, and the plurality of graphene disks a nanometer dot is disposed on the tunneling oxide layer; and a barrier oxide layer covering the charge storage layer, wherein the barrier oxide layer is the germanium dioxide layer; and a control gate is located at the charge storage film on. The memory device of claim 11, wherein the charge storage layer further comprises a plurality of insulating materials, wherein the plurality of insulating materials are respectively disposed between the plurality of graphene disk-shaped nano-dots to make the plurality Graphene disc-shaped nano-dots are spaced apart.