TWI497670B - Semiconductor component based on aluminum alloy lead frame and preparation method thereof - Google Patents

Description

Semiconductor component based on aluminum alloy lead frame and preparation method thereof

The present invention generally relates to a lead frame, and more particularly to an aluminum alloy lead frame for use in a power semiconductor component.

Due to the large power consumption of conventional power semiconductor components, it is usually required to have both a small size and a good heat dissipation performance. Most lead frames used in lead frames are made of alloy materials such as metallic copper or iron-nickel. . In some corresponding packaging methods, there are all-molded components (typically as shown in FIG. 1A, TO220F or TO262F, etc., the wafer of the power component 10 and the lead frame for supporting the wafer except for the pins. The portion is completely sealed in the molding body 18), and the partially molded component (such as the TO220 shown in FIG. 1B), the wafer of the power component 20 is completely sealed, but one bottom surface of the lead frame 21 is exposed outside the molding body 28. For heat dissipation). Since the heat dissipation effect of the package of the power component 10 is extremely poor, it tends to be eliminated, and the lead frame 21 of the power component 20 has an exposed bottom surface as a heat dissipation path, but is not suitable for use in a high voltage place, and usually has a lead frame 21 With a large voltage value, direct exposure of the bottom surface of the lead frame 21 as a metal material may adversely affect other components around it or cause a potential personal danger.

Under the currently disclosed technical conditions, it is difficult to apply the aluminum alloy material as a lead frame in actual production. The biggest problem is that aluminum and aluminum alloys are easily oxidized in the air environment. Once the surface of the aluminum alloy has oxides, it is easy to cause the leads of the electrical connection wafer to be difficult to bond on the lead frame, or the molding compound is easily caused. There is delamination between the lead frame and it cannot be sealed. Based on these thorny problems, the present invention proposes to utilize an aluminum alloy lead frame. A method of producing semiconductor components.

Therefore, how to solve the above problems and deficiencies in the above-mentioned applications, that is, the inventors of the present invention and those involved in the industry are eager to study the direction of improvement.

Therefore, in view of the above-mentioned deficiencies, the inventors of the present invention have collected relevant materials, and have evaluated and considered such patents through continuous evaluation and modification through multi-party evaluation and consideration, and through years of experience in the industry.

The main object of the present invention is to provide a method for fabricating a semiconductor device, which provides a lead frame including a plurality of wafer mounting units, and each of the chip mounting units includes at least a pedestal and a plurality of pins disposed near the pedestal. The method includes the steps of: forming a metal layer on each surface of the pedestal and the pin; attaching a wafer to the front surface of the pedestal; and electrically connecting each of the pads disposed on the front surface of the wafer to the corresponding structure by using the interconnect structure At least a portion of the pins are each adjacent to the end of the pedestal; forming a molding body covering at least the front surface of the pedestal, and the molding body encloses the wafer, the interconnect structure, and the end portion, wherein the pedestal back side Some metal layers are exposed to the outside of the plastic body; the metal layer on the back side of the base is removed; and a passivation layer is formed on the back side of the base.

In a preferred embodiment, the method further includes the step of removing the metal layer on the back surface of the pedestal by wet etching, and avoiding the contact of the metal layer covered by the surface of the portion of the lead extending beyond the plastic body in this step. Etch the liquid to prevent it from being etched away.

In a preferred embodiment, the step of removing the metal layer on the back side of the pedestal by wet etching is further included. And, prior to the step, a layer of a resist is applied on the metal layer covered on the surface of the portion of the lead extending beyond the molding body to isolate the portion of the metal layer and the etching liquid.

In a preferred embodiment, after a passivation layer is formed on the back side of the pedestal, a plating layer is formed over the metal layer covered by the surface of the portion of the lead extending beyond the squeezing body.

In a preferred embodiment, a heat sink is further connected to the base, and a metal layer is formed on the surface of the heat sink in the step of forming the metal layer; and in the step of forming the plastic body, the heat sink is not molded. Wrapped inside; and remove the metal layer on the back surface of the pedestal while removing the metal layer on the surface of the heat sink; and form a passivation layer on the surface of the heat sink while forming a passivation layer on the back surface of the pedestal .

In a preferred embodiment, the lead frame is made of an aluminum alloy, and the passivation layer is an aluminum oxide passivation layer formed by an aluminum alloy hard anodization process.

In order to achieve the above object, a method of fabricating a semiconductor device according to the present invention provides a lead frame including a plurality of wafer mounting units, and each of the wafer mounting units includes at least one pedestal and a plurality of pins disposed near the pedestal The method comprises the steps of: forming a metal layer on a surface of the pedestal other than the back surface and a surface of the lead; pasting a wafer on the front surface of the pedestal; and respectively correspondingly forming the solder pads on the front side of the wafer by using the interconnect structure Electrically connecting to at least a portion of each of the pins adjacent to the end of the pedestal; and forming a molding body covering at least the front surface of the pedestal, and the molding body simultaneously covers the wafer, the interconnect structure, and the respective ends Inside, the back side of the pedestal is exposed outside the plastic body; a passivation layer is formed on the back side of the pedestal.

In a preferred embodiment, a cover film is attached to the back side of the pedestal prior to forming the metal layer, and the cover film is removed after the metal layer is formed.

In order to achieve the above object, a semiconductor device of the present invention has a substrate for carrying a wafer, and has a molding body for coating the wafer and the cladding portion, and the method comprises the following steps. : At least the back side of the pedestal is exposed to the molded body, and a passivation layer is formed on the back surface of the pedestal.

In a preferred embodiment, the surface of the pedestal is covered with a metal layer, and the metal layer on the bottom surface of the pedestal is exposed to the plastic body; wherein, before the passivation layer formed on the back surface of the pedestal, The step of removing the metal layer on the back of the pedestal.

In order to achieve the above object, a semiconductor semiconductor device of the present invention includes a wafer mounting unit and each wafer mounting unit includes at least one pedestal and a plurality of pins disposed near the pedestal, and further includes: formed on the back surface of the pedestal a passivation layer, and a metal layer formed on the remaining surface of the pedestal and on the surface of the lead; a wafer affixed to the front surface of the pedestal; and a plurality of solder pads respectively disposed on the front surface of the wafer are electrically connected correspondingly An interconnect structure to an end of at least a portion of the pin adjacent to the pedestal; at least a plastic body overlying the front surface of the pedestal, the blister body also encasing the wafer, the interconnect structure, and the ends, wherein the pedestal The passivation layer on the back side is exposed to the outside of the molded body.

In a preferred embodiment, the wafer is a vertical power component, a back metal layer disposed on the back surface of the wafer is adhered to the pedestal by a conductive adhesive material; and at least one pin is directly connected to the pedestal And a part of the pin connected to the pedestal is covered by the molding body.

In a preferred embodiment, the interconnect structure is a metal sheet or bond wire or a strip of metal conductive strip.

In a preferred embodiment, the susceptor is further connected to a heat sink having a surface covered with a passivation layer.

In a preferred embodiment, the gold formed by the surface of the portion of the lead extending beyond the molded body The genus layer is also plated with another layer of plating.

In a preferred embodiment, the wafer mounting unit is made of an aluminum alloy and the passivation layer comprises aluminum oxide.

In order to achieve the above object, the present invention is a semiconductor device having a susceptor carrying a wafer, and a plurality of pins disposed near the pedestal, wherein the wafer affixed to the front surface of the pedestal forms an electrical connection relationship with the pins. And having a plastic body for covering a part of each pin, and covering the wafer and a part of the base, characterized in that at least the back surface of the base is exposed to the plastic body, and a back pass is formed on the back surface of the base Floor.

These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;

In order to achieve the above objects and effects, the technical means and the structure of the present invention will be described in detail with reference to the preferred embodiments of the present invention.

Referring to FIG. 2A-1, a lead frame 100 of aluminum alloy material is shown, which typically includes a plurality of wafer mounting units 30, and each wafer mounting unit 30 includes at least one square base 31 for carrying wafers. And a plurality of pins 32a-32c disposed near the susceptor 31 or more pins not shown, the pins 32a, 32c are respectively located at two sides of the pin 32b, and the pins 32a, 32c respectively are close to the pedestal The ends 32a-1 and 32c-1 of the inner bonding region 31 are connected, and the pins 32b are directly connected to the susceptor 31, and the pins 32a to 32c each extend outward in a direction away from the susceptor 31. The wafer mounting unit 30 further includes a heat sink 35 with a through hole connected to the base 31. The pins 32a to 32c and the heat sink 35 are respectively located on opposite sides of the base 31, and the second A-2 is shown. Shown is a schematic view of amplifying a wafer mounting unit 30.

Fig. 2B is a schematic vertical cross-sectional view of the wafer mounting unit 30 taken along the broken line A-A shown in Fig. 2A-1. In the second B-2C diagram, a metal layer 33 is formed on the surface of each of the leads 32a to 32c and the susceptor 31 and the heat sink 35, and may be plated, deposited, steamed, sputtered, or the like, and the metal layer 33 is formed. There are many choices of structure and material, but the wettability of the metal layer 33 is relatively good, and it may be a single layer structure composed of a metal, or a multilayer structure (composite layer) in which a plurality of different metals are sequentially formed from the inside to the outside. . For example, the metal layer 33 may be selected from Cu or Ni or the noble metal Ag, Pd, Pt, or the like, or Ni/Pd/Au or Ni/Cu or Ni/Zn/Cu or the like. Then, as shown in FIG. 2D-2E, a wafer 40 is attached to the front surface of each of the pedestals 31. The wafer 40 can be generally a vertical power component, and the operating current flows from the front side to the back side or vice versa. The back metal layer (not labeled) on the back side may be adhered to the front surface of the susceptor 31 by a conductive adhesive material 34, which may be a conductive silver paste or solder paste or the like. In addition to this, the wafer 40 can also be soldered to the front surface of the susceptor 31 by eutectic soldering.

In the wafer mounting unit 30, the pins 32a to 32c which are arranged in parallel in a row are coplanar, but they are connected to the mutually coplanar fins 35 and the pedestals 31 which are respectively connected to each other on the upper and lower two offset planes. In this embodiment, the end portions 32a-1 and 32c-1 have an increased area compared to the respective body portions of the pins 32a, 32c, respectively, so that the pads 40a, 40b disposed on the front surface of the wafer 40 can pass through a strip. The one or more interconnecting structures 41 are electrically connected to the ends 32a-1, 32c-1, respectively. Although the interconnect structure 41 illustrated in the figure is a bonding wire, it can also be metal piece, A strip of metal conductive tape or the like is substituted.

Referring to FIG. 2F, a molding body 38 is formed by using an epoxy resin molding compound, and the molding body 38 is used to cover the wafer 40, the interconnection structure 41, and the cladding portion base 31 and the cladding pins 32a, 32c. Part of, for example, at least covering each end 32a-1, 32c-1, and pin 32b Part of it is covered. The molding body 38 is coated on at least the front surface of the susceptor 31, and at least the outer surface of the susceptor 31 opposite to the front surface thereof is exposed to the molding body 38. FIG. 2G is a schematic view showing the back surface of the susceptor 31. As shown in the 2G-2H diagram, the heat sink 35 needs to be exposed outside the molding body 38 as a heat dissipating member, and the metal layer 33 carried on the back surface of the base 31 is also exposed outside the molding body 38.

Then, as shown in Fig. 2I, the metal layer 33 on the surface of the heat sink 35 and the back surface of the susceptor 31 is etched away by wet etching. The material used for the metal layer 33 is different, and the type of the etching liquid corresponding thereto needs to be adjusted adaptively, and the etching liquid cannot be corrosive to the molding body 38. In one embodiment, at least the entire heat sink 35 and the back surface of the susceptor 31 are immersed in an etchant in an etched trench (not shown), at which time the metal layer 33 and the heat sink on the back side of the pedestal 31. The metal layer 33 of the surface 35 needs to be in sufficient contact with the etching liquid, and the portion of the leads 32a to 32c extending to the outside of the molding body 38 must be away from the etching liquid and strongly avoid contact or immersion into the etching liquid. As a result, when the metal layer 33 on the back surface of the susceptor 31 and the metal layer 33 on the surface of the heat sink 35 are etched, the metal layer 33 on the surface of the portion of each of the leads 32a to 32c extending to the outside of the molded body 38 is retained. It can continue to be used as an oxidation preventing layer and a contact layer in electrical contact with an external circuit.

In view of the protection of the metal-free layer 33, the back surface of the susceptor 31 will be directly exposed outside the molding body 38, and the surface of the heat sink 35 is also exposed to the air because the chemistry of aluminum is extremely active, which will result in their bareness. The surface is rapidly oxidized and a thin and porous thin oxide layer is formed, reducing the reliability of the component. Therefore, it is also necessary to perform cleaning on the back surface of the susceptor 31 and the surface of the heat sink 35 to remove these undesired oxide layers and other contaminants, such as degreasing, ruthenium etching, and pickling neutralization to obtain clean aluminum. Material surface.

Thereafter, as shown in FIG. 2J, a dense and relatively thick passivation layer 39 of alumina can be formed on the back surface of the susceptor 31 and the surface of the heat sink 35, which can be realized by anodized aluminum alloy. This purpose. For example, another electrolytic cell (not shown) containing an electrolyte is provided first. Generally, an acidic electrolyte, an alkaline electrolyte, a non-aqueous electrolyte, etc. are suitable, but the concentration is moderate and the chemical properties are required to ensure electrolysis. The liquid is not corrosive to the plastic body 38, such as a low concentration of sulfuric acid H2SO4 solution and various auxiliary additives. In this step, it is ensured that the entire surface of the heat sink 35 and the back surface of the susceptor 31 are completely immersed in the electrolyte, and the portions of the leads 32a to 32c that extend beyond the molded body 38 are kept away from the electrolyte and cannot be contacted. Soaking in the electrolyte soaking to prevent the metal layer 33 covered by the surface of this portion from being accidentally damaged by contact with the electrolyte. A typical anodic oxidation method, such as under dc conditions, uses the susceptor 31 and the heat sink 35 as an anode, and lead or platinum as a cathode. In the anodizing treatment of the aluminum alloy, it is equivalent to electrolysis of water, and hydrogen is evolved on the cathode. Oxygen is produced on the anode. On the anode, the susceptor 31 and the heat sink 35 of the aluminum alloy lose electrons and are combined with oxygen, and a passivation layer 39 (FIG. 2J) which is an oxide film of aluminum on the back surface of the susceptor 31 and the surface of the heat sink 35 is obtained. Under some specific oxidation conditions, the oxide film is a two-layer structure comprising a relatively thin but dense non-porous inner layer and a thick and porous outer layer, wherein the inner layer is Al2O3 and the outer layer is an oxide film wall that reacts with water. At the same time, the porous layer is formed by chemically binding adsorption of the electrolytic anion.

Then, the steps of Trim/Form are performed, and the unlabeled ribs in some of the figures are cut, the pins 32a to 32b are cut out from the lead frame 100, and the portions of the leads 32a to 32b are extended. The semiconductor element 300 shown in FIG. 2L is formed by stamping into various pre-designed shapes, and the hatched layer represents the passivation layer 39. Alternatively, when the wafer 40 is a MOSFET, the pad 40b is the gate terminal, the pad 40a is the source terminal, and the back metal layer on the back side of the wafer 40 is At the drain end, if the wafer 40 is an IGBT, the pads 40a, 40b and the back metal layer are respectively an emitter, a gate and a collector, and it is emphasized that the shape and position of the pads 40a, 40b are illustrated in the figure. It is not intended to limit the invention. As a result, in the high-voltage electronic power component, the pedestal 31 electrically connected to the drain terminal (or the collector) tends to have a large voltage drop, if the back surface of the susceptor 31 and the surface of the heat sink 35 are directly exposed. There will be potential safety hazards, and it will also interfere with other electronic components in the vicinity, and the passivation layer 39 is formed to insulate and suppress high voltage. Another great advantage is that the passivation layer 39 is not a thermally insulating material. When the pedestal 31 and the heat sink 35 serve as a heat dissipation path for the wafer 40, the passivation layer 39 does not affect the dissipation of heat.

In some embodiments, as shown in FIG. 2K, a plating layer 36 may be further plated on the metal layer 33 covered by the surface of the portion of the lead 32a to 32c that extends beyond the molding body 38. For example, when the metal layer 33 is not a noble metal layer or the outermost layer does not contain a noble metal layer, such as Ni/Cu or Ni/Zn/Cu, etc., the plating layer 36 may be additionally formed, typically a relatively inexpensive tin Sn. The plating layer is the most cost-effective because it does not use precious metals. The timing of forming the plating layer 36 may be selected after the passivation layer 39 is obtained. One convenience is that the passivation layer 39 of the aluminum oxide does not stick to the solder, and the solder paste is adsorbed on the back surface of the susceptor 31 or the heat sink 35. The trouble of the surface. On the other hand, if the metal layer 33 itself is a precious metal layer, or when the metal layer 33 is a composite layer structure, the outermost layer is a noble metal layer, it is not necessary to additionally form the plating layer 36.

In some embodiments, in consideration of the step of etching the metal layer 33 on the back surface of the susceptor 31 and the surface of the heat sink 35, it is impossible to completely prevent the portions of the pins 32a to 32c extending beyond the molding body 38 from being partially or entirely immersed into In the etching solution, that is, the metal layer 33 covered by the surface thereof may contact the etching liquid and may be corroded, so it is necessary to extend to the plastic body at the pins 32a to 32c. A layer of resist 37 (as in Figure 3a) is formed over the metal layer 33 overlying the surface of the portion other than 38 to provide protection from the metal layer 33 at these locations and the etchant. Generally, as long as the etching solution is corrosive (sensitive) to the metal layer 33 and not corrosive (insensitive) to the resist layer 37, the resist layer 37 can serve as an etch barrier (corresponding to a mask layer). For example, the metal layer 33 is a Ni/Cu composite layer, and the resist layer 37 is a noble metal layer. One advantage is that in the subsequent steps, whether or not the resist layer 37 is peeled off may be selected according to actual needs. For example, the resist layer 37 of the noble metal material disclosed in the foregoing may be retained without being peeled off. As shown in FIG. 3B, the metal layer 33 on the back surface of the susceptor 31 and the surface of the heat sink 35 is etched away, even if the portions of the leads 32a to 32c extending beyond the molded body 38 are entirely or partially immersed in the etch. In the liquid, the metal layer 33 on the surface thereof is not etched away by the isolation and corrosion resistance of the resist layer 37, and then the passivation layer 39 is formed as shown in Fig. 3C.

The above description is based on the typical TO220 series lead frame as an example to clarify the inventive spirit of the present application, but the reader needs to be explicitly noted that this does not mean that the present application is limited only to the package type.

In the embodiment as shown in FIG. 4A, the wafer mounting unit 30' does not intentionally provide an additional heat sink, and a plurality of pins 32'a are disposed in the vicinity of the pedestal 31', and these pins 32'a surround the base. The periphery of the seat 31' extends outwardly, and each of the pins 32'a includes an end portion 32'a-1 as a bonding portion adjacent to the base 31'. 4B is a schematic vertical sectional view of the wafer mounting unit 30'. In the present embodiment, a cover film 50 is attached to the back surface of each of the pedestals 31', and then, as shown in FIG. 4C, at the pedestal 31'. In addition to the back surface covered by the cover film 50, the remaining surface and the surface of the lead 32'a are plated with a metal layer 33, after which the cover film 50 is removed, but it is also possible to form the subsequent molded body 38. The cover film 50 is removed, as shown in FIG. 4D, thus securing the base 31' The metal layer 33 is not covered on the back side. Then, as shown in FIG. 4E, the wafer 40' is pasted on the front side of the pedestal 31' by the adhesive material 34, and a plurality of pads (not shown) on the front side of the wafer 40' are respectively corresponding to each other by the interconnection structure 41. Connected to respective ends 32'a-1 of the plurality of pins 32'a. And forming a molding body 38' covering at least the front surface of the susceptor 31 for covering the wafer 40' and the interconnect structure 41, and covering a portion of the pedestal 31' and covering a portion of each of the pins 32'a For example, at least the end portion 32'a-1 is covered. Wherein, the molding body 38' may be coated on the side wall and the front surface of the base 31', and at least the outer surface of the base 31' opposite to the front surface thereof may be exposed to the molding body 38'. Although a thin oxide layer is quickly formed on the back surface of the pedestal 31' after the cover film 50 is removed, as long as the passivation layer 39 is removed before the passivation layer 39 is formed, the method has been described in the foregoing, and will not be described again. Then, the passivation layer 39 can be obtained by anodization on the back surface of the susceptor 31' to obtain the semiconductor element 300'.

In some embodiments, the type of the wafer 40' may be various, such as the back side of the wafer 40' does not need to be provided with a back metal layer, or the back metal layer is provided but it is possible to choose whether to electrically connect it with the pedestal 31'. At this time, the adhesive material 34 may also be selected from conductive or non-conductive materials. In some embodiments, the lead 32'a is stamped into a stepped Z-shaped structure including an end 32'a-1 as a high mesa and a contact end 32'a-3 as a low mesa, both passing The connecting portion 32'a-2 is connected, wherein the base 31' and the contact end 32'a-3 are respectively located in two staggered planes so that there is a height between the back surface of the base 31' and the contact end 32'a-3 Poor, so that when the contact end 32'a-3 is soldered to the pad on the PCB, the back side of the pedestal 31' does not abut the PCB, facilitating dissipation of heat on the back side of the pedestal 31'.

In some optional embodiments, in the lead frame of the aluminum alloy material, the percentage of the quality of each material is approximately: the content of 矽Si is 0.20%-0.6%, and the content of iron Fe is 0.3%-0.8%. The content of copper Cu is 0.1%~0.3%, the content of manganese Mn is 0.1%~1%, the content of magnesium Mg is 0.5%~5%, the content of chromium Cr is 0.1%~0.5%, and the content of zinc Zn is 0.1. %~0.4%, the content of titanium Ti is 0.05%~0.3%, and other materials are metal aluminum Al and very small amount of impurities (the content ratio disclosed herein is only an example and does not constitute a limitation).

In addition, in the step of forming the passivation layer 39, the aluminum alloy having a high niobium content is liable to cause segregation of the crystal orientation of the niobium, resulting in difficulty in film formation and uniformity in thickness uniformity of the film, so that the 矽Si element is in the entire aluminum alloy. The content should be suitable, for example, less than 10% or even less than 1.00%, so that the passivation layer 39 is more easily formed and its thickness uniformity is improved.

Since aluminum alloy is a low-cost raw material, its hardness and flexibility are suitable for the process of cutting, bending, forming, etc. of the lead frame, so it is suitable for mass production, and its weight is much lower than that of metallic copper or iron. Nickel material, which brings great convenience to actual production, which is a great advantage brought by this application.

Through the above detailed description, it can fully demonstrate that the object and effect of the present invention are both progressive in implementation, highly industrially usable, and are new inventions not previously seen on the market, and fully comply with the invention patent requirements. , 提出 apply in accordance with the law. The above is only the preferred embodiment of the invention, and is not intended to limit the scope of the invention. All changes and modifications made in accordance with the scope of the invention shall fall within the scope covered by the patent of the invention. I would like to ask your review committee to give a clear explanation and pray for it.

10‧‧‧Power components

18‧‧‧Broken body

20‧‧‧Power components

21‧‧‧ lead frame

100‧‧‧ lead frame

30, 30'‧‧‧ wafer mounting unit

300, 300'‧‧‧ semiconductor components

31, 31'‧‧‧ Pedestal

32a, 32’a, 32b, 32c‧‧‧ pins

Ends 32a-1, 32’a-1, 32c-1‧‧

32’a-3‧‧‧Contact

33‧‧‧metal layer

34‧‧‧Adhesive materials

35‧‧‧ Heat sink

37‧‧‧resist layer

38, 38’‧‧‧ Plastic enclosure

39‧‧‧ Passivation layer

40, 40’‧‧‧ wafer

40a, 40b‧‧‧ pads

41‧‧‧Interconnect structure

50‧‧‧ Cover film

1A and 1B are schematic diagrams of a power semiconductor device package according to a prior art; 2A-1, 2A-2 to 2L are schematic views showing a process of preparing a semiconductor device according to a preferred embodiment of the present invention; 3A to 3C are views showing an embodiment of a resist layer according to a preferred embodiment of the present invention; and Figs. 4A to 4E are views showing an embodiment of a semiconductor device according to another preferred embodiment of the present invention.

300‧‧‧Semiconductor components

31‧‧‧ Pedestal

32a, 32b, 32c‧‧‧ pins

35‧‧‧ Heat sink

38‧‧‧plastic body

39‧‧‧ Passivation layer

Claims (17)

A method of fabricating a semiconductor device, comprising: a lead frame comprising a plurality of wafer mounting units, and wherein the chip mounting units comprise at least a pedestal and a plurality of pins disposed adjacent to the pedestal, including: Forming a metal layer uniformly on the surface of each of the pins; attaching a wafer to the front surface of the base; and electrically connecting the solder pads disposed on the front surface of the wafer to at least correspondingly by using an interconnection structure a portion of each of the pins proximate the end of the pedestal; forming a molding overlying the front surface of the pedestal, and encapsulating the wafer, the interconnect structure, and the ends, wherein The metal layer on the back side of the pedestal is exposed to the outside of the molding body; the metal layer on the back side of the pedestal is removed; and a passivation layer is formed on the back surface of the pedestal. The method for fabricating a semiconductor device according to claim 1, further comprising the step of removing the metal layer on the back surface of the pedestal by wet etching, and avoiding extending the pins to the squeezing body in the step The metal layer covered by the surface of the outer portion contacts the etching liquid to prevent it from being etched away. The method for fabricating a semiconductor device according to claim 1, further comprising the step of removing the metal layer on the back surface of the pedestal by wet etching, and before the step, extending the pins to the The metal layer covered on the surface of the portion other than the molded body is plated with a resist layer for isolating part of the metal layer and the etching liquid. A method of fabricating a semiconductor device according to claim 1, wherein the susceptor After forming a passivation layer on the back side, a plating layer is formed on the metal layer covered by the surface of the portion of the pin extending beyond the molding body. The method for fabricating a semiconductor device according to claim 1, wherein a heat sink is further connected to the susceptor, and a metal layer is formed on the surface of the heat sink in the step of forming the metal layer; In the step of molding the body, the heat sink is not covered by the molding body; the metal layer on the surface of the heat sink is also removed together while removing the metal layer on the back surface of the base; The passivation layer is formed on the back side of the pedestal while a passivation layer is formed on the surface of the heat sink. The method for preparing a semiconductor device according to claim 1, wherein the lead frame is made of an aluminum alloy. The method of preparing a semiconductor device according to claim 6, wherein the passivation layer is an aluminum oxide passivation layer formed by an aluminum alloy hard anodization process. A method of fabricating a semiconductor device, comprising: a lead frame including a plurality of wafer mounting units, and each of the chip mounting units includes at least a pedestal and a plurality of pins disposed adjacent to the pedestal, including: Forming a metal layer on the remaining surface except the back surface and the surface of the pins; bonding a wafer to the front surface of the pedestal; and electrically connecting the pads provided on the front surface of the wafer to each other by an interconnection structure And at least a portion of the pins are respectively adjacent to the end of the pedestal; forming a molding body covering at least the front surface of the pedestal, and the molding body simultaneously covers the wafer, the interconnection structure and the end portions, Wherein the back of the base is exposed outside the molded body; A passivation layer is formed on the back side of the susceptor. A method of fabricating a semiconductor device having a susceptor carrying a wafer and having a molding body for coating the wafer and the cladding portion pedestal, comprising the steps of: exposing at least the back surface of the susceptor The body is molded and a passivation layer is formed on the back side of the base. The method for fabricating a semiconductor device according to claim 9, wherein the surface of the pedestal is covered with a metal layer, and the metal layer provided on the bottom surface of the pedestal is exposed to the plastic body, wherein Before the back side of the seat forms the passivation layer, the step of removing the metal layer on the back side of the base is further included. A semiconductor device comprising a wafer mounting unit and each of the wafer mounting units includes at least a pedestal and a plurality of pins disposed adjacent the pedestal, including: a passivation layer formed on a back surface of the pedestal, and formed on a metal layer on the remaining surface of the pedestal and the surface of the pins; a wafer affixed to the front surface of the pedestal; and a plurality of solder pads respectively disposed on the front surface of the wafer are electrically connected to at least a portion of the pads An interconnect structure of the pin proximate the end of the pedestal; and a molding overlying the front surface of the pedestal, the embossing body also wrapping the wafer, the interconnect structure, and the ends Wherein the passivation layer carried on the back side of the pedestal is exposed outside the molding body. The semiconductor device of claim 11, further comprising: the wafer being a vertical power component, a back metal layer disposed on the back surface of the wafer being adhered to the pedestal by a conductive adhesive material; and at least one lead The foot is directly attached to the base, and a portion of the pin attached to the base is covered by the molded body. The semiconductor device of claim 11, wherein the interconnect structure is a metal piece or a bonding wire or a strip-shaped metal conductive tape. The semiconductor device of claim 11, wherein the susceptor is further connected to a heat sink having a surface covered with a passivation layer. The semiconductor device according to claim 11, wherein the metal layer formed by the surface of the portion of the lead extending beyond the molded body is further plated with another plating layer. The semiconductor device of claim 11, wherein the wafer mounting unit is made of an aluminum alloy, and the passivation layer comprises aluminum oxide. A semiconductor component having a susceptor carrying a wafer, and a plurality of pins disposed near the pedestal, the wafer affixed to the front surface of the pedestal is electrically connected to the leads, and has a plastic package And covering a portion of the pins, and coating the wafer and a portion of the pedestal, at least exposing a back surface of the pedestal to the molding body, and forming a passivation layer on a back surface of the pedestal.