TWI495975B - Voltage regulator - Google Patents

Description

Voltage regulator

The present invention relates to a voltage regulator in which an output terminal is connected to a backup battery.

A circuit as shown in FIG. 11 is known as a voltage regulator in which the output terminal is connected to the backup battery 112 (see, for example, Patent Document 1).

The power supply voltage is applied between the VDD terminal 121 and the VSS terminal 123 terminal. The output terminal 122 is connected to the backup battery 112, and even if the power supply voltage between the VDD terminal 121 and the VSS terminal 123 forms zero, the voltage 113 (for example, RAM) of the output terminal 122 is continuously supplied with a voltage.

When the power supply voltage is supplied between the VDD terminal 121 and the VSS terminal 123, if the voltage between the terminals is VBAT1 and the voltage of the backup battery is VBAT2, VBAT1>VBAT2 is generally used. When the power supply voltage is supplied between the VDD terminal 121 and the VSS terminal 123, the Vref circuit 101 outputs a certain voltage (Vref), and the error amplifier 102 amplifies the resistor 107 (resistance value R1) and the resistor 108 (resistance value R2). The voltage of the voltage (VOUT) of the output terminal 122 (R2/(R1+R2)×VOUT) and the voltage difference of Vref are divided to control the gate of the Pch transistor 103, thereby outputting a certain voltage to the output terminal. 122.

The comparator 1105 is connected to the + input terminal by dividing the voltage between the terminals of the VDD terminal 121 and the VSS terminal 123 by the resistor 1101 and the resistor 1102, and dividing the output terminal 122 and the VSS terminal 123 at the resistor 1103 and the resistor 1104. The voltage after the inter-terminal voltage is connected to the -input terminal to compare the terminal voltages of the VDD terminal 121 and the output terminal 122. When the power supply voltage is supplied between the VDD terminal 121 and the VSS terminal 123, since the voltage divided by the resistor 1101 and the resistor 1102 is higher than the voltage divided by the resistor 1103 and the resistor 1104, the comparator 1105 is used. The output is "H", the Pch transistor 105 is in an ON state, and the Pch transistor 106 is in an OFF state. The substrate (NWELL) potential of the Pch transistor 103 is a potential at which the VDD terminal 121 is formed by the Pch transistor 105.

On the other hand, when the voltage between the terminals of the VDD terminal 121 and the VSS terminal 123 is lower than the voltage between the terminals of the output terminal 122 and the VSS terminal 123, the output of the comparator 1105 becomes "L", and the Pch transistor 106 is turned on. The Pch transistor 105 is in an OFF state, and the substrate (NWELL) potential of the Pch transistor is a potential at which the output terminal 122 is formed by the Pch transistor 106.

In other words, by switching the potential of the substrate (NWELL) of the Pch transistor 103 to the side where the potential of the VDD terminal 121 side or the output terminal 122 side is high, even if the voltage of the VDD terminal 121 is lower than the voltage of the output terminal 122, it is still possible. The current is prevented from flowing from the output terminal 122 to the VDD terminal 121 via the parasitic diode between the substrates of the Pch transistor 103.

[Advanced technical literature] [Patent Literature]

[Patent Document 1] Special Report 2001-51735

However, in the conventional voltage regulator, when the potential on the VDD terminal 121 side is zero, the current of the backup battery flows through the resistors 1103 and 1104, so that the problem of the operation cannot be backed up for a long time.

Further, when the potential on the VDD terminal 121 side is zero, the Pch transistor 103 cannot be turned off, and the reverse current flows.

Accordingly, an object of the present invention is to solve the conventional problem and to provide a method in which when the potential on the VDD terminal 121 side is zero, the consumption current of the backup battery is small, and the Pch transistor 103 is turned off, and the reverse current can be surely prevented. The voltage regulator is for the purpose.

The present invention is a circuit configuration in which a voltage dividing resistor is not used in a comparison circuit between the voltage of the VDD terminal 121 of the voltage regulator and the voltage of the output terminal 122, thereby reducing the current flowing to the voltage dividing resistor, thereby solving the above problems.

According to the voltage regulator of the present invention as described above, it is possible to reduce the current consumption and prevent the backflow from the output terminal 122 to the VDD terminal 121 regardless of the magnitude of the voltage of the VDD terminal 121.

The form for carrying out the invention will be described with reference to the drawings.

[Example 1]

Fig. 1 is a circuit diagram showing a voltage regulator of a first embodiment of the present invention. The voltage regulator of the present invention is a Vref circuit 101, an error amplifier 102, a comparison circuit 130, a resistor 107, a resistor 108, a Pch transistor 103, a Pch transistor 104, a Pch transistor 105, a Pch transistor 106, and an Nch transistor 109. The VDD terminal 121, the VSS terminal 123, and the output terminal 122 are formed. The difference from FIG. 11 is that the comparator 1105 and the resistors 1101, 1102, 1103, and 1104 are removed, and the Pch transistors 105 and 106 and the added Pch transistor 104 are controlled by the comparison circuit 130.

Fig. 2 is a view showing a comparison circuit of the present invention.

The comparison circuit 130 is a constant current circuit 203, a constant current circuit 204, a Pch transistor 201, a Pch transistor 202, an inverter 205, an inverter 206, an inverter 208, and a level shifter 207. Composition.

The connection of the voltage regulator of the present invention is explained. The output of the Vref circuit is an inverting input terminal that is connected to the error amplifier 102. The non-inverting input terminal of the error amplifier 102 is connected to the connection point of the resistor 107 and the resistor 108, and the output is connected to the gate of the Pch transistor 103 and the source of the Pch transistor 104. The source of the Pch transistor 103 is connected to the VDD terminal 121 and the drain of the Pch transistor 105, the drain is connected to the output terminal 122 and the drain of the Pch transistor 106, and the back gate is connected to the Pch The source of the crystal 105 and the source of the Pch transistor 106. The gate of the Pch transistor 105 is connected to the node 111, and the back gate is connected to the source of the Pch transistor 105. The gate of Pch transistor 106 is connected to node 110 and the back gate is connected to the source of Pch transistor 106. The drain of Pch transistor 104 is connected to output terminal 122, the gate is connected to node 110, and the back gate is connected to the output of error amplifier 102. The resistor 107 is connected to the output terminal 122 on one side and to the resistor 108 on the opposite side. The Nch transistor 109 has a gate connected to the node 110, a drain connected to the resistor 108, and a source connected to the VSS terminal 123. The comparison circuit 130 is connected to the output terminal 122, the VDD terminal 121, the VSS terminal 123, the node 110, and the node 111. The output terminal 122 is a backup battery 112 and a load 113 are connected in parallel.

Next, the connection of the comparison circuit 130 will be described. The gate of the Pch transistor 201 is connected to the gate of the Pch transistor 202, the drain of the Pch transistor 201, and the constant current circuit 203. The source is connected to the VDD terminal 121, and the back gate is connected to VDD. Terminal 121. The drain of Pch transistor 202 is connected to inverter 205 and constant current circuit 204, the source is connected to output terminal 122, and the back gate is connected to output terminal 122. The output of the inverter 205 is connected to an inverter 206 which is connected as a power source to the output terminal 122. The output of inverter 206 is coupled to level shifter 207 and CONT terminal 223, which is coupled to output terminal 122 as a power source. The output of the level shifter 207 is connected to an inverter 207 which is connected as a power source to the VDD terminal 121. The output of inverter 208 is connected to CONTX terminal 222, which is connected as power supply to VDD terminal 121. The CONT terminal 223 is a junction to the node 111 of FIG. 1, and the CONTX terminal 222 is a junction to the node 110 of FIG.

Next, the operation of the voltage regulator according to the present invention will be described. When the potential of the terminal of the VDD terminal 121 is higher than the potential of the terminal of the output terminal 122, since the voltage between the gate and the source of the Pch transistor 201 is higher than the voltage between the gate and the source of the Pch transistor 202, the Pch is charged. The potential of the drain of the crystal 202 is at the "L" level (the potential of the VSS terminal 123). With the inverters 205 and 206 for waveform shaping, the voltage of the CONT terminal 223 to which the output of the inverter 206 is connected forms an "L" level. The level shifter 207 converts the potential level of the output terminal 122 to the potential level of the VDD terminal 121. Inverter 208 inverts the output voltage of level shifter 207. When the voltage of the CONT terminal 223 is at the "L" level, the CONTX terminal 222 of the output of the inverter 208 is at the potential level of the VDD terminal 121. At this time, the potential of the substrate (NWELL) of the Pch transistor 103 of FIG. 1 is in the ON state of the Pch transistor 105, and the Pch transistor 106 is in the OFF state, so that it becomes the potential of the VDD terminal 121. That is, the potential higher of the potential of the VDD terminal 121 and the potential of the output terminal 122 becomes the substrate (NWEEL) potential of the Pch transistor 103. At this time, the Pch transistor 104 is in an OFF state. Generally, when the power source is connected to the VDD terminal 121, the potential of the VDD terminal 121 > the potential of the output terminal 122.

On the other hand, when the power source is not connected to the VDD terminal 121, since the battery 112 for backup is connected to the output terminal 122, the potential of the VDD terminal 121 is <the potential of the output terminal 122. At this time, since the gate-source voltage of the Pch transistor 201 is lower than the gate-source voltage of the Pch transistor 202, the potential of the drain of the Pch transistor 202 becomes the "H" level ( The potential of the output terminal 122). With the inverters 205 and 206 for waveform shaping, the voltage of the CONT terminal 223 of the output of the inverter 206 is at the "H" level (the potential of the output terminal 122). The level shifter 207 converts the potential level of the output terminal 122 to the potential level of the VDD terminal 121. Inverter 208 inverts the output voltage of level shifter 207. When the voltage of the CONT terminal 223 is at the "H" level (the potential of the output terminal 122), the voltage of the CONTX terminal 222 of the output of the inverter 208 becomes the "L" level (the potential level of the VSS terminal 123). At this time, the potential of the substrate (NWELL) of the Pch transistor 103 of FIG. 1 is in the ON state of the Pch transistor 106, and the Pch transistor 105 is in the OFF state, so that it becomes the potential of the output terminal 122. That is, the potential of the potential of the VDD terminal 121 and the potential of the output terminal 122 becomes the substrate (NWEEL) potential of the Pch transistor 103. At this time, the Pch transistor 104 is in an ON state, and the Pch transistor 103 is turned OFF by forming the gate of the Pch transistor 103 at the same potential as the output terminal 122. As a result, even if the potential of the VDD terminal 121 < the potential of the output terminal 122, current can be prevented from flowing from the output terminal 122 to the VDD terminal 121 by the Pch transistor 103.

Next, the error amplifier 102 used in Fig. 1 will be explained. The general error amplifier is constructed as shown in FIG. The constant current circuit 705, the Nch transistors 701 and 702, and the Pch transistors 703 and 704 are formed. The INP 721 is a + input terminal, the INM 722 is an input terminal, and the EOUT 723 is an output. 8 is a cross-sectional view showing the Pch transistor 704. Among the NWELLs on the P substrate, there are P-type source and drain regions. The P substrate is a VSS terminal 123 that is connected to a low potential. And NWELL is connected to the source (VDD terminal 121).

When the general error amplifier of FIG. 7 is used, when the potential of the output terminal 122 is higher than the potential of the VDD terminal 121, if the Pch transistor 104 is in the ON state, the output 723 of the error amplifier 102 is formed to be connected to the output terminal. 122. At this time, in the general error amplifier circuit of FIG. 7, the drain of the transistor 704 is used as the emitter, the source is the base, and the PNP transistor having the substrate as the collector is in the ON state, via the Pch transistor 104. The backup battery 112 will be discharged. In order to avoid this phenomenon, it is preferable to use the configuration of Fig. 9 as an error amplifier circuit.

The third embodiment of the error amplifier circuit 102 of FIG. 9 is to newly add a Pch transistor 801 between the output 723 of the error amplifier and the Pch transistor 704. The Pch transistor 801 is an output 723 that connects the source and NWELL to the error amplifier, and connects the drain to the drain of the Pch transistor 704. The gate is controlled in accordance with the signal (CONT signal) of the node 111 of FIG. FIG. 10 is a cross-sectional view showing the Pch transistors 704 and 801. In this case, when the potential of the output terminal 122 is higher than the potential of the VDD terminal 121, the output 723 of the error amplifier 102 is connected to the output terminal 122 while the Pch transistor 104 is in an ON state, but the signal of the node 111 is Since the potential is the same as that of the output terminal 122, the Pch transistor 801 is in an OFF state, and no current flows from the drain of the Pch transistor 801 to the drain of the Pch transistor 704.

Further, unlike FIG. 7, the Nch transistor 802 is inserted between the differential input circuit composed of the Nch transistors 701 and 702 and the constant current circuit 705 on the source side. The drain of Nch transistor 802 is connected to the source of Nch transistors 701 and 702, the source is connected to constant current circuit 705, and the gate is a signal (CONTX signal) that is connected to node 110 of FIG. controlled. When the potential of the output terminal 122 is formed higher than the potential of the VDD terminal 121, the Pch transistor 104 is in an ON state, the output 723 of the error amplifier 102 is connected to the output terminal 122, and the Nch transistor 702 is in an ON state. Further, the output terminal 122 and the source of the Nch transistors 701 and 702 are electrically connected to each other. However, when the Nch transistor 802 is turned off, the current path of the constant current circuit 705 is blocked. In this way, current can be prevented from flowing from the output terminal 122 through the Nch transistor 702 to the VSS terminal 123.

In the description of FIG. 9, the Nch transistor 802 is inserted between the source of the Nch transistors 701 and 702 and the constant current circuit 705, but it is apparent that even if the constant current circuit 705 and the VSS terminal 123 are inserted, the same is true. effect. Further, the Pch transistor 801 is inserted between the output 723 of the error amplifier 102 and the Pch transistor 704, but the same effect is obtained even if it is inserted between the VDD terminal 121 and the Pch transistor 704.

FIG. 9 is an example of an error amplifier as a one-stage amplifier circuit, but the error amplifier circuit may be a multi-stage amplifier circuit of two or more stages. In this case, as long as the Pch transistor 801 having the function for blocking the current path is inserted in the output of the error amplifier and the VDD side as shown in FIG. 9, the output of the error amplifier and the VSS side are inserted to block the current path. The function of the Nch transistor 802 can be.

As described above, when compared with the conventional voltage regulator of FIG. 11, the resistor 1101, the resistor 1102, the resistor 1103, and the resistor 1104 for comparing the potential of the VDD terminal 121 with the potential of the output terminal 122 are not present, so that the reduction can be reduced. The consumption current of this part. For example, if the voltage of the backup battery 112 is set to 3 V and the sum of the resistor 1103 and the resistor 1104 is assumed to be 3 Meg Ω, a current of 1 μA at the resistor 1103 and the resistor 1104 is consumed from the backup battery 112. However, the voltage regulator of Figure 1 is equivalent to the resistor, and there is no such consumption. The consumption current of the comparator 1105 of FIG. 11 is equal to the consumption current of the comparison circuit 130 of FIG. 2, 0.5 μA. At this time, the voltage regulator in FIG. 11 consumes 1.5 μA from the backup battery 112. In contrast, the voltage regulator in FIG. 1 consumes only 1/3 of 0.5 μA, which can greatly extend the operation time of the backup battery 112. .

[Embodiment 2]

Fig. 3 is a view showing a second embodiment of the comparison circuit 130 of the voltage regulator of the present invention shown in Fig. 1. The comparison circuit 130 of the second embodiment is a constant current circuit 303, a constant current circuit 304, a Pch transistor 201, a Pch transistor 301, a Pch transistor 302, a Pch transistor 305, an inverter 205, an inverter 206, The inverter 208 and the level shifter 207 are formed. The difference from FIG. 2 is that the Pch transistor 202 is composed of two transistors, a Pch transistor 301, and a Pch transistor 302, and a Pch transistor 305 for realizing a hysteresis function is added. Further, the constant current circuit 203 and the constant current circuit 204 are specifically displayed by an N-channel ‧ depletion MOS transistor that connects the gate and the source to the VSS terminal 123.

Next, the connection of the comparison circuit 130 will be described. The gate of the Pch transistor 201 is connected to the gate of the Pch transistor 301, the gate of the Pch transistor 302, the drain of the Pch transistor 201, and the constant current circuit 303, and the source is connected to the VDD terminal 121. The back gate is connected to the VDD terminal 121. The drain of the Pch transistor 302 is connected to the inverter 205 and the constant current circuit 304. The source is connected to the drain of the Pch transistor 301 and the drain of the Pch transistor 305, and the back gate is connected to Output terminal 122. The source of the Pch transistor 301 is connected to the output terminal 122, and the back gate is connected to the output terminal 122. The gate of Pch transistor 305 is connected to the output of inverter 205, the source is connected to output terminal 122, and the back gate is connected to output terminal 122. The output of the inverter 205 is connected to an inverter 206 which is connected as a power source to the output terminal 122. The output of inverter 206 is coupled to level shifter 207 and CONT terminal 223, which is coupled to output terminal 122 as a power source. The output of the level shifter 207 is connected to an inverter 207 which is connected as a power source to the VDD terminal 121. The output of inverter 208 is connected to CONTX terminal 222, which is connected as power supply to VDD terminal 121. The constant current circuit 303 and the constant current circuit 304 are N-channel ‧ depletion MOS transistors, both of which connect the gate and the source to the VSS terminal 123, and use the drain as the output. The CONT terminal 223 is a junction to the node 111 of FIG. 1, and the CONTX terminal 222 is a junction to the node 110 of FIG.

Next, the operation of the voltage regulator using the comparison circuit of the second embodiment will be described.

When the potential of the VDD terminal 121 is sufficiently higher than the potential of the output terminal 122, the gate-source voltage of the Pch transistor 201 is more sufficient than the gate-source voltage of the Pch transistor 301 and the Pch transistor 302. Since the ground is high, the potential of the drain of the Pch transistor 302 is at the "L" level (the potential of the VSS terminal 123). The inverters 205 and 206 for waveform shaping have the output of the inverter 205 being "H" (the potential of the output terminal 122), the Pch transistor 305 being in the OFF state, and the output of the inverter 206 being the CONT terminal 223. The voltage is formed at the "L" level. The level shifter 207 converts the potential level of the output terminal 122 to the potential level of the VDD terminal 121. Inverter 208 inverts the output voltage of level shifter 207. When the voltage of the CONT terminal 223 is at the "L" level, the CONTX terminal 222 of the output of the inverter 208 is at the potential level of the VDD terminal 121. At this time, since the potential of the substrate (NWELL) of the Pch transistor 103 is in the ON state and the Pch transistor 106 is in the OFF state, the potential of the VDD terminal 121 is set. That is, the potential higher than the potential of the VDD terminal 121 and the potential of the output terminal 122 becomes the substrate (NWELL) potential of the Pch transistor 103. At this time, the Pch transistor 104 is in an OFF state. Generally, when the power source is connected to the VDD terminal 121, the potential of the VDD terminal 121 > the potential of the output terminal 122.

Next, once the potential of the VDD terminal 121 falls, since the Pch transistor 305 is in an OFF state, the voltage and output terminal of the VDD terminal 121 are compared in accordance with the Pch transistor 301, the composite transistor of the Pch transistor 302, and the Pch transistor 201. The voltage of the 122 terminal. Once the potential of the VDD terminal 121 falls, only ΔV1 falls compared to the potential of the output terminal 122, because the gate-source voltage of the Pch transistor 201 is greater than the gate-source of the Pch transistor 301 and the Pch transistor 302. Since the inter-voltage is only lower by ΔV1, the potential of the drain of the Pch transistor 302 is at the "H" level (the potential of the output terminal 122). With the inverters 205 and 206 for waveform shaping, the output of the inverter 205 is at the "L" level, the Pch transistor 305 is in the ON state, and the voltage of the CONT terminal 223 of the output of the inverter 206 is formed. H" level (potential of output terminal 122). The level shifter 207 converts the potential level of the output terminal 122 to the potential level of the VDD terminal 121. Inverter 208 inverts the output voltage of level shifter 207. When the voltage of the CONT terminal 223 is at the "H" level, the CONTX terminal 222 of the output of the inverter 208 is at the "L" level. At this time, the potential of the substrate (NWELL) of the Pch transistor 103 of FIG. 1 is in the ON state of the Pch transistor 106, and the Pch transistor 105 is in the OFF state, so that it becomes the potential of the output terminal 122. That is, the potential higher than the potential of the VDD terminal 121 and the potential of the output terminal 122 becomes the substrate (NWELL) potential of the Pch transistor 103. At this time, the Pch transistor 104 is in an ON state, and the Pch transistor 103 is turned off by forming the gate of the Pch transistor 103 at the same potential as the output terminal 122.

The voltage of ΔV1 is as in the equation (1).

[Formula 1]

Here, I is the current value of the constant current circuits 303, 304, μ is the mobility of the Pch transistor 201 and the Pch transistor 301 and the Pch transistor 302, and L6 is the L length of the Pch transistor 301 and the Pch transistor 302. And L5 is the L length of the transistor of the Pch transistor 201, W6 is the W length of the Pch transistor 301 and the Pch transistor 302, and W5 is the W length of the Pch transistor 201.

Next, when the potential of the VDD terminal 121 rises, since the Pch transistor 305 is in the ON state, the voltage of the VDD terminal 121 and the output terminal 122 are compared in accordance with the transistors of the Pch transistor 201 and the Pch transistor 302. When the current values of the constant current circuits 303 and 304 are equal, and the type of the transistor (VTH, mobility, etc.) of the Pch transistor 201 and the Pch transistor 302 is L long and the W length is the same, the ΔV1 of the equation (1) becomes When ΔV1 = 0, when the voltage of the VDD terminal 121 is almost equal to the voltage of the output terminal 122, the voltages of the CONT terminal 223 and the CONTX terminal 222 are inverted.

4 is a voltage waveform of the CONT terminal 223 and the CONTX terminal 222 when the horizontal axis is the time, the vertical axis is the voltage, and the voltage of the output terminal 122 is constant, and the voltage of the VDD terminal 121 is changed. When the voltage of the VDD terminal 121 is only decreased by ΔV1 from the voltage of the output terminal 122, the voltages of the CONT terminal 223 and the CONTX terminal 222 are reversed, and then the voltage of the VDD terminal 121 is raised, and the voltage of the VDD terminal 121 and the output terminal are When the voltages of 122 are equal, the voltages of the CONT terminal 223 and the CONTX terminal 222 are reversed. As a result, hysteresis is added between the voltage of the VDD terminal 121 that switches the potential of the substrate (NWELL) of the Pch transistor 103 and the voltage of the output terminal 122. Thereby, even if the voltage of the VDD terminal 121 is close to the voltage of the output terminal 122, there is no erroneous operation, and the substrate (NWELL) potential of the Pch transistor 103 can be reliably switched.

In addition, when the voltage of the VDD terminal 121 is lowered, the value of the ΔV1 needs to be set so that the parasitic diode between the output terminal 122 of the Pch transistor 103 and the substrate does not turn ON. The direction is below the ON voltage (about 0.6V). Usually, the value of ΔV1 is around 50 mV to 200 mV.

3 is a diagram in which the Pch transistor 305 is connected in parallel with the Pch transistor 301. However, even if the Pch transistor 305 is connected in parallel with the Pch transistor 302, the same effect is obtained. Further, although it is shown in the first embodiment, it is preferable to use the configuration of Fig. 9 in the same manner as in the first embodiment.

[Example 3]

Fig. 5 is a view showing a third embodiment of the comparison circuit 130 of the voltage regulator of the present invention shown in Fig. 1. The comparison circuit 130 of the third embodiment is a constant current circuit 303, a constant current circuit 304, a Pch transistor 202, a Pch transistor 501, a Pch transistor 502, a Pch transistor 503, an inverter 205, an inverter 206, The inverter 208 and the level shifter 207 are formed. The difference from FIG. 2 is that the Pch transistor 201 is composed of two Pch transistors 501 and Pch transistors 502, and a Pch transistor 503 for realizing a hysteresis function is added. Further, the constant current circuits 203 and 204 are specifically shown in an N-channel ‧ depletion MOS transistor in which the gate and the source are connected to the VSS terminal 123 in the same manner as in FIG. 3 .

Next, the connection of the comparison circuit 130 will be described. The gate of the Pch transistor 501 is connected to the gate of the Pch transistor 202, the gate of the Pch transistor 502, the drain of the Pch transistor 502, and the constant current circuit 303, and the source is connected to the VDD terminal 121. The drain is connected to the source of the Pch transistor 502 and the drain of the Pch transistor 503, and the back gate is connected to the VDD terminal 121. The gate of the Pch transistor 503 is connected to the output of the level shifter 207, the source is connected to the VDD terminal 121, and the back gate is connected to the VDD terminal 121. The drain of Pch transistor 202 is connected to inverter 205 and constant current circuit 304, the source is connected to output terminal 122, and the back gate is connected to output terminal 122. The output of the inverter 205 is connected to an inverter 206 which is connected as a power source to the output terminal 122. The output of inverter 206 is coupled to level shifter 207 and CONT terminal 223, which is coupled to output terminal 122 as a power source. The output of the level shifter 207 is connected to an inverter 207 which is connected as a power source to the VDD terminal 121. The output of inverter 208 is connected to CONTX terminal 222, which is connected as power supply to VDD terminal 121. The constant current circuit 303 and the constant current circuit 304 are N-channel ‧ depletion MOS transistors, both of which connect the gate and the source to the VSS terminal 123, and use the drain as the output. The CONT terminal 223 is a junction to the node 111 of FIG. 1, and the CONTX terminal 222 is a junction to the node 110 of FIG.

Next, the operation of the voltage regulator using the comparison circuit of the third embodiment will be described. When the potential of the VDD terminal 121 is sufficiently higher than the potential of the output terminal 122, the Pch transistor 501 and the Pch transistor 502 are in an ON state, the Pch transistor 202 is in an OFF state, and the potential of the drain of the Pch transistor 202 is " The L" level (potential of the VSS terminal 123). With the inverters 205 and 206 for waveform shaping, the voltage of the CONT terminal 223 of the output of the inverter 206 is at the "L" level. The level shifter 207 converts the potential level of the output terminal 122 to the potential level of the VDD terminal 121. Inverter 208 inverts the output voltage of level shifter 207. When the voltage of the CONT terminal 223 is at the "L" level, the output of the level shifter 207 is at the "L" level, the Pch transistor 503 is in the ON state, and the CONTX terminal 222 of the output of the inverter 208 is VDD. The potential level of the terminal 121. At this time, the potential of the substrate (NWELL) of the Pch transistor 103 of FIG. 1 is in the ON state of the Pch transistor 105, and the Pch transistor 106 is in the OFF state, so that it becomes the potential of the VDD terminal 121. That is, the potential higher than the potential of the VDD terminal 121 and the potential of the output terminal 122 becomes the substrate (NWELL) potential of the Pch transistor 103. At this time, the Pch transistor 104 is in an OFF state. Generally, when the power source is connected to the VDD terminal 121, the potential of the VDD terminal 121 > the potential of the output terminal 122.

Next, when the potential of the VDD terminal 121 is lowered, since the Pch transistor 503 is in an ON state, the voltage of the VDD terminal 121 and the voltage of the output terminal 122 are compared in accordance with the Pch transistor 502 and the Pch transistor 202. When the current values of the constant current circuits 303 and 304 are equal, and the type of the transistor (VTH, mobility, etc.) of the Pch transistor 502 and the Pch transistor 202 is L long and the W length is the same, once the potential of the VDD terminal 121 is lowered to When the potential of the output terminal 122 is substantially the same value, the Pch transistor 502 is in the OFF state, the Pch transistor 202 is in the ON state, and the potential of the drain of the Pch transistor 202 is at the "H" level (the potential of the output terminal 122). . With the inverters 205 and 206 for waveform shaping, the voltage of the CONT terminal 223 of the output of the inverter 206 is at the "H" level (the potential of the output terminal 122). The level shifter 207 converts the potential level of the output terminal 122 to the potential level of the VDD terminal 121. Inverter 208 inverts the output voltage of level shifter 207. When the voltage of the CONT terminal 223 is "H" level, the output of the level shifter 207 is the voltage of the VDD terminal 121, the Pch transistor 503 is turned OFF, and the CONTX terminal 222 of the output of the inverter 208 is "L" level. At this time, since the potential of the substrate (NWELL) of the Pch transistor 103 is in the ON state and the Pch transistor 105 is in the OFF state, the potential of the output terminal 122 is set. That is, the potential higher than the potential of the VDD terminal 121 and the potential of the output terminal 122 becomes the substrate (NWELL) potential of the Pch transistor 103. At this time, the Pch transistor 104 is in an ON state, and the Pch transistor 103 is turned off by forming the gate of the Pch transistor 103 at the same potential as the output terminal 122.

Next, once the potential of the VDD terminal 121 rises, since the Pch transistor 503 is in an OFF state, the voltage and output terminal of the VDD terminal 121 are compared in accordance with the composite transistor of the Pch transistor 501 and the Pch transistor 502 and the Pch transistor 202. The voltage of 122. When the voltage of the VDD terminal 121 is higher than the voltage of the output terminal 122 by ΔV2, the CONT terminal 223 and the CONTX terminal 222 are inverted.

The voltage of ΔV2 is as in the equation (2).

[Formula 2]

Here, I is the current value of the constant current circuits 303, 304, μ is the mobility of the Pch transistor 202 and the Pch transistor 501 and the Pch transistor 502, L6 is the L length of the Pch transistor 202, and L5 is the Pch transistor. 501 is the sum of the L length of the Pch transistor 502, W6 is the W length of the Pch transistor 202, and W5 is the W length of the Pch transistor 501 and the Pch transistor 502.

6 is a voltage waveform of the CONT terminal 223 and the CONTX terminal 222 when the horizontal axis is the time, the vertical axis is the voltage, and the voltage of the output terminal 122 is constant, and the voltage of the VDD terminal 121 is changed. When the voltage of the VDD terminal 121 falls and becomes equal to the voltage of the output terminal 122, the voltages of the CONT terminal 223 and the CONTX terminal 222 are inverted. Then, the voltage of the VDD terminal 121 is raised, and when the voltage of the VDD terminal 121 is higher than the voltage of the output terminal 122 by ΔV2, the voltages of the CONT terminal 223 and the CONTX terminal 222 are inverted. As a result, hysteresis is added between the voltage of the VDD terminal 121 that switches the potential of the substrate (NWELL) of the Pch transistor 103 and the voltage of the output terminal 122. Thereby, even if the voltage of the VDD terminal 121 is close to the voltage of the output terminal 122, there is no erroneous operation, and the substrate (NWELL) potential of the Pch transistor 103 can be reliably switched.

In addition, when the voltage of the VDD terminal 121 rises, the value of the ΔV2 needs to be set so that the parasitic diode between the VDD terminal 121 of the Pch transistor 103 and the substrate does not turn ON. The direction is below the ON voltage (about 0.6V). Usually, the value of ΔV2 is around 50 mV to 200 mV.

Further, FIG. 5 shows that the Pch transistor 503 is connected in parallel with the Pch transistor 501. However, it is obvious that the Pch transistor 503 and the Pch transistor 502 are connected in parallel, and the same effect is obtained. Further, although it is shown in the first embodiment, it is preferable to use the configuration of Fig. 9 in the same manner as in the first embodiment. Further, although it is shown in the first embodiment, it is preferable to use the configuration of Fig. 9 in the same manner as in the first embodiment.

[Example 4]

Fig. 12 is a circuit diagram showing a voltage regulator of a second embodiment. The difference from FIG. 1 is that the back gate of the Pch transistor 104 is connected to the back gate of the Pch transistor 103, and the point of the delay circuit 1201 is added to the output of the comparison circuit 130. The output is that the output of the comparison circuit 130 is connected to the delay circuit 1201, and the output of the delay circuit 1201 is output as the node 110 and the node 111.

Next, the operation of the voltage regulator according to the second embodiment will be described. When the voltage of the VDD terminal 121 is greater than the voltage of the output terminal 122, the voltage of the node 111 becomes the "L" level, the voltage of the node 110 becomes the "H" level, the Pch transistor 105 is turned on, and the Pch transistor 106 is turned off. . At this time, the substrate (NWELL) potential of the Pch transistor 104 is a voltage at which the VDD terminal 121 is formed, and the Pch transistor 104 can be surely turned off.

The delay circuit 1201 prevents the voltages of the nodes 110 and 111 from simultaneously forming an "L" level by a timer circuit. In this way, the Pch transistors 105 and 106 can be prevented from being simultaneously turned on, current flows from the VDD terminal 121 to the output terminal 122, and flows from the output terminal 122 to the VDD terminal 121.

Further, although the voltage regulator of the second embodiment has a problem that the Pch transistors 105 and 106 are simultaneously turned on, the delay circuit 1201 can be operated without the delay.

[Example 5]

Fig. 13 is a view showing a third embodiment of the error amplifier circuit 102 of the voltage regulator of the present invention shown in Fig. 1. The difference from FIG. 9 is that a Pch transistor 803 is inserted under the constant current circuit 705 to connect the gate to the point of the CONT terminal 823.

Next, the action will be described. When the potential of the output terminal 122 is higher than the potential of the VDD terminal 121, the Pch transistor 104 is in an ON state, and the output 723 of the error amplifier 102 is connected to the output terminal 122. Since the Nch transistor 702 is in an ON state, the output terminals 122 and the sources of the Nch transistors 701 and 702 are electrically connected. Then, when the Nch transistors 802 and 803 are in the OFF state, the current path of the constant current circuit 705 is blocked, and current can be prevented from flowing from the output terminal 122 through the Nch transistor 702 to the VSS terminal 123.

In addition, although FIG. 13 is an example of an error amplifier which is a one-stage amplifier circuit, the error amplifier circuit may be a multi-stage amplifier circuit of two or more stages. In this case, as shown in Fig. 13, a Pch transistor 801 having a function for blocking the current path is inserted in the output of the error amplifier and the VDD side, and the output of the error amplifier and the VSS side are inserted to block the current path. The Nch transistor 802 and the Pch transistor 803 of the function can be used.

[Embodiment 6]

Fig. 14 is a view showing a fourth embodiment of the error amplifier circuit 102 of the voltage regulator of the present invention shown in Fig. 1. The difference from FIG. 13 is that the Nch transistors 802 and 803 are deleted, and the CONT terminal 823 and the constant current circuit 705 are connected.

Next, the action will be described. When the potential of the output terminal 122 is higher than the potential of the VDD terminal 121, the Pch transistor 104 is in an ON state, the Pch transistor 801 is turned off, and the output 723 of the error amplifier 102 is connected to the output terminal 122. Since the Nch transistor 702 is in an ON state, the output terminals 122 and the sources of the Nch transistors 701 and 702 are electrically connected. Further, according to the signal of the CONT terminal 823, the constant current circuit 705 is turned off to interrupt the current path, and current can be prevented from flowing from the output terminal 122 through the Nch transistor 702 to the VSS terminal 123.

In addition, FIG. 14 is an example of an error amplifier which is a one-stage amplifier circuit, but the error amplifier circuit may be a multi-stage amplifier circuit of two or more stages. In this case, the configuration in which the constant current circuit is turned off in accordance with the signal of the CONT terminal 823 may be formed.

101. . . Vref circuit

102. . . Error amplifier

112. . . Backup battery

113. . . load

121. . . VDD terminal

122. . . Output terminal

123. . . VSS terminal

130. . . Comparison circuit

203. . . Constant current circuit

204. . . Constant current circuit

207. . . Level shifter

222. . . CONTX terminal

223. . . CONT terminal

303. . . Constant current circuit

304. . . Constant current circuit

705. . . Constant current circuit

721. . . +input terminal

722. . . -Input terminal

723. . . EOUT terminal

823. . . CONT terminal

1105. . . Comparators

Fig. 1 is a circuit diagram of a voltage regulator of a first embodiment of the present invention.

Fig. 2 is a circuit diagram showing a comparison circuit of the first embodiment of the voltage regulator of the present invention.

Fig. 3 is a circuit diagram showing a comparison circuit of a second embodiment of the voltage regulator of the present invention.

Fig. 4 is a view showing voltage waveforms of respective portions of a comparison circuit of a second embodiment of the voltage regulator of the present invention.

Fig. 5 is a circuit diagram showing a comparison circuit of a third embodiment of the voltage regulator of the present invention.

Fig. 6 is a view showing voltage waveforms of respective portions of a comparison circuit of a third embodiment of the voltage regulator of the present invention.

Fig. 7 is a circuit diagram of an error amplifier of a general voltage regulator.

Fig. 8 is a cross-sectional view showing a P-channel type MOS transistor.

Figure 9 is a circuit diagram of an error amplifier of a second embodiment of the voltage regulator of the present invention.

Fig. 10 is a cross-sectional view showing a P-channel type MOS transistor.

Fig. 11 is a circuit diagram showing a conventional voltage regulator.

Figure 12 is a circuit diagram of a voltage regulator of a second embodiment of the present invention.

Figure 13 is a circuit diagram of an error amplifier of a third embodiment of the voltage regulator of the present invention.

Figure 14 is a circuit diagram of an error amplifier of a fourth embodiment of the voltage regulator of the present invention.

101. . . Vref circuit

102. . . Error amplifier

103, 104, 105, 106. . . Pch transistor

107, 108. . . resistance

109. . . Nch transistor

110, 111. . . node

112. . . Backup battery

113. . . load

121. . . VDD terminal

122. . . Output terminal

123. . . VSS terminal

130. . . Comparison circuit

R1, R2. . . resistance

Claims (10)

A voltage regulator comprising: an output transistor disposed between a power supply terminal and an output terminal; and an error amplifier configured to control a gate voltage of the output transistor by a voltage of the output terminal; a second transistor for connecting the substrate of the output transistor to the power supply terminal; a third transistor for connecting the substrate of the output transistor to the output terminal; and a comparison circuit Comparing the voltage between the power supply terminal and the output terminal, and switching and controlling the second transistor and the third transistor according to the comparison result; wherein the comparison circuit includes: a fourth transistor, the source is Connected to the power supply terminal, the gate is connected to the drain, the drain is connected to the first constant current circuit; and the fifth transistor is connected to the output terminal, and the gate is connected to the fourth a gate of the transistor, the drain is connected to the second constant current circuit, and the comparison is output according to the voltage of the connection point of the fifth transistor and the second constant current circuit fruit. The voltage regulator according to claim 1, wherein the comparison circuit causes the second transistor to be in an ON state when a voltage of the power supply terminal is higher than a voltage of the output terminal, and a voltage of the power supply terminal When the potential of the output terminal is lower than the potential of the output terminal, the third transistor is turned on. The voltage regulator of claim 2, wherein the comparison circuit has a hysteresis function. The voltage regulator according to claim 3, wherein the hysteresis function has a sixth transistor connected in series with the fifth transistor, and a seventh transistor connected to the fifth transistor. In parallel, the seventh transistor is controlled by the output of the aforementioned comparison circuit. The voltage regulator according to claim 3, wherein the hysteresis function has an eighth transistor connected in series with the fourth transistor, and a ninth transistor connected to the fourth transistor. In parallel, the ninth transistor is controlled by the output of the aforementioned comparison circuit. The voltage regulator according to claim 1, wherein the error amplifier has a tenth transistor connected between an output of the error amplifier and the power supply terminal, and a substrate connected to an output of the error amplifier. The eleventh transistor is disposed between the output of the error amplifier and the ground terminal, and turns off the tenth transistor and the eleventh transistor when the voltage of the output terminal is higher than the voltage of the power terminal. The voltage regulator according to claim 1, wherein the error amplifier has a tenth transistor connected between an output of the error amplifier and the power supply terminal, and a substrate connected to an output of the error amplifier. An eleventh transistor disposed between the output of the error amplifier and the third constant current circuit; and a twelfth transistor disposed between the third constant current circuit and the ground terminal, wherein the output terminal When the voltage is higher than the voltage of the power supply terminal, the tenth transistor, the eleventh transistor, and the twelfth transistor are turned off. The voltage regulator according to claim 1, wherein the error amplifier has a tenth transistor connected between an output of the error amplifier and the power supply terminal, and a substrate connected to an output of the error amplifier. And the third constant current circuit, wherein the third constant current circuit is turned off when the voltage of the output terminal is higher than the voltage of the power supply terminal. The voltage regulator according to claim 1, wherein the voltage regulator includes: a third transistor that connects an output of the error amplifier to the output terminal, and a substrate of the thirteenth transistor is connected to the foregoing The substrate of the output transistor. The voltage regulator according to any one of claims 1 to 9, wherein the voltage regulator includes an output that is input to the comparison circuit, and switches between the second transistor and the third transistor. In the delay circuit, the delay circuit is controlled not to simultaneously turn on the second transistor and the third transistor.