TWI495060B - Power component package structure - Google Patents
Power component package structure Download PDFInfo
- Publication number
- TWI495060B TWI495060B TW100147114A TW100147114A TWI495060B TW I495060 B TWI495060 B TW I495060B TW 100147114 A TW100147114 A TW 100147114A TW 100147114 A TW100147114 A TW 100147114A TW I495060 B TWI495060 B TW I495060B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate
- layer
- source
- drain
- metal pillar
- Prior art date
Links
Classifications
-
- H10W72/20—
Landscapes
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
本發明是有關於一種功率元件，且特別是有關於一種功率元件之封裝結構。The present invention relates to a power component, and more particularly to a package structure for a power component.
隨著科技的演進，各種電子裝置不斷地往小尺寸及高效能的方向發展，在各種電子裝置中，功率元件(或可稱功率半導體)已成為不可或缺的基本元件。因此，相關技術在近年來蓬勃發展，也帶動這些功率元件的技術迅速成長，其中，上述的功率元件可包含金屬氧化物半導體場效電晶體(Power Metal Oxide Semiconductor Field Transistor)與雙極性電晶體(Bipolar Junction Transistor,BJT)等等。With the evolution of technology, various electronic devices are continually moving toward small size and high efficiency. Among various electronic devices, power components (or power semiconductors) have become indispensable basic components. Therefore, related technologies have prospered in recent years, and the technology of these power components has also been rapidly developed. The above power components may include a metal oxide semiconductor field transistor (Power Metal Oxide Semiconductor Field Transistor) and a bipolar transistor ( Bipolar Junction Transistor, BJT) and more.
功率元件的封裝方式主要係在完成晶片製程後，至封裝廠經由晶片切割、晶片放置、打線模壓裁分的一連串步驟來實現。一般而言，在經由上述步驟所製成的功率元件中，汲極會與源極、閘極位於功率元件的不同表面。舉例而言，汲極係位於功率元件的正面，而源極與閘極則係位於背面，故在操作時位於背面之源極及閘極可直接接觸外部電子元件，而位於正面的汲極則必須拉線至外部電子元件，對於製造者而言，甚為不便。The packaging method of the power component is mainly implemented after a series of steps of completing the wafer process and going to the packaging factory through wafer cutting, wafer placement, wire stamping and cutting. In general, in a power device fabricated through the above steps, the drain and the source and the gate are located on different surfaces of the power device. For example, the drain is located on the front side of the power device, and the source and the gate are on the back side. Therefore, the source and gate on the back side can directly contact external electronic components during operation, while the drain on the front side is It is inconvenient for the manufacturer to pull the wires to the external electronic components.
有鑑於此，本發明之一技術態樣在於提供一種功率元件之封裝結構。In view of this, one aspect of the present invention provides a package structure of a power component.
本發明之一目的在於將三個電極形成於功率元件的同一平面上，故可消弭拉線所帶來的不便，從而克服先前技術所遭遇的問題。One of the objects of the present invention is to form three electrodes on the same plane of the power element, so that the inconvenience caused by the cable can be eliminated, thereby overcoming the problems encountered in the prior art.
本發明之另一目的在於提供一種晶圓級的功率元件封裝，可在完整的晶圓下完成封裝後再切割成為每個獨立的功率元件。Another object of the present invention is to provide a wafer level power device package that can be packaged under a complete wafer and then diced into individual power components.
依據本發明之一實施方式，一種功率元件封裝結構包含一基材、一源極層、一閘極層、一汲極層、一介電層、至少一汲極焊墊、至少一源極焊墊、至少一閘極焊墊、至少一汲極金屬柱、至少一源極金屬柱、以及至少一閘極金屬柱。基材具有一第一表面及相對於第一表面之一第二表面。源極層與閘極層係設置於基材之第一表面。汲極層係設置於基材之第二表面。介電層覆蓋源極層、閘極層及基材之第一表面。汲極焊墊、源極焊墊及閘極焊墊係設置於介電層上。汲極金屬柱連接汲極層與汲極焊墊。源極金屬柱連接源極層與源極焊墊。閘極金屬柱連接閘極層與閘極焊墊。According to an embodiment of the invention, a power device package structure includes a substrate, a source layer, a gate layer, a drain layer, a dielectric layer, at least one drain pad, and at least one source solder. a pad, at least one gate pad, at least one gate metal pillar, at least one source metal pillar, and at least one gate metal pillar. The substrate has a first surface and a second surface relative to the first surface. The source layer and the gate layer are disposed on the first surface of the substrate. The drain layer is disposed on the second surface of the substrate. The dielectric layer covers the source layer, the gate layer, and the first surface of the substrate. The drain pad, the source pad and the gate pad are disposed on the dielectric layer. The bungee metal column connects the drain layer and the drain pad. The source metal pillar connects the source layer and the source pad. The gate metal pillar is connected to the gate layer and the gate pad.
本發明之另一技術態樣在於提供一種功率元件封裝結構之製造方法，依據一實施方式，此製造方法包含下列步驟：形成一源極層及一閘極層於一基材之一第一表面，並形成一汲極層於基材之相對於第一表面之一第二表面；形成一介電層於源極層、閘極層、及基材；標定出至少一汲極蝕刻區域、至少一源極蝕刻區域、及至少一閘極蝕刻區域；蝕刻上述汲極蝕刻區域、上述源極蝕刻區域、及上述閘極蝕刻區域，以分別形成至少一汲極通道、至少一源極通道、及至少一閘極通道；灌注金屬至上述汲極通道、上述源極通道、及上述閘極通道，以分別形成至少一汲極金屬柱、至少一源極金屬柱、及至少一閘極金屬柱；分別形成至少一汲極焊墊、至少一源極焊墊、及至少一閘極焊墊於上述汲極金屬柱、上述源極金屬柱、及上述閘極金屬柱上；以及切割基材與介電層。Another aspect of the present invention provides a method of fabricating a power device package structure. According to an embodiment, the method includes the steps of: forming a source layer and a gate layer on a first surface of a substrate. And forming a drain layer on the second surface of the substrate relative to the first surface; forming a dielectric layer on the source layer, the gate layer, and the substrate; calibrating at least one drain etching region, at least a source etched region and at least one gate etched region; etching the drain etched region, the source etched region, and the gate etched region to form at least one drain channel, at least one source channel, and At least one gate channel; injecting metal into the drain channel, the source channel, and the gate channel to form at least one drain metal pillar, at least one source metal pillar, and at least one gate metal pillar; Forming at least one drain pad, at least one source pad, and at least one gate pad on the drain metal pillar, the source metal pillar, and the gate metal pillar; and cutting the substrate and the dielectric layer Floor.
藉由以上技術手段，本發明之實施方式可透過汲極金屬柱、源極金屬柱、及閘極金屬柱將汲極層、源極層、與閘極層分別導通至汲極焊墊、源極焊墊、及閘極焊墊。由於汲極焊墊、源極焊墊、與閘極焊墊係共同設置於介電層上，因此可將三個電極引導至同一平面上，以避免拉線所造成的困擾。According to the above technical means, the embodiment of the present invention can conduct the drain layer, the source layer, and the gate layer to the drain pad and the source respectively through the drain metal pillar, the source metal pillar, and the gate metal pillar. Polar pad, and gate pad. Since the drain pad, the source pad, and the gate pad are disposed on the dielectric layer together, the three electrodes can be guided to the same plane to avoid the trouble caused by the wire.
以上所述僅係用以闡明本發明之目的、達成此目的之技術手段、以及其所產生的功效等等，本發明之具體細節將於下文中的實施方式及相關圖式中詳細介紹。The above is only to clarify the object of the present invention, the technical means for achieving the same, and the effects thereof, and the like, and the specific details of the present invention will be described in detail in the following embodiments and related drawings.
以下將以圖式揭露本發明之複數實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。換言之，在本發明部分實施方式中，這些細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。The embodiments of the present invention are disclosed in the following drawings, and for the purpose of clarity However, it should be understood that these practical details are not intended to limit the invention. In other words, these details are not necessary in some embodiments of the invention. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.
第1圖繪示依據本發明一實施方式之功率元件封裝結構之剖面圖。如圖所示，一種功率元件封裝結構包含一基材110、一源極層210、一閘極層220、一汲極層230、一介電層120、一汲極焊墊234、一源極焊墊214、一閘極焊墊224、一汲極金屬柱232、一源極金屬柱212、以及一閘極金屬柱222。基材110具有一第一表面112及相對於第一表面112之一第二表面114。源極層210及閘極層220係設置於基材110之第一表面112。汲極層230係設置於基材110之第二表面114。介電層120覆蓋源極層210、閘極層220及基材110之第一表面112。源極焊墊214、閘極焊墊224與汲極焊墊234均係設置於介電層120上。汲極金屬柱232連接汲極層230與汲極焊墊234。源極金屬柱212連接源極層210與源極焊墊214。閘極金屬柱222連接閘極層220與閘極焊墊224。具體而言，汲極焊墊234、源極焊墊214、與閘極焊墊224係設置於介電層120之同一表面。1 is a cross-sectional view showing a power device package structure according to an embodiment of the present invention. As shown, a power device package structure includes a substrate 110, a source layer 210, a gate layer 220, a drain layer 230, a dielectric layer 120, a drain pad 234, and a source. Pad 214, a gate pad 224, a drain metal post 232, a source metal post 212, and a gate metal post 222. The substrate 110 has a first surface 112 and a second surface 114 opposite the first surface 112. The source layer 210 and the gate layer 220 are disposed on the first surface 112 of the substrate 110. The drain layer 230 is disposed on the second surface 114 of the substrate 110. The dielectric layer 120 covers the source layer 210, the gate layer 220, and the first surface 112 of the substrate 110. The source pad 214, the gate pad 224 and the drain pad 234 are both disposed on the dielectric layer 120. The drain metal pillar 232 connects the drain layer 230 and the drain pad 234. The source metal pillar 212 connects the source layer 210 and the source pad 214. The gate metal pillar 222 is connected to the gate layer 220 and the gate pad 224. Specifically, the drain pad 234, the source pad 214, and the gate pad 224 are disposed on the same surface of the dielectric layer 120.
藉由以上實施方式，本發明可利用汲極金屬柱232、源極金屬柱212、及閘極金屬柱222將汲極層230、源極層210、與閘極層220分別導通至汲極焊墊234、源極焊墊214、及閘極焊墊224。由於汲極焊墊234、源極焊墊214、與閘極焊墊224係設置於介電層120之同一表面，因此可透過上述金屬柱將三個電極引導至同一平面上，以避免拉線所造成的困擾。According to the above embodiment, the present invention can utilize the gate metal pillar 232, the source metal pillar 212, and the gate metal pillar 222 to conduct the drain layer 230, the source layer 210, and the gate layer 220 to the gate electrode respectively. Pad 234, source pad 214, and gate pad 224. Since the drain pad 234, the source pad 214, and the gate pad 224 are disposed on the same surface of the dielectric layer 120, the three electrodes can be guided to the same plane through the metal pillar to avoid the wire. The trouble caused.
於部分實施方式中，源極金屬柱212、閘極金屬柱222、及汲極金屬柱232可互相平行。具體而言，源極金屬柱212、閘極金屬柱222、及汲極金屬柱232之平行方向可與基材110之第一表面112或第二表面114垂直，換言之，上述金屬柱可平行於介電層120與基材110之堆疊方向。In some embodiments, the source metal pillar 212, the gate metal pillar 222, and the drain metal pillar 232 may be parallel to each other. Specifically, the parallel direction of the source metal pillar 212, the gate metal pillar 222, and the drain metal pillar 232 may be perpendicular to the first surface 112 or the second surface 114 of the substrate 110. In other words, the metal pillar may be parallel to The stacking direction of the dielectric layer 120 and the substrate 110.
於部分實施方式中，源極金屬柱212可垂直貫穿介電層120而連接源極層210及源極焊墊214。相似地，閘極金屬柱222可垂直貫穿介電層120而連接閘極層220與閘極焊墊224。汲極金屬柱232可垂直貫穿基材110及介電層120而連接汲極層230與汲極焊墊234。上述之『垂直』所代表的方向可為垂直於基材的110第一表面112或第二表面114。In some embodiments, the source metal pillars 212 may extend through the dielectric layer 120 to connect the source layer 210 and the source pads 214. Similarly, the gate metal pillar 222 can vertically connect through the dielectric layer 120 to connect the gate layer 220 and the gate pad 224. The gate metal 232 can connect the drain layer 230 and the drain pad 234 vertically through the substrate 110 and the dielectric layer 120. The direction indicated by "vertical" above may be 110 first surface 112 or second surface 114 perpendicular to the substrate.
於部分實施方式中，源極層210與閘極層220投影至基材110之第二表面114的位置與汲極金屬柱232彼此分開。換句話說，汲極金屬柱232不會接觸或貫穿源極層210及閘極層220。In some embodiments, the location of the source layer 210 and the gate layer 220 projected onto the second surface 114 of the substrate 110 and the gate metal posts 232 are separated from each other. In other words, the drain metal pillar 232 does not contact or penetrate the source layer 210 and the gate layer 220.
於本實施方式中，源極金屬柱212係位於汲極金屬柱232與閘極金屬柱222之間。具體而言，如第1圖所示，汲極金屬柱232、源極金屬柱212、與閘極金屬柱222係由左至右依序排列。換言之，汲極焊墊234、源極焊墊214、與閘極焊墊224係由左至右依序設置於介電層120上。In the present embodiment, the source metal pillar 212 is located between the gate metal pillar 232 and the gate metal pillar 222. Specifically, as shown in FIG. 1, the gate metal pillar 232, the source metal pillar 212, and the gate metal pillar 222 are sequentially arranged from left to right. In other words, the drain pad 234, the source pad 214, and the gate pad 224 are sequentially disposed on the dielectric layer 120 from left to right.
第2圖繪示依據本發明另一實施方式之功率元件封裝結構之剖面圖。本實施方式與第1圖主要差異在於電極的排列方式不同。具體而言，汲極金屬柱232係位於源極金屬柱212與閘極金屬柱222之間。如圖所示，閘極金屬柱222、汲極金屬柱232、與源極金屬柱212係由左至右依序排列。換言之，閘極焊墊224、汲極焊墊234與源極焊墊214係由左至右依序設置於介電層120上。2 is a cross-sectional view showing a power device package structure according to another embodiment of the present invention. The main difference between this embodiment and the first embodiment is that the arrangement of the electrodes is different. Specifically, the gate metal pillar 232 is located between the source metal pillar 212 and the gate metal pillar 222. As shown, the gate metal pillars 222, the gate metal pillars 232, and the source metal pillars 212 are sequentially arranged from left to right. In other words, the gate pad 224, the drain pad 234 and the source pad 214 are sequentially disposed on the dielectric layer 120 from left to right.
相似於第1圖之實施方式，於第2圖中，源極金屬柱212、閘極金屬柱222與汲極金屬柱232可互相平行。源極層210與閘極層220投影至基材110之第二表面114的位置與汲極金屬柱232彼此分開。Similar to the embodiment of FIG. 1, in FIG. 2, the source metal pillar 212, the gate metal pillar 222, and the gate metal pillar 232 may be parallel to each other. The position where the source layer 210 and the gate layer 220 are projected to the second surface 114 of the substrate 110 and the gate metal pillars 232 are separated from each other.
第3圖繪示依據本發明又一實施方式之功率元件封裝結構之剖面圖。本實施方式與第1、2圖主要差異在於電極的排列方式不同。具體而言，閘極金屬柱222係位於源極金屬柱212與汲極金屬柱232之間。如圖所示，源極金屬柱212、閘極金屬柱222、與汲極金屬柱232係由左至右依序排列。換言之，源極焊墊214、閘極焊墊224、與汲極焊墊234係由左至右依序設置於介電層120上。3 is a cross-sectional view showing a power device package structure according to still another embodiment of the present invention. The main difference between this embodiment and the first and second figures is that the arrangement of the electrodes is different. Specifically, the gate metal pillars 222 are located between the source metal pillars 212 and the gate metal pillars 232. As shown, the source metal pillar 212, the gate metal pillar 222, and the gate metal pillar 232 are sequentially arranged from left to right. In other words, the source pad 214, the gate pad 224, and the drain pad 234 are sequentially disposed on the dielectric layer 120 from left to right.
相似於第1圖之實施方式，於第3圖中，源極金屬柱212、閘極金屬柱222與汲極金屬柱232可互相平行。源極層210與閘極層220投影至基材110之第二表面114的位置與汲極金屬柱232彼此分開。Similar to the embodiment of FIG. 1, in FIG. 3, the source metal pillar 212, the gate metal pillar 222, and the gate metal pillar 232 may be parallel to each other. The position where the source layer 210 and the gate layer 220 are projected to the second surface 114 of the substrate 110 and the gate metal pillars 232 are separated from each other.
如第1、2或3圖所示，於部分實施方式中，功率元件封裝結構進一步包含一金屬層130，設置於該汲極層230背對基材110之一表面，可用以導熱或是保護汲極層230。As shown in the first, second or third embodiment, in some embodiments, the power component package structure further includes a metal layer 130 disposed on the surface of the drain layer 230 opposite to the substrate 110 for heat conduction or protection. The bungee layer 230.
於部分實施方式中，介電層120之材料可包含，但不侷限於，聚亞醯胺樹脂(Polyimide)或環氧樹脂(Epoxy)。In some embodiments, the material of the dielectric layer 120 may include, but is not limited to, a polyimide resin or an epoxy resin (Epoxy).
第4A-4H圖繪示依據本發明之一實施方式之功率元件封裝結構之製造步驟的剖面圖。請參閱第4A圖，於本步驟中，係將源極層210及閘極層220形成於基材110之第一表面112，並將汲極層230形成於基材110之相對於第一表面112之一第二表面114。舉例而言，可將源極層210與閘極層220互相分開地形成於基材110之第一表面112，並將汲極層230完全覆蓋地形成於基材110之第二表面114。4A-4H are cross-sectional views showing the steps of fabricating a power device package structure in accordance with an embodiment of the present invention. Referring to FIG. 4A, in this step, the source layer 210 and the gate layer 220 are formed on the first surface 112 of the substrate 110, and the gate layer 230 is formed on the substrate 110 relative to the first surface. One of the second surfaces 114. For example, the source layer 210 and the gate layer 220 may be formed on the first surface 112 of the substrate 110 separately from each other, and the gate layer 230 may be completely covered on the second surface 114 of the substrate 110.
請參閱第4B圖，於本步驟中，係將金屬層130形成於汲極層230背對基材110之一表面。舉例而言，可將金屬層130完全覆蓋地形成於汲極層230背對基材110之表面。Referring to FIG. 4B, in this step, the metal layer 130 is formed on the surface of the drain layer 230 opposite to the substrate 110. For example, the metal layer 130 may be formed in a completely covered manner on the surface of the drain layer 230 opposite the substrate 110.
請參閱第4C圖，於本步驟中，係將介電層120於源極層210、閘極層220及基材110上。舉例而言，可將介電層120完全覆蓋地形成於源極層210、閘極層220與基材110上。於部分實施方式中，介電層120之材料可包含，但不侷限於，聚亞醯胺樹脂(Polyimide)或環氧樹脂(Epoxy)。Referring to FIG. 4C, in this step, the dielectric layer 120 is placed on the source layer 210, the gate layer 220, and the substrate 110. For example, the dielectric layer 120 can be formed over the source layer 210, the gate layer 220, and the substrate 110 in a complete coverage. In some embodiments, the material of the dielectric layer 120 may include, but is not limited to, a polyimide resin or an epoxy resin (Epoxy).
請參閱第4D圖，於本步驟中，係標定出至少一汲極蝕刻區域236、至少一源極蝕刻區域216、及至少一閘極蝕刻區域226。舉例而言，可在源極層210正上方標定源極蝕刻區域216；相似地，可在閘極層220正上方標定閘極蝕刻區域226。另外，可在汲極層230正上方且非源極層210或閘極層220之上方處標定汲極蝕刻區域236。Referring to FIG. 4D, in this step, at least one drain etched region 236, at least one source etched region 216, and at least one gate etched region 226 are labeled. For example, the source etched region 216 can be calibrated directly above the source layer 210; similarly, the gate etched region 226 can be calibrated directly above the gate layer 220. Additionally, the gate etched region 236 can be calibrated directly above the drain layer 230 and over the non-source layer 210 or the gate layer 220.
請參閱第4E圖，於本步驟中，蝕刻上述汲極蝕刻區域236(請併參閱第4D圖)、上述源極蝕刻區域216(請併參閱第4D圖)、及上述閘極蝕刻區域226(請併參閱第4D圖)，以分別形成至少一汲極通道238、至少一源極通道218、及至少一閘極通道228。舉例而言，可由源極蝕刻區域216垂直地蝕刻入介電層120直到源極層210，以形成源極通道218；相似地可由閘極蝕刻區域226垂直地蝕刻入介電層120直到閘極層220，以形成閘極通道228。另外，可由汲極蝕刻區域236垂直地蝕刻進入介電層120及基材110直到汲極層230，以形成汲極通道238。Referring to FIG. 4E, in the step, the gate etched region 236 (see also FIG. 4D), the source etched region 216 (see also FIG. 4D), and the gate etched region 226 are etched (see FIG. 4D). Please refer to FIG. 4D to form at least one drain channel 238, at least one source channel 218, and at least one gate channel 228, respectively. For example, dielectric etch region 216 may be vertically etched into dielectric layer 120 up to source layer 210 to form source channel 218; similarly, gate etch region 226 may be vertically etched into dielectric layer 120 until gate Layer 220 is formed to form gate channel 228. Additionally, the dielectric layer 120 and the substrate 110 can be etched vertically into the drain layer 230 by the drain etched regions 236 to form the drain channels 238.
請參閱第4F圖，於本步驟中，係將金屬灌注至上述汲極通道238(請併參閱第4E圖)、上述源極通道218(請併參閱第4E圖)、以及上述閘極通道228(請併參閱第4E圖)，以分別形成至少一汲極金屬柱232、至少一源極金屬柱212、及至少一閘極金屬柱222。Referring to FIG. 4F, in this step, metal is poured into the above-described drain channel 238 (please refer to FIG. 4E), the source channel 218 (please refer to FIG. 4E), and the gate channel 228 described above. (See also FIG. 4E) to form at least one drain metal pillar 232, at least one source metal pillar 212, and at least one gate metal pillar 222, respectively.
請參閱第4G圖，於本步驟中，分別形成至少一汲極焊墊234、至少一源極焊墊214、及至少一閘極焊墊224於上述汲極金屬柱232、上述源極金屬柱212、及上述閘極金屬柱222上。舉例而言，將源極焊墊214、閘極焊墊224與汲極焊墊234分別覆蓋於源極金屬柱212、閘極金屬柱222與汲極金屬柱232之上。Referring to FIG. 4G, in this step, at least one drain pad 234, at least one source pad 214, and at least one gate pad 224 are formed on the drain metal pillar 232 and the source metal pillar, respectively. 212, and the above gate metal pillar 222. For example, the source pad 214, the gate pad 224, and the drain pad 234 are respectively overlying the source metal pillar 212, the gate metal pillar 222, and the gate metal pillar 232.
請參閱第4H圖，於本步驟中，切割基材110、介電層120(請併參閱第4G圖)、汲極層230(請併參閱第4G圖)與金屬層130(請併參閱第4G圖)。舉例而言，可沿著介電層120、基材110、汲極層230、金屬層130之堆疊方向進行切割，以形成獨立的功率元件封裝結構300。Please refer to FIG. 4H. In this step, the substrate 110, the dielectric layer 120 (please refer to FIG. 4G), the drain layer 230 (please refer to FIG. 4G) and the metal layer 130 (please refer to 4G map). For example, the cutting may be performed along the stacking direction of the dielectric layer 120, the substrate 110, the drain layer 230, and the metal layer 130 to form a separate power device package structure 300.
第5圖繪示第4H圖所製成的功率元件封裝結構300之俯視圖。如圖所示，介電層120係覆蓋於功率元件封裝結構300之上表面。複數電極焊墊244係設置於介電層120上，這些電極焊墊244可包含源極焊墊214(請併參閱第4G圖)、閘極焊墊224(請併參閱第4G圖)、及汲極焊墊234(請併參閱第4G圖)，其位置與數量可分別由第4H圖所示的切割步驟中的切割區域及範圍來決定。舉例而言，當切割範圍越大，則功率元件封裝結構300所包含的電極焊墊244越多。FIG. 5 is a top plan view of the power device package structure 300 fabricated in FIG. 4H. As shown, the dielectric layer 120 covers the upper surface of the power device package structure 300. The plurality of electrode pads 244 are disposed on the dielectric layer 120. The electrode pads 244 may include a source pad 214 (please refer to FIG. 4G), a gate pad 224 (please refer to FIG. 4G), and The drain pad 234 (please refer to FIG. 4G), the position and number of which can be determined by the cutting area and range in the cutting step shown in FIG. 4H, respectively. For example, as the cutting range is larger, the power electrode package structure 300 includes more electrode pads 244.
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.
110．．．基材110. . . Substrate
112．．．第一表面112. . . First surface
114．．．第二表面114. . . Second surface
120．．．介電層120. . . Dielectric layer
130．．．金屬層130. . . Metal layer
210．．．源極層210. . . Source layer
212．．．源極金屬柱212. . . Source metal column
214．．．源極焊墊214. . . Source pad
216．．．源極蝕刻區域216. . . Source etched area
218．．．源極通道218. . . Source channel
220．．．閘極層220. . . Gate layer
222．．．閘極金屬柱222. . . Gate metal column
224．．．閘極焊墊224. . . Gate pad
226．．．閘極蝕刻區域226. . . Gate etched area
228．．．閘極通道228. . . Gate channel
230．．．汲極層230. . . Bungee layer
232．．．汲極金屬柱232. . . Bungee metal column
234．．．汲極焊墊234. . . Bungee pad
236．．．汲極蝕刻區域236. . . Bungee etched area
238．．．汲極通道238. . . Bungee channel
244．．．電極焊墊244. . . Electrode pad
300．．．功率元件封裝結構300. . . Power component package structure
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下：The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.
第1圖繪示依據本發明一實施方式之功率元件封裝結構之剖面圖。1 is a cross-sectional view showing a power device package structure according to an embodiment of the present invention.
第2圖繪示依據本發明另一實施方式之功率元件封裝結構之剖面圖。2 is a cross-sectional view showing a power device package structure according to another embodiment of the present invention.
第3圖繪示依據本發明又一實施方式之功率元件封裝結構之剖面圖。3 is a cross-sectional view showing a power device package structure according to still another embodiment of the present invention.
第4A-4H圖繪示依據本發明之一實施方式之功率元件封裝結構之製造步驟的剖面圖。4A-4H are cross-sectional views showing the steps of fabricating a power device package structure in accordance with an embodiment of the present invention.
第5圖繪示第4H圖所製成的功率元件封裝結構之俯視圖。Fig. 5 is a plan view showing the power element package structure made in Fig. 4H.
110．．．基材110. . . Substrate
112．．．第一表面112. . . First surface
114．．．第二表面114. . . Second surface
120．．．介電層120. . . Dielectric layer
130．．．金屬層130. . . Metal layer
210．．．源極層210. . . Source layer
212．．．源極金屬柱212. . . Source metal column
214．．．源極焊墊214. . . Source pad
220．．．閘極層220. . . Gate layer
222．．．閘極金屬柱222. . . Gate metal column
224．．．閘極焊墊224. . . Gate pad
230．．．汲極層230. . . Bungee layer
232．．．汲極金屬柱232. . . Bungee metal column
234．．．汲極焊墊234. . . Bungee pad
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100147114A TWI495060B (en) | 2011-12-19 | 2011-12-19 | Power component package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100147114A TWI495060B (en) | 2011-12-19 | 2011-12-19 | Power component package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201327747A TW201327747A (en) | 2013-07-01 |
| TWI495060B true TWI495060B (en) | 2015-08-01 |
Family
ID=49225196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100147114A TWI495060B (en) | 2011-12-19 | 2011-12-19 | Power component package structure |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI495060B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201103145A (en) * | 2009-05-01 | 2011-01-16 | Sumitomo Electric Industries | Transverse junction field effect transistor |
-
2011
- 2011-12-19 TW TW100147114A patent/TWI495060B/en active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201103145A (en) * | 2009-05-01 | 2011-01-16 | Sumitomo Electric Industries | Transverse junction field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201327747A (en) | 2013-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI453831B (en) | Semiconductor package and method for making the same | |
| CN102347299B (en) | Wafer level chip scale package | |
| US8642385B2 (en) | Wafer level package structure and the fabrication method thereof | |
| TWI559473B (en) | Semiconductor boundary protection sealant | |
| TWI395277B (en) | Wafer level wafer level packaging | |
| TWI524482B (en) | Chip package structure and method of manufacturing same | |
| JP2011066371A (en) | Semiconductor device and method of manufacturing the same | |
| CN105575825A (en) | Chip packaging method and packaging assembly | |
| CN107993991B (en) | Chip packaging structure and manufacturing method thereof | |
| TWI674647B (en) | Chip package array and chip package | |
| TW201247093A (en) | Semiconductor packaging method to form double side electromagnetic shielding layers and device fabricated from the same | |
| JP2012054496A (en) | Semiconductor device and semiconductor device manufacturing method | |
| CN106783748A (en) | The packaging technology and encapsulating structure of a kind of chip | |
| TWI495060B (en) | Power component package structure | |
| US20120261820A1 (en) | Assembly of stacked devices with semiconductor components | |
| US11121105B2 (en) | Semiconductor devices and methods of manufacturing semiconductor devices | |
| TWI579994B (en) | Package structure | |
| US20110012257A1 (en) | Heat spreader for semiconductor package | |
| TWI536507B (en) | Ultrathin semiconductor device and preparation method | |
| TWI473178B (en) | Wafer level package structure and preparation method thereof | |
| JP2008205292A (en) | Semiconductor device and manufacturing method thereof | |
| JP6389941B2 (en) | Semiconductor device, electronic device, and manufacturing method of semiconductor device | |
| CN103187374A (en) | Power Component Packaging Structure | |
| JP2014160851A (en) | Semiconductor device | |
| JP6211855B2 (en) | Semiconductor device |