TWI493544B - Method and device for accessing a two-way memory - Google Patents

Description

Method and device for accessing a two-way memory

The present invention relates to accessing a two-way memory device.

With the limitation of electronic memory, it is no longer able to produce the well-known density/cost/performance improvement of Moore's Law. It is possible to study the memory host technology as a well-known complementary metal oxide semiconductor (CMOS) integrated circuit memory. Alternative.

Among the memory technologies being studied is a large number of two-way memory technologies: memory that utilizes directional characteristics of materials used to program or read memory devices. That is, conventional memory devices typically incorporate one of two memory states, for example, with or without charge or with high or low voltage. In conventional memory such as these, the memory state is combined with a unidirectional feature, the presence or absence of charge (e.g., DRAM, FLASH), or a node system that maintains a high or low voltage (e.g., SRAM). For these institutions, "direction" is meaningless. Conversely, two-way memory utilizes some directional views of its memory material to store binary information. For example, a memory state can be written by flowing a current through the bidirectional memory device in one direction or by applying a voltage of one polarity, and another memory state can be caused by flowing the current through the same device or in the opposite direction. Write to the opposite polarity voltage. The programmed memory state can then be sensed by, for example, applying a voltage to the memory device to measure the current associated with the state of the memory, or by flowing a current through and measuring the voltage associated with the state of the memory.

Two-way memory types include resistive random access memory and magnetoresistive random access memory (both called RRAM), programmable metallization units, phosphorous element phase change memory, polymer memory, iron Electrical random access memory (FeRAM), ion memory device, and metal nanoparticle memory unit.

The RRAM cell can be separately programmed to a high resistance value or a low resistance value by applying an electrical pulse of opposite polarity to the cell. The high and low resistance values of the cells are used to represent two different memory states. RRAM memory is known and described, for example, in the "Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)" proposed by WW Zhuang et al. at the 2002 International Electron Devices Conference (IEDM). In the literature, the contents are incorporated herein by reference.

The programmable metallization unit uses the electrochemical control of the amount of nanoscale metal in the film of the solid electrolyte. Information is stored via electrical changes caused by oxidation of metals in the solid electrolyte and reduction of metal ions. The electrical changes can be initiated by applying a small electrical bias to a unit. The opposite bias will reverse the oxidation until the electrodeposition or plating metal is removed, thereby returning the unit to the original memory state. Programmable metallization units are known and discussed, for example, in the literature entitled "Non-Volatile Memory Based on Solid Electrolytes" by Michael N. Kozicki et al., and under the heading "Bipolar and Unipolar Resistive Switching in Cu- In the article "Doped SiO ₂ ", in Christina Schindler et al. IEEE Transactions on Electron Devices 54:2762-2768, and from IEEE Michael N. Kozicki et al. "Programmable Metallization Cell Memory Based on Ag-Ge-S and In the literature of Cu-Ge-S Solid Electrolytes, each of the documents is incorporated herein by reference.

When a sufficient portion of the bias is applied to a unit, the polymer memory exhibits electrical bi-stability, including an increase in conductivity. The unit can be returned to a low conductivity state by applying a bias of opposite polarity to the device. Polymeric memory is known and described, for example, in "Polymer Memory Device Based on Conjugated Polymer and Gold Nanoparticles" by Ankita Prakash et al., 2006, American Institute of Physics, which is incorporated herein by reference.

Ferroelectric random access memory (FeRAM) uses ferroelectric capacitors to store data. A voltage pulse of one polarity is used to program a cell into a memory state, and a voltage pulse of the opposite polarity is used to program the cell to another memory state. FeRAM is known and described, for example, in The Proceedings of the IEEE, Vol. 88, No. 5, May 2000 by Ali Sheikholeslami et al. "A Survey of Circuit Innovations in Ferroelectric Random-Access Memories" , which is incorporated herein by reference.

The bidirectional memory cells can be arranged in a rectangular array in which individual memory cells are placed at the intersection of the column and row address lines, where one line is placed on top of the other. Individual cells are accessed (i.e., read from or written thereto) via column address lines and row address lines that establish the location of uniquely defined cells in the array. Or for larger bandwidths, more than one row can be selected in parallel with a column of lines, where each row of lines has individual read and write circuits. Although individual cells can be uniquely addressed by establishing a column and row address pair, the complex memory cells share a column of address lines, and the complex cells share a row of address lines (the cells do not share column and row address lines) The complex unit can be "partially" selected by establishing a column or row address line.

That is, if, for example, the memory cell is selected by raising the voltage of its row address line and lowering the voltage of its column address line, all cells sharing the selected row address line will have their enhanced row address. The voltage of the line, and all cells sharing the selected column address line, will have their reduced column address line voltage, meaning that the unselected cells will be partially selected.

These partial selections pose a risk of inadvertent access to one or more memory cells in addition to the target memory cells. Such inadvertent access will compromise the validity of the data of the memory via an illegal read or write operation, sometimes characterized by erroneous or erroneous writes. The current leakage path can increase the risk of inadvertent access. The attendant risks associated with such partial selection, leakage paths, and negligence unit access may be substantially eliminated, for example, by using a pair of transistors at each unit location to uniquely access each memory unit. However, the addition of such selective transistors to each memory cell results in a significant loss of memory cell area. Thus, there is a high need for a method and apparatus that provides bidirectional write access to uniquely select memory cells in an array, as well as avoid inadvertent access of bidirectional memory cells without significantly increasing the area of the memory cells.

A two-way memory unit in accordance with the principles of the present invention includes, for example, a bidirectional limiting device of a bidirectional limit switch (OTS) and a bidirectional memory element. The bidirectional limiting device is in series with the memory component to isolate the bidirectional memory component from the surrounding circuitry and to avoid inadvertent access to the memory component for reading or writing. OTS in series of more than one memory device is inserted to achieve greater isolation voltage rebound or decreased, for example via the use of proximity of a lower voltage V _H, and by using more than one in series to achieve a suitable total voltage.

The two-way memory component includes a memory component that utilizes directional features of the material used to form the memory device. For example, a memory state can be written by passing a current through the bidirectional memory cell in one direction, and another memory state can be written by passing a current through the same cell in the opposite direction. Alternatively, for example, a voltage of a polarity can be applied to a memory cell to program the cell to a memory state, and a voltage of the opposite polarity can be applied to the same cell to program another memory state. The programmed memory state is then sensed, for example, by applying a voltage and sensing current or passing a current through the unit and measuring the voltage. In accordance with the principles of the present invention, a bidirectional limiting device such as OTS provides circuit isolation within a bidirectional memory unit to avoid inadvertent access by the bidirectional memory device.

In accordance with the principles of the present invention, a bidirectional memory cell comprising a bidirectional memory and an OTS can be arranged in a rectangular array wherein individual memory cells are placed at the intersection of column and row address lines. Individual cells are accessed (i.e., read from or written thereto) via column address lines and row address lines that establish the location of uniquely defined cells in the array. The arrays may include bipolar (applied in either forward or reverse direction) current and/or voltage sources for applying the current and/or voltage required to program the bidirectional cells to different memory states. A bidirectional memory array in accordance with the principles of the present invention may also include a bidirectional switch that enables access to voltages and/or currents of any polarity for each cell within the memory array. In accordance with the principles of the present invention, a bidirectional limiting device such as an OTS can be inserted in series with each bidirectional memory unit. The bidirectional limiting device (OTS) can be configured such that the bias is configured in size and sequence to ensure that no inadvertent access to unselected memory cells is permitted.

The two-way memory according to the principles of the present invention is particularly suitable for the operation of various electronic devices, including mobile phones, radio frequency identification devices (RFID), computers (portable and others), and positioning devices (such as the Global Positioning System (GPS)). Devices, particularly those that store and update location specific information, and handheld electronic devices, including personal digital assistants (PDAs) and entertainment devices such as MP3 players.

Although the present invention will be described in terms of certain preferred embodiments, it will be apparent to those skilled in the art that other embodiments, which are not intended to provide an Inside. Various structural, logical, procedural steps, chemical and electrical changes can be made without departing from the spirit and scope of the invention. The polarity and type of device and power source can be replaced in a manner that is apparent to those skilled in the art. For example, a field effect transistor (FET) can replace a bipolar junction transistor (BJT), an n-channel device can replace a p-channel device, and an npn device can replace a pnp device, each having appropriate adjustments such as supply voltage and bias voltage. Although the description of the illustrated embodiments will be provided in the OTS, other electronic bidirectional limiting devices will be considered and fall within the scope of the present invention.

For clarity and conciseness of the description, the examples in the following detailed description illustrate embodiments that can focus on two-way memory that exhibit resistance changes in response to the application of signals of opposite polarity, but methods and apparatus in accordance with the principles of the present invention are applicable. Use other attributes to distinguish one-way or two-way memory of the memory state. Accordingly, the scope of the invention is defined only by the scope of the claims.

A bidirectional memory cell selection device, i.e., a bidirectional limit switch (OTS), is suitable for use as a bidirectional limiting device for a unidirectional or bidirectional memory cell in accordance with the principles of the present invention. The OTS device utilizes the characteristics of the chalcogenide material to provide switching of electrical signals. Early work in a chalcogenide device exhibiting an electrical switching behavior in which the "OFF" resistive state is switched to the "ON" conducting state is determined by a chalcogenide material equal to or higher than the active The voltage-limited voltage is induced when applied, or when a current equal to or higher than the limiting current of the active chalcogenide material is applied. This effect is the basis of the OTS and retains important practical properties of the chalcogenide material. OTS provides regenerative switching of fast switching speeds. The basic principles and operational characteristics of the OTS are presented in the following documents, for example, in U.S. Patent Nos. 3,271,591, 5,543,737, 5,694,146, and 5,757,446, each incorporated by reference. Many journal articles include SR Ovshinsky's "Physical Review Letters" vol. 21, p. 1450-1453 (1969) "Reversible Electrical Switching Phenomena in Disordered Structures"; and SR Ovshinsky and H Fritzsche, IEEE Transactions on Electron Devices, vol. ED-20, p. 91-105 (1973) "Amorphous Semiconductors for Switching, Memory, and Imaging Applications". A three-terminal OTS device is disclosed in, for example, U.S. Patent Nos. 6,969,867 and 6,967,344, each incorporated by reference. A three terminal OTS device can be used as an alternative to a 2-terminal OTS for unidirectional or bidirectional read and/or write, which will be apparent to the art of the art (e.g., connected to the third terminal) The column line determines the power to be turned on/off, where the power source is connected to a higher voltage for writing in one direction and to a more negative power source for writing in the opposite direction.

Alloys of Group VI elements of the periodic table such as Te, S or Se are referred to as chalcogenides or chalcogenides and are advantageously used to limit the switching device.

A wide range of chalcogenide compositions has been investigated to optimize the performance characteristics of chalcogenide devices. Chalcogenide materials typically include a chalcogenide element and one or more chemical or structural modifying elements. The chalcogen element (for example, Te, Se, S) is selected from the VI row of the periodic table, and the modified element may be selected, for example, from the III row of the periodic table (for example, Ga, Al, In), and the IV row (for example, Si, Ge, Sn). ) or V lines (for example, P, As, Sb). The role of modifying elements includes providing branches or cross-linking points between chains containing chalcogen elements. The IV row modifier can act as a tetracoordination modifier comprising two coordinating sites within the chalcogenide chain and two coordinating sites that allow branching or crosslinking away from the chalcogenide chain. The III and V line modifiers act as a tricoordinate modifier comprising a coordination site within the chalcogenide chain and a coordination site that allows branching or crosslinking away from the chalcogenide chain. Embodiments in accordance with the principles of the invention may include binary, ternary, quaternary, and higher order chalcogenide alloys. Examples of chalcogenide materials are described in U.S. Patent Nos. 5,166,758, 5,296,716, 5,414,271, 5,359,205, 5,341,328, 5,536,947, 5,534,712, 5,687,112, and 5,825,046. The disclosures are hereby incorporated by reference. The chalcogenide material can also be the result of a reactive sputtering process: for example, a chalcogenide nitride or oxide, and the chalcogenide can also be modified via ion implantation or other procedures.

In the conceptual block diagram of FIG. 1, a bidirectional write memory unit 100 in accordance with the principles of the present invention includes an OTS 102 in series with a bidirectional memory element 104. The use of a one-way write memory unit will be apparent to those skilled in the art. One or more OTSs 102 are coupled to the first power source SUPPLY1 at the first terminal 106 and to the first terminal 110 of the bidirectional memory device 104 at the second terminal 108. Bidirectional here refers to the writing of memory components; however, some memories can also be read in either direction. The bidirectional memory element is coupled to the second power source SUPPLY2 via the second terminal 112.

In accordance with the principles of the present invention, power supplies SUPPLY1 and SUPPLY2 can be coupled to respective terminals of memory unit 100 via and under the control of circuitry, such as decoding circuitry, which will be described in greater detail in the related discussion of Figures 2 and 3. The power supplies SUPPLY1 and SUPPLY2 can be configured as current or voltage supplies and can include both current and voltage supplies.

In addition, to meet the needs of the bidirectional memory component 104, each of the power supplies SUPPLY1 and SUPPLY2 is bidirectional. That is, each power source can be a "positive" or "negative" voltage (polarity is a matter of conventional interest), or each power source can, for example, provide or receive current. In various embodiments, the two-way view of the power supply can be implemented by switching various positive elements (eg, corresponding to a positive voltage or current supply) and negative elements (eg, corresponding to a negative voltage or a receiving current) into or out of the power supply circuit.

The conceptual block diagram of Figure 2 provides an overview of a bidirectional array in accordance with the principles of the present invention. The array can be used, for example, as a memory array embedded in a memory circuit, or as a field programmable array, using techniques known to those skilled in the art. The bidirectional memory array 200 includes a plurality of bidirectional memory cells 202 configured in a cross-point array. As described in the related discussion of FIG. 1, each unit 202 includes a bidirectional memory element and an OTS in series. The two power supplies SUPPLY1 and SUPPLY2 are configured to provide positive and negative voltages and/or currents to selected cells 202 within array 200. As will be described in more detail in the related discussion of FIG. 3, one or both of the power supplies SUPPLY1 and SUPPLY2 may include portions directed to a particular memory job. For example, the power supply can include a particular current source that is set to a different level for reading and writing from the memory unit to the memory unit. Selection circuits 201 and 203 operate to select between different polarity power supplies individually provided by power supplies SUPPLY1 and SUPPLY2.

In accordance with the principles of the present invention, selection circuits 201 and 203 typically select power supplies of opposite polarity during any particular access operation (READ job, WRITE 0 job, or WRITE 1 job). That is, for example, during the WRITE 1 operation, the selection circuit 203 can select the positive power supply while the selection circuit 201 selects the negative power supply to cause current to flow through the memory unit to the selected memory in a direction suitable for writing logic "1". unit. During WRITE 0 operation, selection circuit 203 can then select a negative supply while selection circuit 201 selects a positive supply, thereby providing current through the selected memory cell in the opposite direction required for WRITE 1 operation. Selection circuits 201 and 203 select their selection based on the input signals including the following signals: ADDRESS, READ, WRITE 0, and WRITE 1 signals. Bidirectional switches such as switches 204, 206, 208, and 210 are included in the illustrative embodiment selection circuit. Bidirectional switches 204, 206, 208, and 210 are used to select a column and row line combination for selecting individual memory cells within array 200. The bidirectional open relationship is used to adapt the bidirectional characteristics of the memory elements within the memory unit 202.

3 is a schematic diagram showing a more detailed view of an illustrative embodiment of a two-way memory array in accordance with the principles of the present invention. In the illustrated embodiment, as described above, the cross-point memory array 300 includes two-way memory cells selected via the establishment of columns and row lines (eg, cells 2, 2 are asserted via row 2 and column 2 lines). select). In the illustrated embodiment, SUPPLY1 includes READ, WRITE 1, and WRITE 0 circuits. The READ circuit includes a pair of series p-channel FETs 302 and 304 connected to the positive supply voltage V+ at source 302 and to the common supply output through the drain of FET 304, which is selectively coupled to all of the supply. The line of the array 300. In the illustrated embodiment, the gate of p-channel FET 304 is controlled by a regulated voltage signal VREGP generated by a lash adjuster that supplies a stable temperature compensated control voltage to p-channel FET 304. The gate of p-channel FET 302 is controlled by a READ signal. When the READ signal is low relative to the supply voltage V+, a low resistance path is established between the drain of the p-channel FET 304 and the supply voltage V+. Whenever the READ signal activates p-channel FET 302 in this manner, the current flowing through FET 304 is controlled by the voltage VREGP of the gate of FET 304.

Similarly, the WRITE 1 circuit includes a pair of series p-channel FETs 306 and 308 connected to one of the positive supply voltages V+ and connected to the common supply output through the drain of the FET 308 and selectively coupled at the other end. To all lines of power to the array 300.

In the illustrated embodiment, the gate of p-channel FET 308 is controlled by a regulated voltage signal VREGP generated by a lash adjuster that supplies a stable temperature compensated control voltage to p-channel FET 308. The gate of p-channel FET 306 is controlled by the WRITE 1 signal. When the WRITE 1 signal is low relative to the supply voltage V+, a low resistance path is established between the drain of the p-channel FET 308 and the supply voltage V+. Whenever the WRITE 1 signal activates the p-channel FET 306 in this manner, the current flowing through the FET 308 is controlled by the voltage of the gate of the FET 308, VREGP. Since the current requirements for READ and WRITE 1 operations can be different (for example, the current required to write a memory device to a low resistance state can be greater than the current required to read the same memory device), the p-channel FET used to generate the write pulse 308 may be larger than p-channel FET 304 for generating a READ pulse, thereby providing a larger current at the same gate voltage VREGP.

In the illustrated embodiment, the WRITE 0 job is of opposite polarity to the READ and WRITE 1 jobs. That is, in this example, the READ current polarity can be the same as WRITE 1. Then, to read the contents of one of the memory cells in the array 300, or to write a logic "1" to the cell, the current flows in one direction, and to write a logic "0" to the cell, the current is Flow in the opposite direction. In the present embodiment, the WRITE 0 circuit includes a pair of series n-channel FETs 310 and 312 that are connected at one end to the negative supply voltage V- through the source of FET 310 and at the other end through the drain of FET 312. Connected to a common power supply node, which is selectively coupled to the row selected from array 300, thereby coupling the opposite polarity current to the selected memory cell for WRITE 0.

The gate of n-channel FET 312 is controlled by a regulated voltage signal VREGN generated by a lash adjuster that supplies a stable temperature compensated control voltage to n-channel FET 312. The gate of n-channel FET 310 is controlled by the WRITE 0 signal. When WRITE 0 is high relative to the supply voltage V-, a low resistance path is established between the source of the n-channel FET 312 and the supply voltage V-. Whenever the WRITE 0 signal activates the n-channel FET 310 in this manner, the magnitude of the current flowing through the FET 312 is controlled by the voltage VREGN applied to the gate of the FET 312.

As previously mentioned, in the illustrated embodiment, the outputs of the READ, WRITE 1, and WRITE 0 circuits may be tied to a common node of the line lines; or more than one set may individually drive one or a subset of the line lines (so more than one The line of travel is parallel, thus improving the bandwidth). In addition to determining the functions to be implemented and the selection of power supplies implemented via control signals such as READ, WRITE 1 and WRITE 0, each row of lines may have a control input that is governed by the address decoding circuitry. That is, the line circuit is selected by the decoded signal input provided by the decoder driven by the address line. In the illustrated embodiment of FIG. 3, decoding circuit 314 receives address line ADDRESS and generates row select control signals CS1, CS2, ..., CSn based on the address signals appearing on address line ADDRESS. The row select signals CS1, CS2, ..., CSn control the respective bidirectional switches BISW1, BISW2, ..., BISWn providing access to the respective row lines. In this manner, the READ, WRITE 1, and WRITE 0 signals determine the magnitude and polarity of the access signal, and the address line ADDRESS determines that the access signal will be received.

In the illustrated embodiment, the bidirectional switches BISW1, BISW2, ..., BISWn are completed as CMOS analog switches. CMOS analog switches are known in the art. Due to the use of p-channel and n-channel FETs, CMOS analog switches provide a very low-resistance signal path regardless of the polarity or voltage across the signal. That is, when "on", the p-channel and n-channel devices are complementary to each other such that as the resistance of the n-channel device increases due to variations in the signal voltage across the device, the resistance of the p-channel device decreases. vice versa. Based on lower performance and limited voltage ranges, a single n- or p-channel device can be used in place of the illustrated parallel p-channel and n-channel devices.

One or more sense amplifiers SENSEAMP can be coupled to a common node of the line lines. Under the control of signals including READ and CLOCK signals. The sense amplifier SENSEAMP senses and adapts the contents of the accessed memory cells during a read operation. The output from the sense amplifier SENSEAMP can be temporarily stored, for example, in the buffer BUFFER. Other sense amplifier configurations are contemplated within the scope of the present invention.

In the illustrated embodiment, each column of lines is connected to p-channel FETs 316, 328 that respectively couple column lines to positive or negative supplies, depending on whether each column is selected or whether a READ, WRITE 0 or WRITE 1 job will be performed. , 332 and n-channel FETs 318, 330, 334. Based on the n-channel FETs 330, 334 and the p-channel FETs 328, 332 are turned off, the columns of the lines can be "floating". In accordance with the principles of the present invention, the column lines can be precharged to a voltage of, for example, V+/2. In the illustrated embodiment, the column and row lines are coupled through the n-channel FET to V+/2 under the control of the signal PRECHARGE. Furthermore, the column voltage can be forced to an intermediate voltage, such as V+/2, when it is not selected.

In an illustrative embodiment, when not selected, a further driver can be attached to each column and row to be V/2. The drivers can be N-FETs with a drain to a voltage of, for example, V/2 (V+ + V-/2), with a source to column (or row). When the column (or row) is not selected, the gate is extremely high and can be controlled from the decoder.

In the illustrated embodiment, decoding circuit 314 receives signals including: ADDRESS, DATA, READ, WRITE, CLOCK, and ENABLE. Decoding circuit 314 uses the signals to develop control signals including: READ, WRITE 0, WRITE 1, PRECHARGE, RP1 ... RPn, RN1 ... RNn and CS1 ... CSn, which are assigned to the array as previously described And use it. That is, for example, the signal RP1-n controls the gate of the p-channel FET to be coupled to the gate of the n-channel FET controlled by the signal RN1-n, and the column select signal ROW1-n is developed. The signal CS1-n controls the analog line selection signal COL1-n analogy through multiple switches. The PRECHARGE signal controls the n-channel FETs in series, passing the column and row lines to the precharge voltage (V/2 in the illustrated embodiment) through the terminals PRECOL1-n and PREROW1-n.

The bidirectional characteristics of the read and write operations in the embodiment of the present description can be more understood through the use of examples. In the illustrated embodiment, decoder 314 interprets WRITE, ADDRESS, and DATA signals to write "1" to memory cell CELL 1,1 (ie, uniquely addressed by establishing a combination of column 1 and row 1) When the memory unit is commanded, the WRITE 1 signal is asserted (WRITE 1 is driven "low" relative to V+), and CS1 (driven to "low" relative to V+) is established to allow WRITE 1 to be developed. The pulse (commonly referred to herein as a "positive" pulse) is applied from V+ to the line COL1 by appropriate writing. In addition, the ROW1 signal is asserted (for WRITE 1 operations, ROW1 is driven "low" to V-) by driving RN1 and RP1 to "high". On the other hand, to write "0" to the memory cell CELL 1,1, the WRITE 0 signal is asserted (WRITE 0 is driven "high" with respect to V-), and CS1 is asserted (driven relative to V+ is "low") to allow the negative pulse developed by WRITE 0 to pass to line COL1 and establish the ROW1 signal. That is, for the WRITE 0 job, ROW1 is driven to "high" to V+ by driving RN1 and RP1 to "low".

4A-4D are timing diagrams depicting access procedures (i.e., read, write logic "1", and write logic "0") of a bidirectional memory cell in accordance with the principles of the present invention. In the illustrated embodiment, the bidirectional characteristic of the memory cell is shown in the requirement to write a logic "1" using a positive current pulse (such as the "positive" and "negative" system idioms described above), resulting in an extremely high resistance value. And a negative current pulse is used to write a logic "0", resulting in an extremely low resistance value. The read operation also uses a positive current pulse, but may be a negative current pulse depending on the memory technology of the OTS selection device used in the unit of the example circuit described herein and its orientation.

As described in relation to the discussion of FIG. 3, and as represented in the timing diagrams of FIGS. 4A-4D, the column and row select signals are maintained at an intermediate voltage when the associated memory cells are not accessed (in this illustrative embodiment) Medium V/2) to further ensure inadvertent access to prevent units within array 300. That is, when there is no cell on a particular column, ROWn is selected, and each column decoding output RPn and RNn may be "OFF" (as in the state of each of its p-channel FET 316 and n-channel FET 318), and the corresponding column line ROWn may be left to the left, for example via V/2 of the precharge circuit, as described in more detail with respect to Figure 3 (eg, RPn, RNn, and CSn are off, allowing column and row lines to pass precharge circuits that generate PRECOLn and PREROWn) And, for example, during the precharge period of the termination period, the column and row lines are driven to V/2). Maintaining the column and row lines at intermediate voltages also limits the amount of voltage swing during operation, allowing for faster, reduced noise handling and current leakage - thereby reducing power loss, and in portable applications, the device is Operating time between charges. In addition, based on the fact that the columns and rows are at equal voltages, the leakage between the (unselected) columns and rows is reduced, further improving battery life. In another illustrative embodiment, the unselected column may be at V/3 (when writing 0) or 2V/3 (when reading or writing 1), thereby creating margin improvements to prevent erroneous selection.

The timing diagram of Figure 4A depicts a read operation in accordance with the principles of the present invention in which the read bidirectional memory cells (e.g., CELL 1, 1) are in a high resistance, logic "0", RESET (reset) state.

At time t0, column one select signal ROW1 and row one select signal COL1, such as all column and row signals in array 300, are at "precharge" voltage V/2. In the illustrated example, the read program drives the row line COL1 associated with the memory cell CELL 1,1 high (toward V+ with current source) and will be associated with the memory cell CELL 1,1 at time t1. The line ROW1 is driven low (to 0V) to start. In the illustrated embodiment, the line line COL1 is charged to a positive voltage via the current pulse generated by the assertion READ signal and the analog switch control signal CS1 at time t0. That is, the memory cells CELL 1,1 in the array 300 are accessed at time t1 by establishing column one and row one select signals ROW1 and COL1, respectively.

As described in more detail in the discussion of FIG. 3, in the illustrated embodiment, the read signal READ is asserted by driving the gate of the p-channel FET 302 to a very "low" voltage (0V in the illustrated example), thereby providing a positive pulse. (The amount is adjusted by VREGP) is provided to the line access circuit. The resulting pulses are then limited (i.e., allowed to pass (or block)) to the appropriate row by activating (or not activating) a corresponding bidirectional switch (e.g., switch 208). In the illustrated example, the bidirectional switch control signal CS1 is asserted by driving the signal to a "low" voltage V-.

In the illustrated embodiment, row select signal COL1 is thus a current pulse (generated via activation of READ p-channel FET 302) which allows passage of bidirectional analog switch 208 to all of the memory cells in row 1 of array 300. The line of the line entered. As described in more detail in relation to the discussion of FIG. 3, column select signal ROW1 is generated via address decode circuit 314, which generates the columns using ADDRESS, READ, WRITE, and DATA inputs (RP1 and RN1). )control signal. In the illustrated embodiment, since the polarity or bidirectional characteristic of the memory cell is displayed by driving the current flowing through the device in the opposite direction to write "1" or "0", the decoded column outputs RPn and RNn, to generate a column control signal ROWn, which is used to receive or provide current depending on the type of access (READ, WRITE 0 or WRITE 1) that will be performed.

Next, at time T1, column line ROW1 is driven low to V- (0V in the illustrated embodiment) by driving RN1 high, and thereby initiates n-channel FET RN1 (RP1 is still high and p-channel FET 316 "OFF"); the line line COL1 is precharged by driving the read signal low (starting the p-channel FET 302) and driving CS1 low to initiate the current pulse generated by the bidirectional analog switch 208. In the illustrated embodiment, the n-channel FET (e.g., n-channel FET 318) for driving the column lines to be low is characterized by a low on-resistance (Ron) and thus can quickly drive the column lines to 0V. On the other hand, the line circuit is charged via a current source having an amplitude determined by the gate voltage VREGP, and thus the charging of the line line COLn is gradually greater than that indicated by the gradual upward and sharp downward curves of FIG. 4A, respectively. The discharge of the column line ROWn. In the illustrated embodiment, the size of the p-channel FET 304 is selected to ensure that the current flowing through does not interfere with the memory state of any of the memory cells in the array 300 during the READ operation based on the applied gate voltage VREGP. As will be apparent to those skilled in the art, a voltage source will enable memory cell technology to be better read (or written), and (with voltage compliance) read or write current sources may be (with current compliance) Voltage or internal resistance).

The voltage Vcell across the memory cell CELL 1,1 is the difference between the row and column voltages. As in this example, if the memory component is in a high resistance state, the voltage applied to the memory cell Vcell will be distributed across the serial OTS 102 and the bidirectional memory through a combination of current limited charging of the "ground" column line ROW1 and the row line COL1. Element 104. For the first approximation, the voltage distribution will be proportional to the resistance of the OTS 102 and the memory component 104. If their resistances are equal, the voltages will be equally distributed; if, for example, one of the devices (OTS or memory components) exhibits one-third of the total series resistance, it will face one-third of the voltage. In the illustrated embodiment, based on the memory in the high resistance state, the ratio of the peak read voltage facing the OTS (at the arrival time t2) is insufficient to trigger the OTS. According to the principle of the present invention, parameters such as a peak read voltage, a relative resistance of the memory element and the OTS, and an OTS limit voltage are selected such that if the unit is in its low resistance state, the OTS is triggered during the READ operation period t2, but if The unit is in its high resistance state (for example, 2/3 (peak READ) is greater than or equal to the limit voltage of OTS, but the smaller amount 1/2 (peak READ) is less than the limit voltage of OTS), OTS does not Triggered during a READ job. When the OTS is triggered, the voltage on the line drops to a lower voltage and the memory is in a low resistance state (having a low voltage across the OTS). If the transition of the OTS is excessive for the required threshold voltage V _TH necessary for the memory, the transition is reduced while maintaining a higher V _TH by using one or more OTSs in series (each having a lower V _TH ). For example, thinner OTSs are stacked in series. Adjustments to the limits and transition voltages are discussed, for example, in U.S. Patent No. 7,280,390, the disclosure of which is incorporated herein by reference.

At time t3, the read output is latched. The delay between t2 and t3 provides processing time for the output sense amplifier to be accessed and for the voltage of the row of selected cells (eg, if the memory component is in a low resistance state, the OTS has time to trigger and line the line) Pull down to the level that will be recognized as the low resistance state, ie "SET (SET)" or logic "1" state). In the illustrated embodiment, the forward edge of the READ signal can be used to latch the time (t3) to be valid. As depicted by the trace of the mark DATA OUT, the output data is undefined until t3 (hatched portion), at which time DATA OUT is valid (logic "0" in the illustrated embodiment), and the rising edge latch of the READ signal Lock the valid output. In the illustrated embodiment, the input DATA IN is undefined, as indicated by the slanted line, and may be on a signal line separated from the DATA OUT.

The timing diagram of Figure 4B depicts a read operation in accordance with the principles of the present invention in which the read bidirectional memory cells (CELL 1, 1) are in a low resistance, logic "1", SET state.

At time t0, column one select signal ROW1 and row one select signal COL1, such as all column and row signals in array 300, are at "precharge" voltage V/2. As described in more detail above, at time t1, by driving RN1 high and thereby turning on n-channel FET RN1 (RP1 remains high and p-channel FET 316 "off"), column line ROW1 is driven to 0V; row line COL1 is The precharge is initiated by driving the READ signal low (starting p-channel FET 302) and turning CS1 low to turn on the current pulse generated by bidirectional analog switch 208. Adjusting the current through the p-channel FET 304 based on the applied gate voltage VREGP to avoid interfering with the memory state of the selected memory cell within the array 300 during READ operation; if necessary, excessive voltage or current flows into the memory cell After the memory is reliably read and the appropriate signal is developed, the shutdown pulse is applied and the read cycle is stopped.

The voltage Vcell across the memory cell CELL 1,1 is the difference between the row and column voltages. The voltage applied to the memory cell Vcell by the combination of current limited charging of the "ground" column line ROW1 and the row line COL1 will be distributed across the series OTS 102 and the bidirectional memory element 104. In the illustrated embodiment, memory element 104 exhibits low resistance and most of the voltage Vcell drops across OTS 102. At time t2, the voltage across OTS 102 reaches the threshold voltage of OTS 102, and the OTS responds to ground (ie, enters a low resistance state). Since the OTS 102 and the memory component 104 are now in a low resistance state, the voltage Vcell across the memory cell drops, as indicated by the Vcell trace in Figure 4B.

In the illustrated embodiment, the on-resistance of the p-channel FET supplying current to the row line COL1 is greater than the on-resistance of the n-channel FET of the discharge column line ROW1, and therefore, the line line voltage COL1 is decreased, and the column line voltage is substantially maintained at 0V. . The voltage Vcell across the e-memory cell drops approximately to about the sum of the OTS hold voltage ( _VH ) of about 1 V and the resistance of the memory cell and the current flowing therethrough, as depicted by the trace of the mark Vcell in Figure 4B. The lower voltage can be sensed at time t3 and properly interpreted as a low resistance, "SET", "1" state. As previously mentioned, the design parameters can be adjusted such that the OTS triggers when the memory component is in a low resistance state and the OTS is not triggered when the memory component is in a high resistance state. On the other hand, OTS is triggered for any memory state based on a relatively high voltage for a relatively high resistance memory. At time t3, the read output is latched as described in more detail in the discussion of Figure 4A.

The timing diagram of Figure 4C depicts the sequence of writing a "1" (low resistance) "SET" operation in accordance with the principles of the present invention. In the illustrated embodiment, the programmable memory cell is in a low resistance state (ie, writing a logic "1" to the memory) is accomplished by flowing a current through the memory cell in the same direction, as described above. Forced to flow through a unit. As described above, a pulse generating circuit for programming a cell in a low resistance state, for example, can use more current for reading the cell.

At time t0, column one select signal ROW1 and row one select signal COL1 are both at "precharge" voltage V/2. On the other hand, the V/3 method can be used to improve the write margin. In the illustrated example, the WRITE 1 program drives the row line COL1 associated with the memory cell CELL 1,1 to be high (toward V+) and the column associated with the memory cell CELL 1,1 via time t1. The ROW1 driver is enabled low (to 0V). In the illustrated embodiment, the line line COL1 is charged to a positive voltage via the current pulse generated by the assertion of the WRITE 1 signal and the analog switch control signal CS1 at time t1.

As indicated by the trace of mark COL1, the selected memory cell CELL 1,1 line begins to charge to a positive voltage above V/2. At the same time, the column line represented by the trace of the mark ROW1 is quickly discharged from V/2 to 0V. The memory cell voltage represented by the trace of the mark Vcell is the difference between the row and column voltages.

If the memory element 104 is already in a low resistance state, most of the cell voltage Vcell will fall across the OTS 102. As a result, the OTS will be triggered with very low cell voltages, as indicated by the dashed traces of the labeled LowR in the COL1 and Vcell plots. On the other hand, if the memory device 104 is in a high resistance state, the cell voltage Vcell will be distributed across the series combination of the OTS 102 and the memory device 104 depending on the relative resistance of the OTS 102 and the memory device 104, and the OTS 102 will be higher. The cell voltage is triggered, as indicated by the dashed trace of the mark high-R in the COL1 and Vcell traces. In both cases, where the existing state of the memory cell is low resistance and the existing state of the memory cell is high resistance, the OTS 102 is triggered and sufficient current is transferred to the memory component 104 to be used after the OTS trigger Program control is a logic "1" low resistance state.

The timing diagram of Figure 4D depicts a sequence of writing a "0" (high resistance) "reset" job in accordance with the principles of the present invention. In the illustrated embodiment, the program-controlled memory cell is in a high-resistance state (ie, writing a logic "0" to the memory) by completing the current flowing through the memory cell in the opposite direction, as described above. "The current is forced to flow through a unit.

At time t0, column one select signal ROW1 and row one select signal COL1 are both at "precharge" voltage V/2. In the illustrated example, the WRITE 0 program drives the line COL1 associated with the memory cell CELL 1,1 to be low (toward V-, eg, 0V) and to the memory cell CELL 1,1 via time t1. The associated column ROW1 is driven high (to V+) to start. This bias meter generates current to pass through the memory element 104 in the opposite direction as used in the READ or WRITE 1 operation. In the illustrated embodiment, row line COL1 is discharged from V/2 to 0V by establishing a WRITE 0 signal and a current pulse generated by analog switch control signal CS1 at time t1. The signal RP1 is asserted (driven low) at time t1, while current is supplied from the V+ supply through p-channel transistor 316 through memory element 104. Signal RN1 remains "low", so n-channel FET 318 remains "off."

As indicated in the trace of the mark COL1, the row line of the selected memory cell CELL 1,1 is discharged from V/2 toward 0V. At the same time, the line represented by the trace of the mark ROW1 is quickly charged from V/2 toward V+. The memory cell voltage represented by the trace of the mark Vcell is the difference between the row and column voltages. If the memory element 104 is already in a low resistance state, most of the cell voltage Vcell will fall across the OTS 102. As a result, the OTS will be triggered with very low cell voltages, as indicated by the dashed traces of the labeled LowR in the COL1 and Vcell plots. On the other hand, if the memory component 104 is in a high resistance state, as previously described, the cell voltage Vcell will be distributed across the series combination of the OTS 102 and the memory component 104 depending on the relative resistance of the OTS 102 and the memory component 104, and As indicated by the dashed traces marked high-R in the COL1 and Vcell traces, the OTS 102 will trigger at a higher cell voltage. In both cases, where the existing state of the memory cell is low resistance and the existing state of the memory cell is high resistance, the OTS 102 is triggered and sufficient current is transferred to the memory component 104 to be used after the OTS trigger Program control is logic "0" high resistance state.

As previously discussed, various parameters such as the amount of OTS trigger voltage can be adjusted to suit the needs of a particular memory technology. For example, the read and write voltages associated with ion memory cells are extremely low, typically below 1V. The OTS device used as an isolation device in the array of ion memory cells can be adapted to be triggered, for example, at 2V.

Referring to FIG. 5, unit 500 can be coupled to device 556 and conductive word line 552 of element 558 to form on substrate 536. The interlayer dielectric 548 can separate the integrated circuit component 546 from the bidirectional memory 550. Component 546 can include any of a variety of components, such as a logic gate, a microprocessor, or a memory.

In the illustrated embodiment, selection device 556 is an OTS formed from a non-programmable chalcogenide material. The OTS includes a top electrode 571, a chalcogenide material 572, and a bottom electrode 570. The selection device 556 can be permanently in an amorphous state in one embodiment. Although the depiction device 556 is depicted on the bi-directional memory component 558 in one embodiment, the opposite orientation can also be used. A typical OTS with a symmetrical electrode is quite symmetrical. It can be adjusted, for example, by changing the electrodes. For better durability, one or two tungsten electrodes can be used as the heat sink.

As previously mentioned, the bidirectional memory element 558 can assume a set or reset state. In one embodiment of the invention, the bidirectional memory component 558 can include an insulator 562, a bidirectional memory material 564, a top electrode 566, and a barrier film 568. In an embodiment of the invention, the lower electrode 560 can be defined within the insulator 562.

The bi-directional material 564 can be a bi-directional material suitable for non-volatile memory data storage characterized by two states. As previously mentioned, the material can be programmed to a state via application of a voltage or current in one direction, and programmed to another state via application of a voltage or current in the opposite direction. The memory can be read via a similar voltage or current signal or a smaller amount, for example, as one of the write signals in the same direction.

Programmization of the memory material to change the state of the material can be accomplished by applying a voltage potential to lines 552 and 554 to create a voltage potential across memory material 564. Current can flow through a portion of the memory material 564 in response to the applied voltage potential.

In an illustrative embodiment, a voltage potential difference of about 0.5 to 1.5 volts may be applied across a portion of the memory material via application of about 0 volts to line 552 and supply of about 0.5 to 3.0 volts to upper line 554. The current flowing through the memory material 564 in response to the applied voltage potential can be used to read or change the state of the material.

The information stored in the memory material 564 can be read, for example, by measuring the resistance of the memory material. For example, the read current can be supplied to the memory material using lines 554, 552, and the final read voltage across the memory material can be compared to the reference voltage using, for example, a sense amplifier. The read voltage can be proportional to the resistance exhibited by the memory storage element.

To select the cell 550 defined by the intersection of row 554 and column 552, the OTS 556 of the selected cell 550 can be triggered to provide bidirectional access. When activated, the selection device 556 allows current to flow through the memory element 558 in a direction determined by the biasing unit 550 and achieves a READ, WRITE 0 or WRITE 1 job.

In some embodiments, when a low voltage is applied across the OTS device 556, the OTS device 556 is turned off and exhibits a very high resistance. This is true regardless of the direction of the applied electric field. The biasing resistance may be in the range of, for example, 10 ⁵ ohms to more than 10 ⁹ ohms with a bias voltage of half the limiting voltage. The OTS device features, such as the thresholding of the chalcogenide material 572, the thickness adjustment of the chalcogenide material 572, or the "stacking" of the OTS device, such as a threshold voltage, may be suitable for individual applications.

The OTS device 556 can maintain its off state until the threshold voltage _VTH or the limiting current I _TH switches the OTS device 556 to a conducting, low resistance open state. In one illustrative embodiment, the voltage across the device 556 is to the dynamic resistance to a lower voltage or after turning, called the holding voltage V _H, as long as sufficient supply current I _H to the apparatus, it remains V _H. Given threshold voltage V _TH and the difference between the holding voltage V _H collectively as "transition (the snapback)" corresponding region voltage, and the current / voltage graph is called the transition region. Based on the low V _TH , the transition can be zero.

In operation, the access signal applied to the memory unit 500 in accordance with the principles of the present invention does not instantaneously convert the cell voltage. That is, during the time period of the memory access operation, the access signal gradually accesses the voltage charging unit 500 and the associated column and row lines toward the target. During the charging process, a portion of the voltage across cell 500 increases across OTS device 556. With the increase of the voltage administration unit 500, the voltage across the OTS device 556 will reach the predetermined threshold voltage OTS device 556, the OTS device 556 triggers at this time and becomes highly conductive, with a transition to a low dynamic resistance of V _H, for example less than 1000 ohms (depending on electrode selection and resistance).

For the first approximation, the ratio of the cell voltage falling across the OTS 556 during the charging process is determined by the ratio of the resistance of the OTS 556 to the resistance of the memory element 558 in the "off" state, which can be varied by changing each Change across voltage. As previously mentioned, the "OFF" resistance of the OTS 556 ranges up to ¹⁰⁹ ohms or higher. As a result, the analysis generally assumes that as long as the OTS 556 remains off, only a small portion of the cell voltage is applied across the memory element 558, most of the donor unit The voltage of 500 drops across the OTS 556.

Moreover, for the first approximation, the analysis typically assumes that once the OTS device 556 triggers, the voltage across the OTS device 556 remains substantially at the device's holding voltage _VH , and the remaining cell voltage (Vcell- _VH ) drops across Memory element 558. As before, the minimum current I _H must remain through the OTS so that the voltage drops across the OTS device 556 and remains at the hold voltage V _H . The current through the OTS 556 should be limited (eg, via the resistance of the memory element 558) to a value below the holding current _IH , and the OTS device 556 will remain in the "OFF" state with a voltage drop greater than _VH and less than _VTH , rather than Approximately equal to V _H .

As a result, if the memory element 558 is in a high resistance state and it exhibits a resistance in the high resistance state that limits the current in series with the memory element 558 through the OTS 556 to a lower current than the holding current I _H of the OTS device 556, the OTS device 556 will remain OFF and the voltage across the OTS device 556 will remain at or below the device's threshold voltage V _THOTS . The voltage across the memory device will be the difference between the cell voltage and the OTS voltage: Vcell-V _OTS .

On the other hand, if the memory device is in a high resistance state and it exhibits a sufficiently low resistance in the high resistance state to allow the limiting current I _{TH to} flow and the voltage across the OTS exceeds V _TH , the OTS 556 will start and cross the OTS 556 The voltage will drop to the holding voltage of the device, approximately V _H , or more accurately: V _H +Ixdv/di (V _H + current through the device multiplied by the dynamic resistance in the triggered state). The remaining amount of cell voltage will drop across memory element 558.

Similarly, if the memory element 558 is in its low resistance state, but the low resistance state exhibits a resistance that limits the current in series with the memory element 558 through the OTS 556 to a lower limit current ITH _H than the OTS device 556, the OTS device 556 will The voltage that remains OFF and across the OTS device 556 will remain below or at the device's threshold voltage V _THOTS . The voltage across the memory device will be the difference between the cell voltage and the OTS voltage: Vcell-V _THOTS . If the memory element 558 is in its low resistance state and it exhibits a sufficiently low resistance in the low resistance state to allow the limiting current I _{TH to} flow, the OTS 556 will start and the voltage across the OTS 556 will drop to the holding voltage of the device V _H And the remaining amount of cell voltage will drop across memory element 558. The OTS will remain activated unless the current through the device drops below its holding current I _H .

If the OTS device 556 exhibits a turning point (ie, V _TH >V _H ), and the resistance of the memory element 558 is insufficient to allow the OTS device 556 to be free from the limit, in the activated state, after passing through the turning region, the passing device The current increases until a very high current level, and the voltage drop of the OTS device 556 remains close to the hold voltage. Above the threshold current level, the device triggers the start and as long as the holding current flows, the device remains activated and displays a very low, finite differential resistance, the voltage drop increases with increasing current, and is projected to remain The cutoff zero current of the voltage V _H . The OTS device 556 can remain activated until the current through the OTS device 556 drops below a characteristic retention current value that is dependent on the size and material used to form the OTS device 556.

In some embodiments of the invention, the OTS device 556 does not change phase. It is still permanently amorphous and its current-voltage characteristics can maintain the same general shape and characteristics throughout the life of the job. For example, in one embodiment, the holding current can be about 0.1 to 100 microamperes for a 0.5 micron diameter device 556 composed of TeAsGeSSe having a ratio of atoms of 16/13/15/1/55. Below this holding current, device 556 is turned off and returns to a high resistance state with a low voltage, low electric field. The limiting current of device 556 is typically about the same as the holding current. The holding current can be varied by changing the program variables, such as the top and bottom electrode materials and the chalcogenide material. Device 556 can provide a high "starting current density" for a particular region of the device as compared to conventional access devices such as metal oxide semiconductor field effect transistors or bipolar junction transistors.

In some embodiments, the higher current density of the "on" state of the OTS device 556 allows the memory element 558 to have a variable higher program current. The memory component 558 is a bidirectional memory, which enables the use of a large program-controlled current bidirectional memory device, which reduces the need to allocate more wafer regions to the configuration unit region, and has considerable cost savings and improved memory. Performance potential.

A technique for addressing a bidirectional memory array using a voltage V applied to a selected row and a zero voltage applied to the selected column. For the condition that component 558 is a bidirectional memory, the selected voltage V is greater than the maximum threshold voltage of access device 556 plus memory component 558 resets the maximum threshold voltage, but less than twice the maximum threshold voltage of device 556. In other words, the maximum threshold voltage of all devices 556 plus the maximum reset limit voltage of component 558 within the array can be less than V to ensure that all cells are selectable and programmable. And in some embodiments, V can be less than twice the minimum threshold voltage of device 556 (plus the minimum memory cell component voltage during the limited OTS period) to help ensure that the wrong selection of unselected memory cells is avoided. . As previously mentioned, all unselected columns and rows can be biased by V/2. By this method, there is no bias between the unselected column and the unselected row. This reduces the background leakage current.

After biasing the array in this manner, memory element 558 can be programmed and read via the devices required by any particular memory technology. The resistance of element 558 can be determined, for example, by driving a current required to program the bidirectional memory element to program a memory element 558 using a bidirectional material, or by driving a lower current readable memory array.

A bidirectional memory array in accordance with the principles of the present invention can use surrounding conductive traces to interconnect memory components and bias voltages to connect conductive traces and line segments disposed in different layers of the bidirectional memory array. In addition, the memory arrays can use "shared" address lines. The use of address lines and the use of surrounding interconnects are known in the art and are disclosed, for example, in the publication No. 2006/0120136 and the application No. 11/202,428, entitled "Shared Address Lines For Crosspoint Memory". It is disclosed in the application, which is incorporated herein by reference.

Bidirectional memory arrays in accordance with the principles of the present invention may also be stacked on top of one another in each layer. The stacking of such memory devices is known in the art and is disclosed, for example, in the U.S. Patent No. 6,795,338, the disclosure of which is incorporated herein by reference.

The two-way memory device described in the discussion of the previous figures can be used for a particular advantage of a wide variety of systems. The schematic of Figure 6 will be used to depict the use of a device in a few such systems. The schematic of Figure 6 includes a number of components and devices, some of which will be used in particular embodiments of the system in accordance with the principles of the present invention, and others. In other embodiments, other similar systems, components, and devices may be used. Typically, such systems include logic circuitry for working with memory. The logic circuitry can be, for example, discrete, programmable, application specific, or in the form of a microprocessor. Embodiments herein are also used in or connected to the wafer.

The exemplary system of Figure 6 is for illustrative purposes only. Although the description may refer to terms commonly used to describe particular computer, communication, tracking, and entertainment systems, the description and concepts apply equally to other systems, including systems having different architectures than those depicted in FIG. In various embodiments, the electronic system 600 can be implemented as, for example, a general purpose computer, a router, a large data storage system, a portable computer, a personal digital assistant, a mobile phone, an electronic entertainment device such as a music or video playback device or a video game, A microprocessor, microcontroller or audio recognition device. Any or all of the components depicted in Figure 6 may enable the memory of the bi-directional chalcogenide electronics selection switch, such as a chalcogenide-based limit switch.

In an illustrative embodiment, system 600 can include a central processing unit (CPU) 605 that can be implemented by some or all of the microprocessors, a random access memory (RAM) 610 for temporary storage of information, and permanent information for information. Stored read-only memory (ROM) 615. A memory controller 620 is provided for controlling the RAM 610. In accordance with the principles of the present invention, all or any portion of any memory component (e.g., RAM or ROM) can be implemented as a memory using an OTS in series with a two-way memory.

Electronic system 600 in accordance with the principles of the present invention may be a microprocessor operating as CPU 605, in combination with, or as part of, a memory such as RAM 610 and/or ROM 615. In the illustrated example, the microprocessor/chalcogenide selection switch combination can be a stand-alone computer or can operate with other components such as that not described in FIG.

Busbar 630 is interconnected with components of system 600 in completion within the scope of the present invention. A bus bar controller 625 is provided for controlling the bus bar 630. Interrupt controller 635 may or may not be used to receive and process various interrupt signals from system components. Components such as bus 630, bus controller 625, and interrupt controller 635 can be used for large-scale completion of systems in accordance with the principles of the present invention, such as a stand-alone computer, router, portable computer, or data storage system.

A floppy disk 642, a compact disc (CD ROM) 647 or a hard disk 652 can provide a large amount of storage. The data and software can be exchanged with system 600 via removable media such as floppy disk 642 and CD ROM 647. The floppy disk 642 can be inserted into the floppy disk drive 641 connected to the bus bar 630 via the controller 640 in sequence. Similarly, the CD ROM 647 can be inserted into the optical disk drive 646 connected to the bus bar 630 via the controller 645 in sequence. Hard disk 652 is part of a fixed disk drive 651 that is coupled to bus bar 630 via controller 650. Although conventional terms for storage devices (e.g., floppy disks) are used in the description of a system in accordance with the principles of the present invention, any or all of the storage devices may use OTS as a series in parallel with a two-way memory in accordance with the principles of the present invention. The selection device is completed. The removable storage can be provided via a non-volatile storage component, such as a USB flash drive having a two-way memory in accordance with the principles of the present invention as a storage medium. Using such memory as a storage system for a "plug and play" alternative to a conventional removable memory such as a disc, CD ROM or flash drive, an existing controller can be simulated to provide, for example, a controller 640, 645. And the transparent interface of the 650 controller.

User input to system 600 can be provided via any of a number of devices. For example, keyboard 656 and mouse 657 are connected to bus bar 630 via controller 655. As depicted, an audio converter 696, which can function as a microphone and speaker, is coupled to bus bar 630 via audio controller 697. Other input devices, such as pens and/or trackpads, may be coupled to bus bar 630 and appropriate controllers and software as needed as input devices. As previously described, a direct memory access (DMA) controller 660 is provided to perform direct memory access to RAM 610, which may be accomplished in whole or in part using such memory in accordance with the principles of the present invention. The visual display device is generated via a video controller 665 that controls display device 670. Display device 670 can be any size or technology suitable for a particular application.

In a mobile phone or portable entertainment system embodiment, for example, display device 670 can include one or more relatively small (e.g., each side sized) LCD display device. In large data storage systems, the display device can be implemented as a large multi-screen, liquid crystal display (LCD) or organic light emitting diode (OLED), including, for example, a point-of-sale OLED.

System 600 can include a communication adapter 690 that allows the system to be interconnected to a local area network (LAN) or wide area network (WAN) that is schematically depicted by bus 691 and network 695. Input interface 699 operates in conjunction with input device 693 to allow the user to transmit information to system 600 regardless of instructions and controls, data or other types of information. The input device and interface can be any number of common interface devices, such as a joystick, trackpad, touch screen, voice recognition device, or other known input device. In some embodiments of a system in accordance with the principles of the present invention, adapter 690 can operate in conjunction with transceiver 673 and antenna 675 to provide wireless communication for implementation, such as mobile phones, radio frequency identification (RFID), and wireless broadband (wifi) computers. .

The operation of system 600 is typically controlled and coordinated by the operating system software. The operating system controls the configuration and execution of system resources, such as processing schedules between events, memory management, network cabling, and input/output (I/O) services. In particular, the operation of other components of the operating system coordination system 600 resident in the system memory and executed on the CPU 605.

In a handheld electronic device embodiment in accordance with the principles of the present invention, for example, a mobile phone, a personal digital assistant, an electronic calendar, a notebook computer, a handheld information device, such as a device for playing music and/or video. Handheld entertainment devices, as well as small input devices such as keypads, function keys, and soft keys known in the art, may be substituted for, for example, controller 655, keyboard 656, and mouse 657. Embodiments with transmitters, recording capabilities, etc. may also include a microphone input (not shown).

In the RFID interrogator implementation of system 600 in accordance with the principles of the present invention, antenna 675 can be used to intercept interrogation signals from frequency F ₁ of the base station. The intercepted interrogation signal is then used to guide the tuning circuit (not shown) receives the signal F ₁ and rejects all other signals. This signal is then passed to a transceiver 673 where the modulation of the carrier F ₁ containing the interrogation signal is detected, amplified and shaped in a known manner. The detected interrogation signal is then passed to a decoder and logic circuit, which may be implemented as discrete logic, such as a low power application, or as a microprocessor/memory combination as described above. The interrogation signal modulation can define a code from the OTS selection memory in accordance with the principles of the present invention to read data or to write data to the OTS selection memory. In the present illustrative embodiment, data read from the memory is transferred to the transceiver 673 or as a second frequency F "response" signal on the antenna _6752. The passive RFID system power system is derived from interrogation signals, and memory in accordance with the principles of the present invention is particularly well suited for such applications.

100. . . Bidirectional write memory unit

102. . . Bidirectional limit switch (OTS)

104. . . Two-way memory component

106, 110. . . First terminal

108, 112. . . Second terminal

200. . . Two-way memory array

201, 203. . . Selection circuit

202. . . Two-way memory unit

204, 206, 208, 210. . . Bidirectional switch

300. . . Crosspoint memory array

302, 304, 306, 308, 316, 328, 332. . . P-channel field effect transistor

310, 312, 318, 330, 334. . . N-channel field effect transistor

314. . . Decoding circuit

500. . . unit

536. . . Substrate

546. . . Integrated circuit component

548. . . Interlayer dielectric

550. . . Two-way memory

552. . . Conducted word line

554. . . line

556. . . Selection device

558. . . Two-way memory component

560. . . Lower electrode

562. . . Insulator

564. . . Two-way memory material

566,571. . . Top electrode

568. . . Barrier film

570. . . Bottom electrode

572. . . Chalcogenide material

600. . . electronic system

605. . . Central processing unit

610. . . Random access memory

615. . . Read only memory

620. . . Memory controller

625. . . Bus controller

630, 691. . . Busbar

635. . . Interrupt controller

640, 645, 650, 655. . . Controller

641. . . Floppy disk player

642. . . Soft disk

646. . . CD player

647. . . Disc

651. . . Fixed disk drive

652. . . Hard disk

656. . . keyboard

657. . . mouse

660. . . Direct memory access controller

665. . . Video controller

670. . . Display device

673. . . transceiver

675. . . antenna

690. . . Communication adapter

693. . . Input device

695. . . network

696. . . Audio converter

697. . . Audio controller

699. . . Input interface

1 is a conceptual block diagram of a two-way memory unit in accordance with the principles of the present invention;

2 is a conceptual block diagram of a bidirectional memory array in accordance with the principles of the present invention;

3 is a more detailed block diagram of a two-way memory array in accordance with the principles of the present invention;

4A through 4D are timing diagrams illustrating the operation of the bidirectional memory in accordance with the principles of the present invention;

Figure 5 is a perspective view showing a two-way memory unit in accordance with the principles of the present invention;

6 is a conceptual block diagram of an electronic system including a two-way memory array in accordance with the principles of the present invention.

100. . . Bidirectional write memory unit

102. . . Bidirectional limit switch (OTS)

104. . . Two-way memory component

106, 110. . . First terminal

108, 112. . . Second terminal

Claims (5)

An apparatus for accessing a bidirectional memory, comprising: a plurality of bidirectional memory cells arranged in a rectangular array, having a column for accessing each cell and a row access line, each bidirectional memory cell comprising a bidirectional a limit switch and a bidirectional memory element for blocking inadvertent access to the bidirectional memory element; and a plurality of power supplies, wherein at least two of the power supplies are opposite current polarities, the power supplies being used for A current directed opposite is coupled to the memory cells to access a two-way memory cell. The device of claim 1, wherein the bidirectional memory unit comprises a resistive random access memory. The device of claim 1, wherein the bidirectional memory unit comprises a magnetoresistive random access memory. The device of claim 1, wherein the two-way memory unit comprises a ferroelectric random access memory. The device of claim 1, wherein the two-way memory unit comprises a metal nanoparticle memory.