TWI492048B - Data display method - Google Patents
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Description
本發明係與數位資料有關，更詳而言之是指一種資料顯示方法。The present invention relates to digital data, and more particularly to a method of displaying data.
隨著數位科技的進步，越來越多電子產品配備有微處理器及記憶體來達到快速運算及處理之目的，藉以透過運算及處理應用程式之方式使電子產品具有更多的額外附加功能。With the advancement of digital technology, more and more electronic products are equipped with microprocessors and memory for fast computing and processing purposes, so that electronic products have more additional functions through computing and processing applications.
當研發人員在研發上述配備有微處理器及記憶體之電子產品時，通常會利用邏輯分析儀來擷取記憶體匯流排上之數位資料，並透過於一顯示裝置上顯示之方式供研發人員分析上述所擷取之數位資料，藉以判定上述電子產品之設計是否正常。When R&D personnel develop the above-mentioned electronic products equipped with microprocessors and memories, they usually use logic analyzers to capture digital data on the memory bus and display them on a display device for developers. The above-mentioned digital data is analyzed to determine whether the design of the above electronic product is normal.
請參閱圖1，市售之邏輯分析儀在擷取數位資料，並將其轉譯顯示於顯示裝置上後，大多係直接以橫軸位移之波型圖、或是以波型圖解譯對應之數值列來顯示所擷取之數位資料。Referring to FIG. 1 , after the commercially available logic analyzer captures the digital data and translates it on the display device, most of the waveforms are directly shifted by the horizontal axis, or by the waveform. A numeric column displays the digital data captured.
然而，當研發人員利用邏輯分析儀在擷取數位資料後，仍須逐項記錄所擷取之記憶體匯流排訊號被寫入與被讀取之資料數值進行比對，才可判定電子產品數位資料處理之設計是否正常。However, when the R&D personnel use the logic analyzer to retrieve the digital data, it is still necessary to record the memory bus signal received by the data record and compare it with the data value to be read. Whether the data processing design is normal.
然而，眾所皆知的是，隨著科技的進步，各種電子產品所需處理之數位資料量越來越龐大，使得所顯示之波型圖或是數值列將會變的繁多與複雜，而此種顯示方式不僅會造成研發人員比對之困難度增加，而可能有誤判之情形發生外，且亦會造成比對時間之延宕，進而造成研發效率低落。是以，綜上所述可得知，習用邏輯分析儀用以顯示數位資訊之方法仍未臻完善，且尚有待改進之處。However, it is well known that with the advancement of technology, the amount of digital data that various electronic products need to process is becoming larger and larger, so that the displayed waveforms or numerical columns will become more complicated and complicated. This kind of display method will not only increase the difficulty of comparison between R&D personnel, but may also lead to misjudgment, and it will also cause delay in comparison time, which will result in low efficiency of research and development. Therefore, in summary, it can be known that the method used by the conventional logic analyzer to display digital information is still not perfect, and there is still room for improvement.
有鑑於此，本發明之主要目的在於提供一種資料顯示方法，可有效地提升訊號分析之速度與效率。In view of this, the main object of the present invention is to provide a data display method, which can effectively improve the speed and efficiency of signal analysis.
緣以達成上述目的，本發明所提供之資料顯示方法係用以於一邏輯分析儀擷取一記憶體匯流排之資料時，顯示該記憶體匯流排之資料；該資料顯示方法包含下列步驟：In order to achieve the above object, the data display method provided by the present invention is used to display the data of the memory bus when a logic analyzer captures data of a memory bus; the data display method comprises the following steps:
A. 載入對應該記憶體匯流排之通訊協定的解碼手段；A. Loading the decoding means of the communication protocol corresponding to the memory bus;
B. 擷取複數個該記憶體匯流排之訊號封包；B. extracting a plurality of signal packets of the memory bus;
C. 以步驟A所選擇之解碼手段解譯步驟B所擷取之訊號封包；C. Interpreting the signal packet captured in step B by using the decoding method selected in step A;
D. 以陣列排列之方式至少顯示該記憶體匯流排之各位址欄位中，被寫入或被讀取之資料數值於一顯示裝置上。D. Display at least the data value written or read in the address field of the memory bus in an array arrangement on a display device.
依據上述構思，於步驟D中，係以陣列表格之方式顯示該記憶體匯流排之各位址欄位被寫入或被讀取的資料數值。According to the above concept, in step D, the data value of the address field of the memory bus is written or read in an array table.
依據上述構思，於步驟D中，係以矩陣圖形之方式顯示該記憶體匯流排之各位址欄位被寫入或被讀取的資料數值。According to the above concept, in step D, the value of the data to which the address field of the memory bus is written or read is displayed in a matrix pattern.
依據上述構思，於步驟D中，更同時依據擷取順序以一串接列顯示該記憶體匯流排被寫入或被讀取資料之位址欄位的位址以及欄位中之資料數值。According to the above concept, in step D, the address of the address field of the memory bus bar to be written or read data and the data value in the field are displayed in a series of columns according to the order of the capture.
依據上述構思，於步驟D中，該串接列中的每筆被寫入或被讀取資料之位址欄位，係以各位址欄位之位址顯示，且各位址欄位中之資料數值串接在後方式，顯示於該顯示裝置上。According to the above concept, in step D, the address field of each data written or read in the serialized column is displayed by the address of the address field, and the information in the address field The value is serially connected to the display device and displayed on the display device.
依據上述構思，於步驟D中，以陣列排列方式顯示之各該資料數值，係超連結於該串接排列中相對應之位址欄位。According to the above concept, in step D, each of the data values displayed in an array arrangement is hyperlinked to a corresponding address field in the serial arrangement.
依據上述構思，於步驟D中，各該被寫入之資料數值係以一第一顯示方式顯示之，而各該被讀取之資料數值係以一第二顯示方式顯示之。According to the above concept, in step D, each of the written data values is displayed in a first display manner, and each of the read data values is displayed in a second display manner.
依據上述構思，該第一顯示方式係以一第一顏色顯示，而該第二顯示方式則係以一第二顏色顯示，且該第二顏色不等於該第一顏色。According to the above concept, the first display mode is displayed in a first color, and the second display mode is displayed in a second color, and the second color is not equal to the first color.
依據上述構思，於步驟D之陣列排列中的每個資料位置係各別對應於該記憶體匯流排之一個位址欄位；且於步驟D中，更同時偵測該記憶體匯流排之各該位址欄位所被讀取之資料數值是否等於被寫入之資料數值，於不相等時，該陣列排列中所對應之資料位置，以不同於其他資料位置之顯示方式顯示出來。According to the above concept, each of the data locations in the array arrangement of step D corresponds to an address field of the memory busbar; and in step D, the memory busbars are detected simultaneously. Whether the data value read by the address field is equal to the data value to be written, when the data is not equal, the data position corresponding to the array arrangement is displayed in a manner different from the display manner of other data positions.
依據上述構思，於步驟D中，係以顯示不同於其他資料位置之顏色的方式，顯示出被讀取之資料數值不等於被寫入之資料數值的位址欄位所對應之資料位置。According to the above concept, in step D, the data position corresponding to the address field of the data value to be written is not displayed in a manner different from the color of the other data position.
依據上述構思，於步驟D中，係顯示該記憶體匯流排之位址欄位最後一次被寫入之資料或被讀取之資料的資料數值。According to the above concept, in step D, the data of the last time the address field of the memory bus is written or the data value of the read data is displayed.
依據上述構思，於步驟D中，係顯示該記憶體匯流排之位址欄位每一次被寫入之資料或被讀取之資料的資料數值。According to the above concept, in step D, the data of each time the address field of the memory bus is written or the data value of the read data is displayed.
依據上述構思，於步驟D中，係以下拉式選單之顯示方式呈現所點選之位址欄位每次被寫入或被讀取之資料數值。According to the above concept, in step D, the display mode of the pull-down menu presents the data value of the selected address field that is written or read each time.
依據上述構思，於步驟D中，陣列排列的縱向欄位的排列順序係對應該記憶體匯流排之區段位址之順序，而其橫向列位的排列順序則係對應該記憶體匯流排之偏移位址之順序。According to the above concept, in step D, the order of the vertical columns of the array arrangement is the order of the sector addresses corresponding to the memory bus, and the order of the horizontal columns is the bias of the memory bus. The order of the shifted addresses.
依據上述構思，於步驟D中，更同時顯示有該記憶體匯流排之資料的波型圖。According to the above concept, in step D, a waveform pattern of the data of the memory busbar is displayed at the same time.
依據上述構思，於步驟D中，係同時顯示被寫入之資料與被讀取之資料的資料數值。According to the above concept, in step D, the data of the data to be written and the data of the data to be read are simultaneously displayed.
藉此，透過上述以陣列之方式同時顯示該記憶體匯流排之位址欄位被寫入之資料或被讀取之資料的資料數值，而可有效地提升研發人員訊號分析之速度與效率。Thereby, the speed and efficiency of the signal analysis of the research and development personnel can be effectively improved by simultaneously displaying the data written in the address field of the memory busbar or the data value of the read data in an array manner.
為能更清楚地說明本發明，茲舉較佳實施例並配合圖示詳細說明如後。In order that the present invention may be more clearly described, the preferred embodiments are illustrated in the accompanying drawings.
請參閱圖2，本發明提供一種資料顯示方法用以在一邏輯分析儀擷取一記憶體匯流排之資料時，顯示該記憶體匯流排之資料，藉以供研發人員可透過所顯示之內容判定與分析記憶體匯流排之資料走向是否正常。該資料顯示方法包含有下列步驟：Referring to FIG. 2, the present invention provides a data display method for displaying data of a memory bus when a logic analyzer captures data of a memory bus, so that the developer can determine through the displayed content. Whether the data of the analysis memory bus is normal. The data display method includes the following steps:
A. 載入對應該記憶體匯流排之通訊協定的解碼手段。一般來說，該通訊協定係存放於電腦中對應該影像訊號產生裝置之動態連結資料庫(Dynamic Link Library，DLL)中，且該動態連結資料庫係採用靜態連結(statically linked)至微軟基礎類別庫(Microsoft Foundation Classes，MFC)之動態連結資料庫。藉此，便可透過載入對應之動態連結資料庫來取得其通訊協定之解碼手段。A. Load the decoding means for the communication protocol that corresponds to the memory bus. Generally speaking, the communication protocol is stored in a dynamic link library (DLL) corresponding to the image signal generating device in the computer, and the dynamic link database is statically linked to the Microsoft basic category. Dynamic Linking Database for Microsoft Foundation Classes (MFC). In this way, the decoding method of the communication protocol can be obtained by loading the corresponding dynamic link database.
B. 擷取複數個該記憶體匯流排之訊號封包。B. Capture a plurality of signal packets of the memory bus.
C. 以步驟A所選擇之解碼手段解譯步驟B所擷取之訊號封包。於本實施例中，所載入對應該記憶體匯流排之通訊協定為I2 C，當該邏輯分析儀擷取訊號後，則先解譯出對應之記憶體位址，而後依據後面接續之訊號狀態，判讀是寫入資料至對應之記憶體位址、或是自記憶體位址讀取資料，舉例來說，當記憶體位址後面接續之訊號為低電位(Low)時，則判讀為寫入後續之資料至對應之記憶體位址；而當記憶體位址後面接續之訊號為高電位(High)時，則判讀為自對應之記憶體位址讀取資料。於本實施例中，上述方式主要以I2 C為例，而每一通訊協定進行解碼之方式皆有差異，非僅以此實施例中之高低電位判斷為依據。C. Interpret the signal packet captured in step B by the decoding means selected in step A. In this embodiment, the communication protocol corresponding to the memory bus is I 2 C. When the logic analyzer captures the signal, the corresponding memory address is first interpreted, and then the subsequent signal is followed. State, the interpretation is to write data to the corresponding memory address, or read data from the memory address. For example, when the signal following the memory address is low (Low), the reading is written as a follow-up The data is sent to the corresponding memory address; when the signal following the memory address is high, the data is read from the corresponding memory address. In this embodiment, the above method mainly uses I 2 C as an example, and each communication protocol performs decoding in a different manner, which is not based only on the high and low potential judgments in this embodiment.
D. 以陣列排列之方式至少顯示該記憶體匯流排之各位址欄位中，被寫入或被讀取之資料數值於一顯示裝置上。D. Display at least the data value written or read in the address field of the memory bus in an array arrangement on a display device.
請參閱圖3至圖5，於本實施例中，係於該顯示裝置上以一第一顯示區塊10顯示該記憶體匯流排之資料的波型圖、以及依據擷取順序以一串列列顯示該記憶體匯流排被寫入或被讀取資料之位址欄位的位址以及欄位中之資料數值，而於本實施例中，該串接列每筆被寫入或被讀取資料之位址欄位，係以各位址欄位之位址顯示在前，而各位址欄位中之資料數值串接在後的方式顯示於該顯示裝置上。同時，於一第二顯示區塊20以陣列排列之方式顯示該記憶體匯流排之各位址欄位的資料數值，且陣列排列中的每個資料位置皆各別對應於該記憶體匯流排之一個位址欄位。而於本實施例中，該第二顯示區塊20所顯示之陣列排列的縱向欄位的排列順序，係對應該記憶體匯流排之區段位址(0X00、0X10、0X20…)之順序，而其橫向列位的排列順序則係對應該記憶體匯流排之偏移位址(0~F)之順序。Referring to FIG. 3 to FIG. 5, in the embodiment, a waveform pattern of the data of the memory busbar is displayed on the display device by a first display block 10, and a series is arranged according to the order of the capture. The column displays the address of the address field in which the memory bus is written or read, and the data value in the field. In this embodiment, the serial column is written or read. The address field of the data is displayed in front of the address of the address field, and the data value in the address field is displayed in series on the display device. At the same time, the second display block 20 displays the data values of the address fields of the memory bus in an array arrangement, and each data position in the array arrangement corresponds to the memory bus. An address field. In this embodiment, the arrangement order of the vertical columns of the array arrangement displayed by the second display block 20 is in the order of the sector addresses (0X00, 0X10, 0X20...) of the memory bus. The order of the horizontal columns is the order of the offset addresses (0~F) of the memory bus.
另外，本實施例中，更透過按鍵選擇之方式提供研發人員可選擇僅顯示被寫入資料的位址欄位所對應之資料位置及資料數值(如圖3)、或是僅顯示被讀取資料的位址欄位所對應之資料位置及資料數值(如圖4)、亦或是同時顯示所有位址欄位被寫入資料與被讀取資料所對應之資料位置及資料數值(如圖5)。而值得一提的是，於步驟C解譯所擷取之訊號時，可在解譯出寫入資料至對應之記憶體位址、或是解譯出自對應之記憶體位址讀取資料時，同時一併抓取寫入或讀取之資料數值，而可提升步驟D在顯示被寫入資料的欄位及資料數值、或是顯示被讀取資料的欄位資料數值時之速度。In addition, in this embodiment, the research and development personnel can select to display only the data location and the data value corresponding to the address field of the written data (as shown in FIG. 3) or only the display is read through the button selection manner. The data location and data value corresponding to the address field of the data (as shown in Figure 4), or the data location and data value corresponding to the data being read and the data of all the address fields are displayed at the same time (as shown in the figure). 5). It is worth mentioning that when the signal captured in step C is interpreted, the data can be written to the corresponding memory address or the corresponding memory address can be interpreted. The data value written or read is also captured, and the speed of step D in displaying the field and data value of the written data or the field data value of the read data can be increased.
再者，在本實施例中係以陣列表格之方式同時顯示該記憶體匯流排之各個位址欄位最後一次被寫入之資料或被讀取之資料的資料數值，且各該被寫入之資料數值係以一第一顯示方式顯示，而各該被讀取之資料數值係以一第二顯示方式顯示，於本實施例中，該第一顯示方式係以一第一顏色顯示，而該第二顯示方式則係以一第二顏色顯示且該第二顏色不等於該第一顏色，藉以供研發人員可快速辨識被寫入資料與被讀取資料的位址欄位。Furthermore, in this embodiment, the last written data of each address field of the memory bus bar or the data value of the read data is simultaneously displayed in an array table, and each of the data is written. The data value is displayed in a first display manner, and each of the read data values is displayed in a second display manner. In this embodiment, the first display mode is displayed in a first color. The second display mode is displayed in a second color and the second color is not equal to the first color, so that the developer can quickly recognize the address field of the written data and the read data.
值得一提的是，於步驟D中，更會偵測各該位址欄位所被讀取之資料數值是否等於被寫入之資料數值，若不相等時，則於該陣列排列中所對應之資料位置將以不同於其他資料位置之顯示方式顯示出來。舉例來說，可透過不同於其他資料位置之顏色的顯示方式，顯示出不相等之位址欄位所對應之資料位置(如圖3至圖5中被填滿顏色的資料位置)，而可使研發人員快速地查覺資料有誤之位址欄位。It is worth mentioning that in step D, it is detected whether the data value read by each address field is equal to the data value to be written, and if not equal, the corresponding in the array arrangement The location of the data will be displayed in a different way than the other data locations. For example, the data position corresponding to the unequal address field can be displayed through a display manner different from the color of the other data position (as shown in FIG. 3 to FIG. 5, the data position filled with the color), but Enable R&D personnel to quickly detect the location of the incorrect data.
藉此，透過上述資料顯示方法之設計，以陣列排列之方式顯示該記憶體匯流排之位址欄位被寫入或被讀取的資料數值，而可使得研發人員不用拖拉時間軸位移波型圖來逐一記錄各位址欄位資料被寫入或被讀取之狀況，不僅可以有效地降低研發人員訊號分析時之負擔，更可藉此大幅地提升研發人員訊號分析之速度與效率。Thereby, through the design of the data display method, the data value of the address field of the memory bus bar is written or read in an array arrangement, so that the researcher does not have to drag the time axis displacement waveform. The picture records the status of the address field data being written or read one by one, which not only can effectively reduce the burden of the developer's signal analysis, but also greatly improve the speed and efficiency of the researcher's signal analysis.
必須說明的是，以上所述僅為本發明較佳可行實施例而已，並不以此為限，舉例來說，本發明除使用前述實施例之表格顯示方式外，亦可如圖6以矩陣圖形之方式顯示。另外，除顯示各位址欄位最後一次被寫入或被讀取之資料數值外，亦同時記錄各位址欄位每次被寫入或被讀取之資料數值，並透過如圖7所示，研發人員點選欲查閱的位址欄位後，以下拉式選單之顯示方式呈現所點選之位址欄位每次被寫入或被讀取之資料數值，此下拉式選單所呈現之資料數值亦如同上述實施例，若寫入和讀取數值不相同時，可透過以顯示不同於其他位址欄位之顏色的方式，標示出所被讀取之資料數值不等於被寫入之資料數值之位址欄位，並且更可透過將各資料數值超連結於該第一顯示區塊10所顯示之串接列中，相對應之位址欄位以及波形圖，讓研發人員能藉由點選某個資料位置中之資位數值，就可讓波形顯示區域直接跳到對應所點選之資料數值的位址欄位，以利進行資料之分析。再者，舉凡應用本發明說明書及申請專利範圍所為之等效方法變化，理應包含在本發明之專利範圍內。It should be noted that the above description is only a preferred embodiment of the present invention, and is not limited thereto. For example, the present invention may be in the form of a matrix as shown in FIG. 6 except that the table display manner of the foregoing embodiment is used. Graphical display. In addition, in addition to displaying the data value of the last time the address field was written or read, the data value of each address field being written or read is also recorded, as shown in FIG. After the R&D personnel selects the address field to be accessed, the following pull-type menu displays the data value of the selected address field that is written or read each time. The data presented in the drop-down menu is displayed. The value is also the same as the above embodiment. If the written and read values are different, the value of the data to be read is not equal to the data value to be written by displaying the color different from the other address fields. The address field can be further connected to the serial column displayed by the first display block 10, corresponding to the address field and the waveform diagram, so that the developer can use the point field Selecting the value of a position in a data location allows the waveform display area to jump directly to the address field corresponding to the selected data value for analysis of the data. Furthermore, variations of the equivalent methods of the present invention and the scope of the claims are intended to be included in the scope of the invention.
10‧‧‧第一顯示區塊10‧‧‧First display block
20‧‧‧第二顯示區塊20‧‧‧Second display block
圖1為習用顯示記憶體匯流排資料之畫面。Fig. 1 is a view showing a conventional display memory bus data.
圖2為本發明資料顯示方法之流程圖。2 is a flow chart of a method for displaying data according to the present invention.
圖3為本發明僅顯示被寫入資料的位址欄位及資料數值之畫面。FIG. 3 is a view showing only the address field and the data value of the data to be written in the present invention.
圖4為本發明僅顯示被讀取資料的位址欄位及資料數值之畫面。4 is a screen showing only the address field and the data value of the read data according to the present invention.
圖5為本發明同時顯示被寫入及被讀取資料的位址欄位及資料數值之畫面。FIG. 5 is a view showing the address field and the data value of the data to be written and read simultaneously.
圖6為本發明以矩陣圖型顯示位址欄位及數值的畫面。FIG. 6 is a view showing a frame type and a numerical value in a matrix pattern according to the present invention.
圖7為透過下拉選單顯示各位址欄位所有被寫入及被讀取之資料數值Figure 7 shows the value of all the data fields written and read in the address field through the drop-down menu.
Claims (18)
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4696004A (en) * | 1984-05-28 | 1987-09-22 | Takeda Riken Kogyo Kabushikikaisha | Logic analyzer |
| TWI224195B (en) * | 2002-10-25 | 2004-11-21 | Zeroplus Technology Co Ltd | Data analysis method for programmable logic analyzer |
| TW200921399A (en) * | 2007-11-09 | 2009-05-16 | Zeroplus Technology Co Ltd | Method of a single-step logic analyzer processing multi-step trigger by using software |
| US20090327538A1 (en) * | 2008-06-27 | 2009-12-31 | Fujitsu Limited | Data transfer apparatus, information processing apparatus, and data transfer method |
| TW201006140A (en) * | 2008-07-18 | 2010-02-01 | Hon Hai Prec Ind Co Ltd | Signal decoding system and method |
| US7743296B1 (en) * | 2007-03-26 | 2010-06-22 | Lattice Semiconductor Corporation | Logic analyzer systems and methods for programmable logic devices |
| US20100195512A1 (en) * | 2009-02-02 | 2010-08-05 | Harvey Timothy J | Systems and methods for presenting electronic communication packets using a logic analyzer |
| CN102369535A (en) * | 2009-02-03 | 2012-03-07 | 费森尼斯医疗德国公司 | Device and method for preventing unauthorized use and/or manipulation of software |
-
2012
- 2012-03-30 TW TW101111453A patent/TWI492048B/en active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4696004A (en) * | 1984-05-28 | 1987-09-22 | Takeda Riken Kogyo Kabushikikaisha | Logic analyzer |
| TWI224195B (en) * | 2002-10-25 | 2004-11-21 | Zeroplus Technology Co Ltd | Data analysis method for programmable logic analyzer |
| US7743296B1 (en) * | 2007-03-26 | 2010-06-22 | Lattice Semiconductor Corporation | Logic analyzer systems and methods for programmable logic devices |
| TW200921399A (en) * | 2007-11-09 | 2009-05-16 | Zeroplus Technology Co Ltd | Method of a single-step logic analyzer processing multi-step trigger by using software |
| US20090327538A1 (en) * | 2008-06-27 | 2009-12-31 | Fujitsu Limited | Data transfer apparatus, information processing apparatus, and data transfer method |
| TW201006140A (en) * | 2008-07-18 | 2010-02-01 | Hon Hai Prec Ind Co Ltd | Signal decoding system and method |
| US20100195512A1 (en) * | 2009-02-02 | 2010-08-05 | Harvey Timothy J | Systems and methods for presenting electronic communication packets using a logic analyzer |
| CN102369535A (en) * | 2009-02-03 | 2012-03-07 | 费森尼斯医疗德国公司 | Device and method for preventing unauthorized use and/or manipulation of software |
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