TWI491065B - Light-emitting chip package and method of forming same - Google Patents

Description

Light-emitting chip package and method of forming same

The present invention relates to a light-emitting chip package and a method of forming the same, and more particularly to a light-emitting chip package having through-substrate vias.

The chip package not only provides a connection interface for the wafer packaged therein, but also protects the wafer from environmental contaminants.

As the functionality increases, a large amount of heat may be generated during wafer operation, which will adversely affect the performance of the wafer. Especially for light-emitting diode (LED) components, the thermal energy generated during operation may seriously degrade the LED characteristics and lifetime of the LED components.

Therefore, there is a need in the industry for a light-emitting chip package having excellent heat dissipation and high structural strength.

An embodiment of the present invention provides a light emitting chip package comprising: a carrier substrate having a first surface and a second surface opposite thereto, and a recess extending from the first surface toward the second surface; at least one conductive a channel and at least one heat conducting plug, located outside the groove and passing through the first surface and the second surface of the carrying substrate; a light emitting element having at least one contact electrode disposed in the groove, wherein the contact The electrode is electrically connected to the conductive channel and insulated from the thermal conductive plug.

An embodiment of the present invention provides a method for forming a light emitting chip package, comprising: providing a carrier substrate having a first surface and a second surface opposite thereto; partially removing the carrier substrate to form at least one first hole, The first surface of the carrier substrate extends toward the second surface; the carrier substrate is partially removed to form at least a second hole extending from the first surface of the carrier substrate toward the second surface; The second surface is thinned to expose the first hole and the second hole to form at least one first through hole and at least one second hole; a first conductive layer is formed on the sidewall of the first hole; Forming a second conductive layer on the sidewall of the second via; and disposing a light emitting component on the first surface, wherein the light emitting component has a contact electrode to electrically connect the first conductive layer.

The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.

1A and 1C-1E are cross-sectional views showing a series of processes of a light-emitting chip package according to an embodiment of the present invention. Referring to FIG. 1A, a carrier substrate 100 having a first surface 100a and an opposite second surface 100b is provided. The carrier substrate 100 can include, but is not limited to, a semiconductor material such as germanium. For example, the carrier substrate 100 can be a germanium wafer. When the germanium wafer is selected as the carrier substrate 100, wafer-level packaging can be performed to form the light-emitting chip package according to an embodiment of the invention, thereby significantly reducing the cost of fabricating the light-emitting chip package and time. In another embodiment, the carrier substrate 100 can be made of other materials such as aluminum, aluminum nitride, aluminum oxide, or a combination of the foregoing.

Figure 1B shows a top view of the carrier substrate 100 of Figure 1A. As shown in Figures 1A and 1B, the carrier substrate 100 is partially removed to form at least one hole, such as holes 104a and 104a', and holes 104b and 104b'. The holes 104a, 104a', 104b, and 104b' extend from the first surface 100a of the carrier substrate 100 toward the second surface 100b. These holes can be formed simultaneously or separately. For example, a lithography and etching process can be performed to partially remove the carrier substrate 100, thereby simultaneously or separately forming the holes 104a, 104a', 104b, and 104b'.

As shown in FIGS. 1A and 1B, in another embodiment, a recess 302 may be formed in the carrier substrate 100 that extends from the first surface 100a of the carrier substrate 100 toward the second surface 100b. The bottom of the recess 302 is used to carry the light-emitting element, and a reflective layer may be formed on the sidewall or the bottom of the recess 302, thereby forming a reflective structure surrounding the light-emitting element to reflect the light emitted from the light-emitting element upward. The groove 302 can be formed before or after the holes 104a, 104a', 104b, and 104b' are formed. Alternatively, a groove can be formed simultaneously with the holes. Furthermore, the openings of the holes and recesses may have any suitable shape, such as circular, rectangular, square, or the like.

Referring to Fig. 1C, the second surface 100b of the carrier substrate 100 is thinned until the holes 104a, 104a', 104b, and 104b' are exposed. The thinning process can include, but is not limited to, chemical mechanical polishing (CMP) or grinding. After the thinning process, the holes 104a, 104a', 104b, and 104b' are now through-holes. Thus, reference numerals 104a and 104a' can also be used to represent the perforations 104a and 104a', respectively. Similarly, reference numerals 104b and 104b' can also be used to represent the perforations 104b and 104b', respectively. After the carrier substrate 100 is thinned, the distance between the bottom of the recess 302 and the second surface 100b of the carrier substrate 100 is reduced. In an embodiment, the perforations surround the groove 302 and not under the groove.

Referring to FIG. 1D, an insulating layer 106 is formed on the surface of the carrier substrate 100. The insulating layer 106 may include, but is not limited to, an epoxy resin, a solder resist material, or other suitable insulating material, such as a cerium oxide layer of an inorganic material, a tantalum nitride layer, a cerium oxynitride layer, a metal oxide, or the foregoing. Combination; or may be a polyimine resin of organic polymer materials, butylcyclobutene (BCB, Dow Chemical Company), parylene, polynaphthalenes, Fluorocarbons, acrylates, and the like. The manner in which the insulating layer 106 is formed may include a coating method such as spin coating, spray coating, or curtain coating, or other suitable deposition method, for example, liquid deposition, Processes such as physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or atmospheric pressure chemical vapor deposition. In an embodiment, the carrier substrate 100 includes a crucible. In this case, the insulating layer 106 is preferably a ruthenium oxide layer formed by a thermal oxidation process. In other embodiments, the carrier substrate 100 is an insulating substrate, such as an aluminum nitride substrate or an alumina substrate. In this case, the insulating layer 106 can be omitted.

Continuing to refer to FIG. 1D, a conductive layer is then formed on the surface of the carrier substrate 100, and then patterned into conductive layers 108a, conductive layers 108b, and line redistribution layers 108c extending into the vias 104a, 104b as a conductive path of the light emitting element. The conductive layer can include, but is not limited to, copper, aluminum, gold, indium tin oxide, or the like. The conductive layer may be formed by physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, or the like. The conductive layer can be patterned by, for example, a patterning process including lithography and etching processes. In this embodiment, the conductive layer 108a and the conductive layer 108b further extend into the recess 302, and the trace redistribution layer 108c is located on the bottom of the recess 302 to serve as the reflective layer 150 of the reflective structure. Therefore, the light-emitting element placed on the carrier substrate 100 can receive electrical energy from a power source located on the other side of the carrier substrate 100 through a conductive via (TSV). In one embodiment, the light-emitting elements to be placed comprise a plurality of light-emitting diodes connected in series with one another. In this case, the line redistribution layer 108c can serve as a conductive bridge between the light-emitting diodes.

Although the conductive layer 108a and the conductive layer 108b shown in FIG. 1D are only conformally formed on the sidewalls of the perforations without completely filling the perforations, embodiments of the present invention are not limited to this specific example. In other embodiments, the conductive layer can be made to fill the perforations substantially completely, as desired.

Referring to FIG. 1E, a light emitting element 110 is disposed on the bottom of the recess 302. The light emitting element 110 can include, but is not limited to, a light emitting diode (LED), an organic light emitting diode (OLED), a polymer light emitting diode (PLED), or the like. The light emitting element 110 includes a first contact electrode 110a and a second contact electrode 110b for receiving power. The first contact electrode 110a and the second contact electrode 110b may be located on the same side of the light emitting element 110. In another embodiment, the first contact electrode 110a and the second contact electrode 110b may be located on different sides of the light emitting element 110.

Furthermore, when the light-emitting element 110 is a light-emitting diode, the first contact electrode 110a has a conductivity type opposite to that of the second contact electrode 110b. In an embodiment, the first contact electrode 110a is a p-type electrode and the second contact electrode 110b is an n-type electrode. In another embodiment, the first contact electrode 110a is an n-type electrode and the second contact electrode 110b is a p-type electrode.

In an embodiment, the light emitting element 110 includes a plurality of light emitting diodes 111. These light-emitting diodes 111 are connected in series to each other, for example, as shown in the structure of FIG. 1E. One of the light-emitting diodes 111 can be electrically connected to the other light-emitting diodes 111 through a bonding wire or a circuit redistribution layer 108c previously defined on the carrier substrate 100. In one embodiment, the light-emitting element 110 includes an array of a plurality of light-emitting diodes 111 connected in series with each other.

In the embodiment shown in FIG. 1E, the first contact electrode 110a of the light-emitting element 110 is in direct contact with the conductive layer 108a extending to the bottom of the recess 302, and the second contact electrode 110b of the light-emitting element 110 is extended. The conductive layer 108b on the bottom to the recess 302 is in direct contact. The light emitting element 110 may include a plurality of light emitting diodes 111 connected in series with each other. In this case, a large amount of current will flow through the light emitting element 110 during operation.

In addition, the conductive layer 108a and the conductive layer 108b extending over the sidewalls of the recess 302 can be used as the reflective layer 150 in addition to providing power to the light-emitting element 110 to reflect the light emitted from the light-emitting element upward. In other words, the conductive layer 108a and the conductive layer 108b can also serve as a reflective layer for electrically connecting the contact electrode and the conductive path. In this case, the conductive layer 108a and the conductive layer 108b are preferably made of a conductive material having high reflectivity such as aluminum, silver, copper, or the like. In other embodiments, a reflective layer may be additionally formed on the conductive layer 108a and the conductive layer 108b in the recess 302 as a reflective structure.

Referring to FIGS. 1E and 1B, the first contact electrode 110a of the light-emitting element 110 is electrically connected to two conductive channels (the combination of the vias 104a and 104a' and the conductive layer 108a), and the second contact electrode of the light-emitting element 110 110b is electrically connected to two conductive vias (the combination of vias 104b and 104b' and conductive layer 108b). Therefore, the high current flowing through the light-emitting element 110 is shared by a plurality of conductive channels, which can significantly improve the reliability of the light-emitting chip package. Sometimes, the electrical connection between one of the conductive paths and the light-emitting element may not be successfully established due to process error or error. Because at least two conductive channels are designed to be electrically connected to the contact electrodes of the light-emitting elements, so that even if one of the conductive paths fails to be electrically connected to one of the contact electrodes of the light-emitting element, other conductive channels can be used. An electrical connection between the power source and the light emitting element is provided.

In this embodiment, the conductive path is preferably disposed outside the area surrounded by the reflective structure (the combination of the recess and the conductive layer). The thermal energy from the conductive path and the light-emitting element 110 will not accumulate in the recess in which the light-emitting element 110 is located, and the heat energy loss can be remarkably enhanced.

In an embodiment, at least one thermal via may be further formed in the carrier substrate to further enhance thermal energy dissipation of the light emitting chip package. 2 is a top view of a carrier substrate of a light emitting chip package in accordance with an embodiment of the present invention. In this embodiment, an additional thermally conductive aperture 204 is formed in the carrier substrate 100 using a similar method of forming the holes and recesses of FIG. Next, similar to FIG. 1D, a conductive layer is formed on the sidewalls of the holes including the thermally conductive holes 204 to form at least one thermally conductive plug that extends to the sidewall or bottom of the recess to further carry thermal energy away from the outside of the recess. Also, heat energy is prevented from accumulating at the bottom of the groove or under the substrate. Therefore, the thermal plug helps to dissipate heat from the light emitting chip package. In one embodiment, the conductive layer for heat conduction can serve as another reflective layer 160, but is electrically insulated from the contact electrodes and the conductive vias to avoid short circuits. The position and distribution of the thermal plug can take any form depending on the requirements.

As described above, in one embodiment, a plurality of conductive vias may be provided in the light emitting chip package for sharing (or dispersing) a high current flowing through the light emitting elements or as a backup conductive path. In another embodiment, the conductive vias and the additional thermally conductive plugs are located outside of the area surrounded by the recess and are not disposed at the base below the recess. Therefore, in addition to the enhancement of the strength under the substrate, the heat dissipation and reliability of the light-emitting chip package can be increased. Therefore, a light-emitting chip package having excellent heat dissipation properties and excellent structural strength can be obtained.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

100‧‧‧bearing substrate

100a, 100b‧‧‧ surface

104a, 104a', 104b, 104b'‧‧‧ holes (or perforations)

106‧‧‧Insulation

108a, 108b‧‧‧ conductive layer

108c‧‧‧Line redistribution

110‧‧‧Lighting elements

110a, 110b‧‧‧ contact electrode

111‧‧‧Lighting diode

204‧‧‧thermal hole

150, 160‧‧‧reflective layer

302‧‧‧ Groove

1A and 1C-1E are cross-sectional views showing a series of processes of a light-emitting chip package according to an embodiment of the present invention.

Figure 1B shows a top view of the carrier substrate 100 of Figure 1A.

2 is a top view of a carrier substrate of a light emitting chip package in accordance with an embodiment of the present invention.

100. . . Carrier substrate

100a, 100b. . . surface

104a, 104b. . . Hole (or perforation)

106. . . Insulation

108a, 108b. . . Conductive layer

108c. . . Line redistribution

110. . . Light-emitting element

110a, 110b. . . Contact end

111. . . Light-emitting diode

150. . . Reflective layer

302. . . Groove

Claims (18)

An illuminating chip package comprising: a carrier substrate having a first surface and a second surface opposite thereto; and a recess extending from the first surface toward the second surface; at least one conductive via and at least one thermal insertion a plug, located outside the groove and passing through the first surface and the second surface of the carrier substrate; and a light emitting element having at least one contact electrode disposed in the recess, wherein the contact electrode is electrically connected to the The conductive path is insulated from the thermally conductive plug, the contact electrode facing a bottom of the recess. The illuminating chip package of claim 1, wherein the illuminating element comprises a light emitting diode. The illuminating chip package of claim 1, wherein the illuminating element comprises a plurality of illuminating diodes, wherein the illuminating diodes are connected in series with each other. The illuminating chip package of claim 1, further comprising a reflective structure surrounding the illuminating element. The illuminating chip package of claim 4, wherein the illuminating element is disposed on the bottom of the recess, and the reflective structure is located on the bottom or a side wall of the recess. The light emitting chip package of claim 5, wherein the reflective structure comprises a first reflective layer and a second reflective layer, and the first reflective layer and the second reflective layer are electrically insulated from each other. The light emitting chip package of claim 6, wherein the first reflective layer and the second reflective layer are made of a metal material. The light emitting chip package according to claim 7 of the patent application, The first reflective layer is electrically connected to the contact electrode and the conductive path. The illuminating chip package of claim 8, wherein the second reflective layer is connected to the thermal conductive plug and electrically insulated from the contact electrode and the conductive path. A method for forming a light-emitting chip package, comprising: providing a carrier substrate having a first surface and a second surface opposite thereto; partially removing the carrier substrate to form at least one first hole, the first substrate from the carrier substrate a surface extending toward the second surface; partially removing the carrier substrate to form at least one second hole extending from the first surface of the carrier substrate toward the second surface; the second surface from the carrier substrate being thinned The carrier substrate exposes the first hole and the second hole to form at least one first through hole and at least one second through hole; a first conductive layer is formed on a sidewall of the first through hole; and the second through hole is formed on the sidewall Forming a second conductive layer on the sidewall; and disposing a light emitting element on the first surface; wherein the light emitting element has a contact electrode electrically connected to the first conductive layer, wherein the contact electrode faces the groove a bottom portion and insulated from the second conductive layer. The method for forming a light-emitting chip package according to claim 10, wherein the light-emitting element comprises a plurality of light-emitting diodes, and the light-emitting diodes are connected in series with each other. Such as the luminescent crystal described in claim 10 or 11 a method for forming a chip package, wherein the first conductive layer serves as a conductive path in the first through hole, and the second conductive layer serves as a heat conductive plug in the second through hole, wherein the heat conductive plug is respectively The conductive channel and the contact electrode are electrically insulated from each other. The method for forming a light-emitting chip package according to claim 12, further comprising: forming a groove extending from the first surface toward the second surface; and disposing the light-emitting element at the bottom of the groove And forming a reflective structure on one of the sidewalls or the bottom of the recess. The method for forming a light-emitting chip package according to claim 13 , wherein the reflective structure comprises a first reflective layer and a second reflective layer, and the first reflective layer and the second reflective layer are electrically connected to each other Sexual insulation. The method of forming a light-emitting chip package according to claim 14, wherein the first through hole and the second through hole surround the groove. The method for forming a light-emitting chip package according to claim 13, wherein the groove, the first holes, and the second holes are simultaneously formed. The method for forming a light-emitting chip package according to claim 10, wherein the first holes and the second holes are simultaneously formed. The method for forming an illuminating chip package according to claim 14, wherein the first conductive layer and the second conductive layer respectively extend to a sidewall or a bottom of the recess to serve as the first reflective layer. And the second reflective layer.