TWI490998B - Chip package unit - Google Patents
Chip package unit Download PDFInfo
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- TWI490998B TWI490998B TW097110140A TW97110140A TWI490998B TW I490998 B TWI490998 B TW I490998B TW 097110140 A TW097110140 A TW 097110140A TW 97110140 A TW97110140 A TW 97110140A TW I490998 B TWI490998 B TW I490998B
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- chip package
- package unit
- conductive structures
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- end region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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Description
本發明係關於一種晶片封裝單元；特別是關於可應用於一堆疊封裝結構之晶片封裝單元。The present invention relates to a chip package unit; and more particularly to a chip package unit that can be applied to a stacked package structure.
隨著半導體技術的進步，各種封裝技術已被廣泛使用於各種電子產品中。例如將晶片封裝單元與另一實質上相同結構之晶片封裝單元以電性連接方式堆疊之技術。此先前技術在不增加電路板面積條件下，可置入更高密度之晶片。故當電子產品需要節省電路板所佔空間時，晶片封裝單元便成為不可或缺的元件。With the advancement of semiconductor technology, various packaging technologies have been widely used in various electronic products. For example, a technique of stacking a chip package unit and another wafer package unit of substantially the same structure in an electrical connection manner. This prior art can place higher density wafers without increasing board area. Therefore, when an electronic product needs to save space occupied by a circuit board, the chip package unit becomes an indispensable component.
先前技術已提出可實現晶片封裝單元應用之封裝堆疊架構，目前已知先前技術揭露利用一導線架來作為電性連接晶片封裝單元之中介層，請參第1圖以便說明。The prior art has proposed a package stacking architecture that can implement a chip package unit application. It is known in the prior art to utilize a lead frame as an interposer for electrically connecting the chip package unit. Please refer to FIG. 1 for illustration.
第1圖為習知一晶片封裝單元1與另一晶片封裝單元1a堆疊之一實施例之示意圖，其晶片封裝單元與1與另一晶片封裝單元1a具有實質上相同結構。晶片封裝單元1包含一晶片10及一導線架11。在該導線架11具有一第一表面12與一第二表面13，且該導線架11包含有複數針通孔(Pin Through Hole,PTH)14，各該針通孔14在第二表面13下有對應之各該銲點凸塊15，如此形成一晶片封裝單元1。一晶片封裝單元1之各該銲點凸塊15與另一晶片封裝單元1a之複數針通孔16電性連接，其電性連接處用一錫膏17來固接，該錫膏17可輔助並加強連接結構之穩固。並將堆疊之後晶片封裝單元1電性連接於一印刷電路板18上。1 is a schematic view showing an embodiment of a conventional chip package unit 1 and another chip package unit 1a stacked, and the chip package unit 1 and the other chip package unit 1a have substantially the same structure. The chip package unit 1 includes a wafer 10 and a lead frame 11. The lead frame 11 has a first surface 12 and a second surface 13 , and the lead frame 11 includes a plurality of pin through holes (PTH) 14 , each of which is under the second surface 13 . There are corresponding solder bumps 15 corresponding thereto, thus forming a chip package unit 1. Each of the solder bumps 15 of the chip package unit 1 is electrically connected to the plurality of pin through holes 16 of the other chip package unit 1a, and the electrical connection is fixed by a solder paste 17, and the solder paste 17 can assist And strengthen the connection structure. The chip package unit 1 after being stacked is electrically connected to a printed circuit board 18.
第2圖為習知一晶片封裝單元2與另一晶片封裝單元2a堆疊時之一實施例之示意圖，其晶片封裝單元與2與另一晶片封裝單元2a具有實質上相同結構。本實施例與前一實施例不同之處在於一晶片封裝單元2於導線架21之第一表面22及第二表面23上分別各使用一複數銲點凸塊24來作為電性連接方式。其方式是為在晶片封裝單元2之各該複數針通孔25之第一表面22與第二表面23上分別形成一銲點凸塊24，藉此與另一相同結構之晶片封裝單元2a進行堆疊，各該銲點凸塊24與各該針通孔25電性連接處用一錫膏26來輔助與加強結構穩固。並將堆疊之後晶片封裝單元2堆疊之電性連接於一印刷電路板27上。2 is a schematic view showing an embodiment of a conventional chip package unit 2 stacked with another chip package unit 2a, the chip package unit 2 and the other chip package unit 2a having substantially the same structure. The difference between the present embodiment and the previous embodiment is that a chip package unit 2 uses a plurality of solder bumps 24 on the first surface 22 and the second surface 23 of the lead frame 21 as electrical connections. The method is to form a solder bump 24 on the first surface 22 and the second surface 23 of each of the plurality of pin vias 25 of the chip package unit 2, thereby performing the chip package unit 2a of another identical structure. Stacking, each solder joint bump 24 and each of the pin through holes 25 are electrically connected with a solder paste 26 to assist the reinforcing structure. The stack of the chip package unit 2 after the stack is electrically connected to a printed circuit board 27.
通常來說，晶片封裝單元1之堆疊需在導線架11上透過針通孔14使用銲點凸塊15來做電性連接，但銲點凸塊15之厚度相當厚，其佔據了大部分堆疊之空間，使該晶片封裝單元1與晶片封裝單元1a所進行之堆疊結構具有相當之厚度。同時銲點凸塊15在接點處容易造成裂縫，導致品質成本增加。且一般傳統晶片封裝單元為非晶片級封裝(Non Chip Scale Package)其晶片在封裝後之引腳尺寸較大，造成其晶片封裝單元面積較大，在堆疊時造成封裝結構內部散熱不良。Generally, the stack of the chip package unit 1 needs to be electrically connected to the lead frame 11 through the pin through holes 14 using the solder bumps 15, but the thickness of the solder bumps 15 is relatively thick, which occupies most of the stack. The space is such that the stacked structure of the chip package unit 1 and the chip package unit 1a has a considerable thickness. At the same time, the solder bumps 15 are liable to cause cracks at the joints, resulting in an increase in quality cost. Moreover, the conventional chip package unit is a non-chip scale package, and the size of the chip after the package is large, resulting in a large area of the chip package unit, which causes poor heat dissipation inside the package structure during stacking.
有鑑於此，提供一種改良之晶片封裝單元，使堆疊後之整體厚度縮減，並使接點處不易斷裂進而減少品質成本，乃為此一業界亟待解決的問題。In view of the above, it is an urgent problem to be solved in the industry to provide an improved chip package unit, which reduces the overall thickness after stacking, and makes the joints difficult to break and thus reduces the quality cost.
本發明之目的在於提供一種晶片封裝單元，於晶片封裝單元與 晶片封裝單元之間採用一導線架，以提供一導電路徑。該導線架上使用單面平板銲球來以固接各晶片封裝單元間之堆疊，適以與另一實質上相同結構之晶片封裝單元進行電性堆疊。藉此，可達到減低堆疊後晶片封裝單元厚度之目的，使堆疊後之整體厚度縮減，同時減少製程成本。It is an object of the present invention to provide a chip package unit for a chip package unit and A lead frame is used between the chip package units to provide a conductive path. The lead frame uses a single-sided flat solder ball to fix the stack between the chip package units, and is electrically stacked with another substantially identical structure of the chip package unit. Thereby, the purpose of reducing the thickness of the chip package unit after stacking can be achieved, the overall thickness after stacking is reduced, and the process cost is reduced.
本發明之另一目的在於提供一種晶片封裝單元，於晶片封裝單元與晶片封裝單元之間採用一導線架或一可撓性基板，以提供一導電路徑。該導線架上使用雙面平板銲球來固接各晶片封裝單元間之堆疊，適以與另一實質上相同結構之晶片封裝單元進行電性堆疊。藉此，可達到減低堆疊後晶片封裝單元厚度之目的，使堆疊後之整體厚度縮減，並減少製造成本。Another object of the present invention is to provide a chip package unit in which a lead frame or a flexible substrate is used between the chip package unit and the chip package unit to provide a conductive path. The lead frame uses double-sided flat solder balls to fix the stack between the chip package units, and is electrically stacked with another substantially identical structure of the chip package unit. Thereby, the purpose of reducing the thickness of the chip package unit after stacking can be achieved, the overall thickness after stacking is reduced, and the manufacturing cost is reduced.
為達上述目的，本發明揭露一種晶片封裝單元，適以與另一實質上相同結構之晶片封裝單元進行電性堆疊。該晶片封裝單元包含一晶片及二導電結構。該晶片具有二端面及位於該二端面間之一主動面。各該導電結構具有一第一端部區域與該第一端部區域相對之一第二端部區域、一第一表面及與該第一表面相對之一第二表面。各該導電結構係藉由該第一端部區域，以該第一表面與該主動面電性連接，並沿該晶片之其中一端面彎折。藉此該晶片封裝單元之第二端部區域，適可藉由該第一表面，與該另一晶片封裝單元之相對應導電結構之一第二表面呈電性連接。To achieve the above object, the present invention discloses a chip package unit that is electrically stacked with another substantially identical structure of a chip package unit. The chip package unit comprises a wafer and two conductive structures. The wafer has two end faces and an active face between the two end faces. Each of the electrically conductive structures has a first end region opposite the first end region, a second end region, a first surface, and a second surface opposite the first surface. Each of the conductive structures is electrically connected to the active surface by the first end region and bent along one of the end faces of the wafer. Thereby, the second end region of the chip package unit is electrically connected to the second surface of one of the corresponding conductive structures of the other chip package unit by the first surface.
本發明更揭露一種晶片封裝單元，適以與另一實質上相同結構之晶片封裝單元進行電性堆疊。該晶片封裝單元包含一晶片及二導電結構。該晶片具有二端面及位於該二端面間之一主動面及一 非主動面。各該導電結構具有一第一端部區域、與該第一端部區域相對之一第二端部區域、一第一表面及與該第一表面相對之一第二表面。各該導電結構係藉由該第一端部區域，以該第一表面與該主動面電性連接，並沿該晶片之其中一端面，彎折至該非主動面上。藉此該晶片之第二端部區域，適可藉由該第二表面，與該另一晶片封裝單元之相對應導電結構之一第二表面呈電性連接。The invention further discloses a chip package unit suitable for electrically stacking with another substantially identical structure of a chip package unit. The chip package unit comprises a wafer and two conductive structures. The wafer has two end faces and an active surface between the two end faces and a Inactive surface. Each of the electrically conductive structures has a first end region, a second end region opposite the first end region, a first surface, and a second surface opposite the first surface. Each of the conductive structures is electrically connected to the active surface by the first end region and bent along the one end surface of the wafer to the inactive surface. Thereby, the second end region of the wafer is electrically connected to the second surface of one of the corresponding conductive structures of the other chip package unit by the second surface.
為讓本發明之上述目的、技術特徵、和優點能更明顯易懂，下文係以較佳實施例配合所附圖式進行詳細說明。The above described objects, technical features, and advantages of the present invention will become more apparent from the following description.
以下將透過實施例來解釋本發明內容，其係關於一種晶片封裝單元，適以與另一實質上相同結構之晶片封裝單元進行電性堆疊，以達到減低堆疊後晶片封裝單元厚度之目的，並改進先前技術中使用針通孔、銲點凸塊來做為導電路徑之缺點。然而，本發明的實施例並非用以限制本發明需在如實施例所述之任何特定的環境、應用或特殊方式方能實施。關於實施例之說明僅為闡釋本發明之目的，而非用以限制本發明。需說明者，以下實施例及圖式中，與本發明非直接相關之元件已省略而未繪示；且為求容易瞭解起見，各元件間之尺寸關係乃以稍誇大之比例繪示出。The present invention will be explained below by way of embodiments, relating to a chip package unit suitable for electrically stacking with another substantially identical structure of a chip package unit to reduce the thickness of the packaged wafer package unit. The disadvantages of using pin through holes and solder joint bumps as conductive paths in the prior art are improved. However, the embodiments of the present invention are not intended to limit the invention to any specific environment, application, or special mode as described in the embodiments. The description of the embodiments is merely illustrative of the invention and is not intended to limit the invention. It should be noted that in the following embodiments and drawings, elements that are not directly related to the present invention have been omitted and are not shown; and for ease of understanding, the dimensional relationships between the elements are shown in a slightly exaggerated proportion. .
第3圖係為本發明之晶片封裝單元3之一實施例之示意圖。須說明的是，該晶片封裝單元3可適用至一微間距錫球陣列封裝(Fine pitch Ball Grid Array,FBGA)，其為一種晶片級封裝之封裝類型。一般而言，晶片級封裝之定義為封裝後晶片之面積與封 裝前晶片之面積比小於百分之二十。晶片封裝單元3包含一晶片30及二導電結構31a及31b。該晶片30具有二端面32a及32b及一主動面33，該主動面33位於該二端面32a及32b間。各該導電結構31a及31b具有一第一端部區域34、與該第一端部區域34相對之一第二端部區域35、一第一表面36及與該第一表面36相對之一第二表面37。具體而言，本實施例中各導電結構31a及31b之材料，係由銅所製成，但在其他實施例中並不以此材料為限，例如其他金屬亦可作為導電結構31a及31b之材料如鋁、金、銀、鉻、鈀、鎢、鎳及鉑等，以發揮電性傳導並可支撐之目的。各該導電結構31a及31b，係藉由該第一端部區域34，以該第一表面36與該主動面33電性連接，並沿該晶片30之其中一端面32a及32b彎折。在本實施例中，晶片30之主動面33上具有複數襯墊38，導電結構31a及31b即透過該等襯墊，電性連結至晶片30。因此，導電結構31a及31b可具有細指狀之外型，以對應該等襯墊38之分佈。Fig. 3 is a schematic view showing an embodiment of the chip package unit 3 of the present invention. It should be noted that the chip package unit 3 can be applied to a Fine Pitch Ball Grid Array (FBGA), which is a package type of a wafer level package. In general, wafer level packaging is defined as the area and sealing of the packaged wafer. The area ratio of the pre-mount wafer is less than 20%. The chip package unit 3 includes a wafer 30 and two conductive structures 31a and 31b. The wafer 30 has two end faces 32a and 32b and an active face 33. The active face 33 is located between the two end faces 32a and 32b. Each of the conductive structures 31a and 31b has a first end region 34, a second end region 35 opposite the first end region 34, a first surface 36, and a first surface 36 opposite the first surface 36. Two surfaces 37. Specifically, the materials of the conductive structures 31a and 31b in the embodiment are made of copper, but in other embodiments, the material is not limited thereto. For example, other metals may also be used as the conductive structures 31a and 31b. Materials such as aluminum, gold, silver, chromium, palladium, tungsten, nickel and platinum are used for electrical conduction and support. Each of the conductive structures 31a and 31b is electrically connected to the active surface 33 by the first surface portion 34 and bent along one of the end faces 32a and 32b of the wafer 30. In the present embodiment, the active surface 33 of the wafer 30 has a plurality of pads 38 through which the conductive structures 31a and 31b are electrically connected to the wafer 30. Therefore, the conductive structures 31a and 31b may have a thin finger shape to correspond to the distribution of the pads 38.
請繼續參考第3圖，晶片封裝單元3之導電結構31a及31b沿該晶片30之其中一端面32a及32b彎折後，如此便可與另一實質上相同結構之晶片封裝單元4進行電性堆疊，其內容將於第4圖詳細說明。需進一步說明的是在第3圖中複數第一連接件39形成於各該第一端部區域34，以使該晶片之主動面33透過該等第一連接件39與該主動面33電性連接。具體而言於本實施例中，該第一連接件39係為單面平板式銲球，用來作為晶片封裝單元3中晶片30與導電結構31a及31b之電性連接。Referring to FIG. 3, the conductive structures 31a and 31b of the chip package unit 3 are bent along one of the end faces 32a and 32b of the wafer 30, so that the chip package unit 4 of substantially the same structure can be electrically connected. Stacked, the contents of which will be detailed in Figure 4. It should be further noted that in FIG. 3, a plurality of first connecting members 39 are formed on each of the first end regions 34 such that the active surface 33 of the wafer is electrically connected to the active surface 33 through the first connecting members 39 and the active surfaces 33. connection. Specifically, in the embodiment, the first connecting member 39 is a single-sided flat solder ball for electrically connecting the wafer 30 and the conductive structures 31a and 31b in the chip package unit 3.
請繼續參考第4圖係為本發明晶片封裝單元3與另一實質上相 同結構之晶片封裝單元4進行電性堆疊之一實施例示意圖，藉由彎折後之晶片封裝單元3與另一實質上相同結構之晶片封裝單元4進行電性堆疊，其堆疊方式為晶片封裝單元3之第二端部區域35，適可藉由該第一表面36，與該另一晶片封裝單元4之相對應導電結構40a及40b之一第二表面41呈電性連接。Please refer to FIG. 4 for the wafer package unit 3 of the present invention and another substantial phase. A schematic diagram of an embodiment of electrically stacking the same package of the chip package unit 4 is performed by electrically stacking the bent chip package unit 3 and another substantially identical structure of the chip package unit 4 in a chip package. The second end region 35 of the unit 3 is electrically connected to the second surface 41 of one of the corresponding conductive structures 40a and 40b of the other chip package unit 4 by the first surface 36.
進一步言，複數第二連接件42形成於該晶片封裝單元3之各該第二端部區域35，以使晶片封裝單元3透過該等第二連接件42，與該另一晶片封裝單元4之相對應導電結構40a及40b之該第二表面41呈電性連接。Further, a plurality of second connecting members 42 are formed on each of the second end regions 35 of the chip package unit 3 such that the chip package unit 3 passes through the second connecting members 42 and the other chip package unit 4 The second surface 41 of the corresponding conductive structures 40a and 40b is electrically connected.
於本實施例中，該第二連接件42係一平板式錫球，與先前技術使用之銲點凸塊相較下，平板式錫球厚度相對較薄，但可一次完成所有平板式錫球之製造，同時較不易發生錫球斷裂或連接不良等狀況。需說明的是，視需要可裝置一散熱裝置43於晶片封裝單元4之頂端，以幫助散熱，此散熱裝置43可選擇性依製程考量來決定是否附加。In this embodiment, the second connecting member 42 is a flat solder ball. Compared with the solder bumps used in the prior art, the flat solder ball is relatively thin, but all the flat solder balls can be completed at one time. The manufacture is also less prone to breakage of the solder balls or poor connection. It should be noted that a heat sink 43 can be disposed at the top of the chip package unit 4 as needed to help dissipate heat. The heat sink 43 can selectively determine whether to attach according to process considerations.
堆疊後之該晶片封裝單元3可設於一印刷電路板44上。需注意的是各該晶片封裝單元3之各該導電結構31a及31b係設計為具有50歐姆阻抗匹配，可與其他電路作阻抗匹配，設計50歐姆阻抗匹配之方法與結構並非本發明之重點，在此不再多作說明。The stacked chip package unit 3 can be disposed on a printed circuit board 44. It should be noted that each of the conductive structures 31a and 31b of each of the chip package units 3 is designed to have 50 ohm impedance matching and can be impedance matched with other circuits. The method and structure for designing 50 ohm impedance matching are not the focus of the present invention. No more explanation is given here.
第5圖係為本發明另一種晶片封裝單元5之另一實施例示意圖，該晶片封裝單元5包含一晶片50及二導電結構51a及51b。須說明的在此實施例中該晶片封裝單元5為一微間距錫球陣列封裝，在前一實施例已經說明在此不再贅述。該晶片具有二端面52a 及52b及位於該二端面52a及52b間之一主動面53及一非主動面54。各該導電結構51a及51b具有一第一端部區域55與該第一端部區域55相對之一第二端部區域56、一第一表面57及與該第一表面57相對之一第二表面58。本實施例中導電結構51a及51b之材料，係由銅所製成，但在其他實施例中並不以此材料為限，例如其他金屬亦可作為導電結構51a及51b之材料如鋁、金、銀、鉻、鈀、鎢、鎳及鉑等，以發揮電性傳導並可支撐之目的。各該導電結構51a及51b係藉由該第一端部區域55，以該第一表面57與該主動面53電性連接，並沿該晶片50之其中一端面52a及52b，彎折至該非主動面54上。在本實施例中，晶片50之主動面53上具有複數襯墊59，導電結構51a及51b即透過該等襯墊，電性連結至晶片50。因此，導電結構51a及51b可具有細指狀之外型，以對應該等襯墊之分佈。FIG. 5 is a schematic diagram of another embodiment of another chip package unit 5 according to the present invention. The chip package unit 5 includes a wafer 50 and two conductive structures 51a and 51b. It should be noted that in the embodiment, the chip package unit 5 is a micro pitch solder ball array package, which has been described in the previous embodiment and will not be described again. The wafer has two end faces 52a And 52b and an active surface 53 and an inactive surface 54 between the two end faces 52a and 52b. Each of the conductive structures 51a and 51b has a first end region 55 opposite the first end region 55, a second end region 56, a first surface 57 and a second surface opposite the first surface 57 Surface 58. The materials of the conductive structures 51a and 51b in this embodiment are made of copper, but in other embodiments, the material is not limited thereto. For example, other metals may also be used as the materials of the conductive structures 51a and 51b, such as aluminum and gold. , silver, chromium, palladium, tungsten, nickel and platinum, etc., in order to play the role of electrical conduction and support. Each of the conductive structures 51a and 51b is electrically connected to the active surface 53 via the first end region 55, and is bent along the one end surface 52a and 52b of the wafer 50 to the non- Active surface 54. In the present embodiment, the active surface 53 of the wafer 50 has a plurality of pads 59 through which the conductive structures 51a and 51b are electrically connected to the wafer 50. Therefore, the conductive structures 51a and 51b may have a thin finger shape to correspond to the distribution of the pads.
請繼續參考第5圖，本實施例中之導電結構51a及51b係一導線架(Lead frame)，但在其他實施例中可為一可撓性基板，但並不以此材料為限，例如其他電路板材料亦可作為導電結構51a及51b之材料，以發揮電性傳導之目的。藉此該晶片50之第二端部區域56，適可藉由該第二表面58，與該另一晶片封裝單元6之相對應導電結構62a及62b之一第二表面63呈電性連接，其詳細內容於第6圖說明。需更進一步說明的是晶片封裝單元5之複數第一連接件60形成於各該第一端部區域55，以使該主動面53透過該等第一連接件60與該主動面53電性連接。本實施例中各該第一連接件60係一平板式錫球，可利用一次塗佈或者轉印之方式將平板式錫球形成於各該第一端部區域55。第一連接件60之材料並 不限定為平板式錫球，例如其他方式形成之錫球，或者其他可導電材料，以發揮電性傳導並可連接第一連接件60與主動面53之目的。Referring to FIG. 5, the conductive structures 51a and 51b in this embodiment are a lead frame, but in other embodiments may be a flexible substrate, but not limited to this material, for example. Other circuit board materials can also be used as the material of the conductive structures 51a and 51b for the purpose of electrical conduction. The second end region 56 of the wafer 50 is electrically connected to the second surface 63 of the corresponding conductive structures 62a and 62b of the other chip package unit 6 by the second surface 58. The details are illustrated in Figure 6. It is to be further noted that a plurality of first connecting members 60 of the chip package unit 5 are formed in each of the first end regions 55 such that the active surface 53 is electrically connected to the active surface 53 through the first connecting members 60. . In the embodiment, each of the first connecting members 60 is a flat solder ball, and the flat solder balls can be formed in each of the first end regions 55 by one application or transfer. The material of the first connecting member 60 It is not limited to a flat type solder ball, for example, a solder ball formed by other means, or other electrically conductive material, for the purpose of electrically conducting and connecting the first connecting member 60 and the active surface 53.
第6圖係為本發明晶片封裝單元5與另一實質上相同結構之晶片封裝單元6進行電性堆疊之另一實施例示意圖，藉由彎折後之晶片封裝單元5與另一實質上相同結構之晶片封裝單元6進行電性堆疊。詳細而言，其堆疊方式為晶片封裝單元5之複數第二連接件61，形成於各該第二端部區域56，以使晶片封裝單元5透過該等第二連接件61與該另一晶片封裝單元6之相對應導電結構62a及62b之該第二表面63呈電性連接。本實施例中之晶片封裝單元5，該第二連接件61係一平板式錫球，可用以作為二晶片封裝單元堆疊時之連接材料，如同前述，平板式錫球並非作為本發明之限制。FIG. 6 is a schematic view showing another embodiment of electrically stacking the chip package unit 5 of the present invention with another wafer package unit 6 of substantially the same structure, wherein the bent wafer package unit 5 is substantially identical to the other The structure of the chip package unit 6 is electrically stacked. In detail, the plurality of second connecting members 61 of the chip package unit 5 are formed in each of the second end regions 56 such that the chip package unit 5 passes through the second connecting members 61 and the other chip. The second surface 63 of the corresponding conductive structures 62a and 62b of the package unit 6 is electrically connected. In the wafer package unit 5 of the embodiment, the second connector 61 is a flat solder ball, which can be used as a connecting material when the two chip package units are stacked. As described above, the flat solder ball is not limited by the present invention.
該晶片封裝單元5更包含複數第一支撐件64，形成於各該導電結構51a及51b之該第二端部56與該晶片50之該非主動面54之間。此第一支撐件64可用來支持此實例中之導電結構51a及51b。需說明的是堆疊後之該晶片封裝單元5可設於一印刷電路板65上並與之電性連接。且各該晶片封裝單元5之各該導電結構51a及51b係設計為具有50歐姆，可與其他電路作阻抗匹配，設計50歐姆阻抗匹配之方法與結構並非本發明之重點，在此不再多作說明。The chip package unit 5 further includes a plurality of first support members 64 formed between the second end portion 56 of each of the conductive structures 51a and 51b and the inactive surface 54 of the wafer 50. This first support member 64 can be used to support the conductive structures 51a and 51b in this example. It should be noted that the stacked chip package unit 5 can be disposed on a printed circuit board 65 and electrically connected thereto. Each of the conductive structures 51a and 51b of the chip package unit 5 is designed to have 50 ohms and can be impedance matched with other circuits. The method and structure for designing 50 ohm impedance matching are not the focus of the present invention, and no more Give instructions.
第7圖係為本發明另一晶片封裝單元7之結構之另一實施例示意圖，該晶片封裝單元7包含一可撓性基板，其具有一第一表面 73及與該第一表面73相對之一第二表面74，第一表面73及第二表面74上，各形成有一圖案化導電層，藉此，二導電結構可分別形成於該可撓性基板70之兩側。晶片封裝單元7可為一微間距錫球陣列封裝，其優點如同前述，在此不再贅述。Figure 7 is a schematic view showing another embodiment of the structure of another chip package unit 7 of the present invention, the chip package unit 7 comprising a flexible substrate having a first surface And a second surface 74 opposite to the first surface 73, the first surface 73 and the second surface 74 are each formed with a patterned conductive layer, whereby the two conductive structures can be respectively formed on the flexible substrate On both sides of 70. The chip package unit 7 can be a micro pitch solder ball array package, and the advantages thereof are as described above, and are not described herein again.
以左側之導電結構70a為例，其具有一第一端部區域71與相對之一第二端區域72、第一表面73及第二表面74。該導電結構70a係藉由該第一端部區域71，以該第一表面73與該晶片75之主動面78電性連接。該可撓性基板70並沿該晶片75之二端面77a及77b，分別彎折至該主動面78上。在本實施例中，晶片75之主動面78上具有複數襯墊79，導電結構70a即透過該等襯墊79，電性連結至晶片75。Taking the conductive structure 70a on the left side as an example, it has a first end region 71 and a second end region 72, a first surface 73 and a second surface 74. The conductive structure 70a is electrically connected to the active surface 78 of the wafer 75 by the first surface 73 by the first end region 71. The flexible substrate 70 is bent along the two end faces 77a and 77b of the wafer 75 to the active surface 78, respectively. In the present embodiment, the active surface 78 of the wafer 75 has a plurality of pads 79 through which the conductive structures 70a are electrically connected to the wafers 75.
請繼續參考第7圖，晶片封裝單元7更包含複數第一連接件80，形成於各該第一表面73上，藉由該複數第一連接件80與該導電結構70a電性連接，並可在可撓性基板70與晶片75之間注入晶片黏著材料來固接該可撓性基板70與該晶片75。在此實施例中各該第一連接件80係一平板式錫球，其優點如同前述，在此不在贅述。晶片封裝單元7亦包含複數第一支撐件84，以導電結構70a為例，第一支撐件84形成於導電結構70a之第二端部72與晶片75之非主動面76之間。Continuing to refer to FIG. 7 , the chip package unit 7 further includes a plurality of first connecting members 80 formed on each of the first surfaces 73 , and the plurality of first connecting members 80 are electrically connected to the conductive structure 70 a , and A wafer adhesive material is injected between the flexible substrate 70 and the wafer 75 to fix the flexible substrate 70 and the wafer 75. In this embodiment, each of the first connecting members 80 is a flat type solder ball, and the advantages thereof are as described above, and are not described herein. The chip package unit 7 also includes a plurality of first support members 84. The conductive support structure 70a is exemplified. The first support member 84 is formed between the second end portion 72 of the conductive structure 70a and the inactive surface 76 of the wafer 75.
第8圖係為本發明另一晶片封裝單元7與另一實質上相同結構之晶片封裝單元8進行電性堆疊之另一實施例示意圖。其堆疊方式為彎折後之導電結構70a適可藉由該第二表面74，與該另一晶片封裝單元8之相對應導電結構81之一第二表面82呈電性連接。 進一步說明此實施例中晶片封裝單元7及8間之電性連接方式，係藉由複數第二連接件83，形成於第二表面74上，以使晶片封裝單元7透過該等第二連接件83，與該另一晶片封裝單元8之相對應導電結構81之該第二表面82呈電性連接。晶片封裝單元7中，各該第二連接件83係一平板式錫球，其優點如同前述，在此不在贅述。FIG. 8 is a schematic view showing another embodiment of electrically stacking another chip package unit 7 and another wafer package unit 8 of substantially the same structure. The conductive structure 70a is configured to be electrically connected to the second surface 82 of the corresponding conductive structure 81 of the other chip package unit 8 by the second surface 74. Further, the electrical connection between the chip package units 7 and 8 in this embodiment is formed on the second surface 74 by a plurality of second connectors 83 to allow the chip package unit 7 to pass through the second connectors. 83. The second surface 82 of the corresponding conductive structure 81 of the other chip package unit 8 is electrically connected. In the chip package unit 7, each of the second connecting members 83 is a flat solder ball, and the advantages thereof are as described above, and are not described herein.
堆疊後之該晶片封裝單元7可設於一印刷電路板85上並與之電性連接。在此實施例中該導電結構70a係設計為具有50歐姆阻抗匹配，可與其他電路作阻抗匹配，設計50歐姆阻抗匹配之方法與結構並非本發明之重點，在此不再多作說明。The stacked chip package unit 7 can be disposed on a printed circuit board 85 and electrically connected thereto. In this embodiment, the conductive structure 70a is designed to have a 50 ohm impedance matching and can be impedance matched with other circuits. The method and structure for designing a 50 ohm impedance matching are not the focus of the present invention and will not be further described herein.
第9圖係為本發明另一晶片封裝單元9之結構之另一實施例示意圖。與前述實施例之主要差異之處在於晶片封裝單元9之晶片係為一晶粒90。需注意的是，以導電結構91為例，因應製造過程需要，在導電結構91彎折包覆晶粒90前，可利用在晶粒90之銲墊92上使用無電鍍鎳金製程技術，形成複數第一連接件93，再由導電結構91彎折包覆成一晶片封裝單元9。Figure 9 is a schematic view showing another embodiment of the structure of another chip package unit 9 of the present invention. The main difference from the foregoing embodiment is that the wafer of the chip package unit 9 is a die 90. It should be noted that, taking the conductive structure 91 as an example, in order to meet the needs of the manufacturing process, before the conductive structure 91 is bent and coated with the die 90, the electroless nickel-gold process technology can be formed on the pad 92 of the die 90. The plurality of first connecting members 93 are further bent and covered by the conductive structure 91 into a chip package unit 9.
藉由前述揭露之晶片封裝單元，使用導線架與可撓性基板作為電性連接之中介層，在製程上不需做太大改變，可避免製造成本之增加。With the chip package unit disclosed above, the lead frame and the flexible substrate are used as the intermediate layer of the electrical connection, and the manufacturing process does not need to be changed much, and the manufacturing cost can be avoided.
本發明於晶片封裝單元使用一微間距錫球陣列封裝，其可適用於晶片級封裝(Chip Scale Package)，與先前技術相較之下，該晶片封裝單元面積較小，且晶片的引腳尺寸也較小。一般傳統晶片封裝單元，在堆疊時容易造成封裝結構內部散熱不良。針對散熱 問題，本發明在晶片封裝單元堆疊後可在最上方放置一散熱裝置以幫助散熱。The present invention uses a micro-pitch solder ball array package in a chip package unit, which is applicable to a chip scale package. Compared with the prior art, the chip package unit has a small area and a chip lead size. Also small. Generally, a conventional chip package unit is likely to cause poor heat dissipation inside the package structure during stacking. For heat dissipation Problem, the present invention can place a heat sink at the top of the wafer package unit after stacking to help dissipate heat.
先前技術該晶片封裝單元行之堆疊結構用銲點凸塊來作為電性連接使該晶片封裝單元行之堆疊結構具有較厚之厚度，而本發明使用在微間距錫球陣列封裝技術之晶片封裝單元厚度相對變薄。其主要在電性接合處採用平板式錫球，改進先前技術銲點凸塊之缺點，相對減少晶片封裝單元之堆疊厚度。同時銲點凸塊在接點處容易造成裂縫，導致品質成本增加。本發明平板式錫球較先前技術不容易發生裂縫。Prior art, the stacked structure of the chip package unit row uses solder bumps as electrical connections to make the stack structure of the chip package unit have a thick thickness, and the present invention uses a chip package in a micro pitch solder ball array package technology. The cell thickness is relatively thin. It mainly uses flat-plate solder balls at the electrical joints, which improves the disadvantages of the prior art solder joint bumps and relatively reduces the stack thickness of the chip package unit. At the same time, the solder bumps are prone to cracks at the joints, resulting in an increase in quality cost. The flat type solder ball of the present invention is less prone to cracking than the prior art.
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。The embodiments described above are only intended to illustrate the embodiments of the present invention, and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalents that can be easily made by those skilled in the art are within the scope of the invention. The scope of the invention should be determined by the scope of the claims.
1‧‧‧晶片封裝單元1‧‧‧ Chip package unit
1a‧‧‧晶片封裝單元1a‧‧‧ Chip package unit
10‧‧‧晶片10‧‧‧ wafer
11‧‧‧導線架11‧‧‧ lead frame
12‧‧‧第一表面12‧‧‧ first surface
13‧‧‧第二表面13‧‧‧ second surface
14‧‧‧針通孔14‧‧‧ pin through hole
15‧‧‧銲點凸塊15‧‧‧ solder bumps
16‧‧‧針通孔16‧‧‧ pin through hole
17‧‧‧錫膏17‧‧‧ solder paste
18‧‧‧印刷電路板18‧‧‧Printed circuit board
2‧‧‧晶片封裝單元2‧‧‧ Chip package unit
2a‧‧‧晶片封裝單元2a‧‧‧ Chip package unit
21‧‧‧導線架21‧‧‧ lead frame
22‧‧‧第一表面22‧‧‧ first surface
23‧‧‧第二表面23‧‧‧ second surface
24‧‧‧銲點凸塊24‧‧‧ solder bumps
25‧‧‧針通孔25‧‧‧ pin through hole
26‧‧‧錫膏26‧‧‧ solder paste
27‧‧‧印刷電路板27‧‧‧Printed circuit board
3‧‧‧晶片封裝單元3‧‧‧ Chip package unit
30‧‧‧晶片30‧‧‧ wafer
31a‧‧‧導電結構31a‧‧‧Electrical structure
31b‧‧‧導電結構31b‧‧‧Electrical structure
32a‧‧‧端面32a‧‧‧ end face
32b‧‧‧端面32b‧‧‧ end face
33‧‧‧主動面33‧‧‧Active face
34‧‧‧第一端部區域34‧‧‧First end area
35‧‧‧第二端部區域35‧‧‧Second end area
36‧‧‧第一表面36‧‧‧ first surface
37．．．第二表面37. . . Second surface
38．．．襯墊38. . . pad
39．．．第一連接件39. . . First connector
4．．．晶片封裝單元4. . . Chip package unit
40a．．．導電結構40a. . . Conductive structure
40b．．．導電結構40b. . . Conductive structure
41．．．第二表面41. . . Second surface
42．．．第二連接件42. . . Second connector
43．．．散熱裝置43. . . Heat sink
44．．．印刷電路板44. . . A printed circuit board
5．．．晶片封裝單元5. . . Chip package unit
50．．．晶片50. . . Wafer
51a．．．導電結構51a. . . Conductive structure
51b．．．導電結構51b. . . Conductive structure
52a．．．端面52a. . . End face
52b．．．端面52b. . . End face
53．．．主動面53. . . Active surface
54．．．非主動面54. . . Inactive surface
55．．．第一端部區域55. . . First end area
56．．．第二端部區域56. . . Second end area
57．．．第一表面57. . . First surface
58．．．第二表面58. . . Second surface
59．．．襯墊59. . . pad
6．．．晶片封裝單元6. . . Chip package unit
60．．．第一連接件60. . . First connector
61．．．第二連接件61. . . Second connector
62a．．．導電結構62a. . . Conductive structure
62b．．．導電結構62b. . . Conductive structure
63．．．第二表面63. . . Second surface
64．．．第一支撐件64. . . First support
65．．．印刷電路板65. . . A printed circuit board
7．．．晶片封裝單元7. . . Chip package unit
70．．．可撓性基板70. . . Flexible substrate
70a．．．導電結構70a. . . Conductive structure
71．．．第一端部區域71. . . First end area
72．．．第二端部區域72. . . Second end area
73．．．第一表面73. . . First surface
74．．．第二表面74. . . Second surface
75．．．晶片75. . . Wafer
76．．．非主動面76. . . Inactive surface
77a．．．端面77a. . . End face
77b．．．端面77b. . . End face
78．．．主動面78. . . Active surface
79．．．襯墊79. . . pad
8．．．晶片封裝單元8. . . Chip package unit
80．．．第一連接件80. . . First connector
81．．．導電結構81. . . Conductive structure
82．．．第二表面82. . . Second surface
83．．．第二連接件83. . . Second connector
84．．．第一支撐件84. . . First support
85．．．印刷電路板85. . . A printed circuit board
9．．．晶片封裝單元9. . . Chip package unit
90．．．晶粒90. . . Grain
91．．．導電結構91. . . Conductive structure
92．．．銲墊92. . . Solder pad
93．．．第一連接件93. . . First connector
第1圖係習知晶片封裝單元與另一晶片封裝單元堆疊之一實施例之示意圖；第2圖係習知晶片封裝單元與另一晶片封裝單元在堆疊時另一不同電性連接方式一實施例之示意圖；第3圖係為本發明之晶片封裝單元之結構之一實施例之示意圖；第4圖係為本發明晶片封裝單元與另一實質上相同結構之晶片封裝單元進行電性堆疊之一實施例示意圖；第5圖係為本發明另一種晶片封裝單元之另一實施例示意圖；第6圖係為本發明晶片封裝單元與另一實質上相同結構之晶片 封裝單元進行電性堆疊另一實施例示意圖；第7圖係為本發明另一晶片封裝單元之結構之另一實施例示意圖；第8圖係為本發明另一晶片封裝單元與另一實質上相同結構之晶片封裝單元進行電性堆疊之另一實施例示意圖；以及第9圖係為本發明另一晶片封裝單元之結構之另一實施例示意圖。1 is a schematic diagram of one embodiment of a conventional chip package unit and another chip package unit stack; FIG. 2 is a different electrical connection manner of a conventional chip package unit and another chip package unit when stacked. 3 is a schematic diagram of an embodiment of a structure of a chip package unit of the present invention; and FIG. 4 is an electrical stack of a chip package unit of the present invention and another substantially identical structure of the chip package unit. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a schematic view showing another embodiment of another chip package unit according to the present invention; FIG. 6 is a wafer package unit of the present invention and another wafer having substantially the same structure. FIG. 7 is a schematic diagram of another embodiment of the structure of another chip package unit according to the present invention; FIG. 8 is another chip package unit of the present invention and another substantially A schematic diagram of another embodiment of electrical stacking of the same structure of the chip package unit; and FIG. 9 is a schematic view of another embodiment of the structure of another chip package unit of the present invention.
5．．．晶片封裝單元5. . . Chip package unit
50．．．晶片50. . . Wafer
51a．．．導電結構51a. . . Conductive structure
51b．．．導電結構51b. . . Conductive structure
52a．．．端面52a. . . End face
52b．．．端面52b. . . End face
53．．．主動面53. . . Active surface
54．．．非主動面54. . . Inactive surface
55．．．第一端部區域55. . . First end area
56．．．第二端部區域56. . . Second end area
57．．．第一表面57. . . First surface
58．．．第二表面58. . . Second surface
59．．．襯墊59. . . pad
6．．．晶片封裝單元6. . . Chip package unit
60．．．第一連接件60. . . First connector
61．．．第二連接件61. . . Second connector
62a．．．導電結構62a. . . Conductive structure
62b．．．導電結構62b. . . Conductive structure
63．．．第二表面63. . . Second surface
64．．．第一支撐件64. . . First support
65．．．印刷電路板65. . . A printed circuit board
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097110140A TWI490998B (en) | 2008-03-21 | 2008-03-21 | Chip package unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097110140A TWI490998B (en) | 2008-03-21 | 2008-03-21 | Chip package unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200941674A TW200941674A (en) | 2009-10-01 |
| TWI490998B true TWI490998B (en) | 2015-07-01 |
Family
ID=44868378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW097110140A TWI490998B (en) | 2008-03-21 | 2008-03-21 | Chip package unit |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI490998B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110114869A (en) * | 2016-12-27 | 2019-08-09 | 株式会社村田制作所 | Circuit module and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200926392A (en) * | 2007-07-24 | 2009-06-16 | Micron Technology Inc | Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods |
-
2008
- 2008-03-21 TW TW097110140A patent/TWI490998B/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200926392A (en) * | 2007-07-24 | 2009-06-16 | Micron Technology Inc | Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110114869A (en) * | 2016-12-27 | 2019-08-09 | 株式会社村田制作所 | Circuit module and method of manufacturing the same |
| CN110114869B (en) * | 2016-12-27 | 2021-08-31 | 株式会社村田制作所 | Circuit module and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200941674A (en) | 2009-10-01 |
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