TWI489845B - Slave device for an ethernet system and related method of reducing synchronization power consumption - Google Patents

Description

Slave device for an Ethernet system and related methods for improving synchronous power consumption

The present invention relates to a slave device and its associated clock synchronization method, and more particularly to a slave device for an Ethernet system and related methods for improving synchronization power consumption.

In a Giga Ethernet system, both the master and the slave must maintain the clock synchronization by transmitting the idle sequence (Sdle) with or without data transmission. However, continuously transmitting idle sequences without data transmission can result in excessive power consumption. Therefore, the Institute of Electrical and Electronics Engineers (IEEE) has developed Energy Efficient Ethernet (EEE) specifications to save power consumption. Under the energy efficiency Ethernet specification, when the master and slave devices do not transmit data, both parties enter the sleep mode, and only occasionally wake up to transmit the idle sequence to maintain synchronization.

In an Ethernet system, the slave device responds to the clock based on the received signal. For example, the master's transmitter uses a fixed Free Running Clock to transmit the signal. After receiving the transmission signal from the receiver of the device, the slave device performs a Timing Recovery operation to generate one of the free-running clocks of the master device to reply to the clock, the transmitter and the receiver of the slave device. The device transmits or samples the signal according to the reply clock. When the receiver receives the signal transmitted by the slave device according to the reply clock, the receiver of the master device synchronizes to optimize the phase of the receiver sample.

In order to save power, Giga Ethernet includes two machines in idle mode. System: Symmetric and Symmetric. Under the symmetry mechanism, both the master device and the slave device enter the Quiet Mode at the same time when the data is not transmitted, and wake up at the same time when the data is transmitted by either party. During the wake-up process, the master device leads away from the quiet mode, and the slave device can only issue a wake-up request (Request) command. When the transmitted data is in a single direction, one party (master device/slave device) transmits data, and the other party (slave device/master device) has no data transmission, but under the symmetry mechanism, it must be awake with sleep, unable to enter quiet mode to cause excess power. Consumption.

The asymmetric mechanism includes the following two situations: First, the slave device enters the quiet mode, and the master device continuously sends a signal to the slave device; since the slave device receives the signal transmitted by the master device and performs the clock recovery action, the two parties can still reach Clock synchronization. Second, when the master device enters the quiet mode, the slave device continuously transmits a signal to the master device. In this mode, since the slave device does not receive the signal transmitted by the master device, the clock reply operation cannot be performed. After a period of time, the clock transmitting the signal from the device cannot perform the clock recovery because the free action clock of the transmitting end of the main device is not received, causing the clock to drift, and when the main device wakes up and needs to transmit the first data, the main device transmits The device cannot know how much the phase has drifted during the period when the receiver receives the signal from the device. Therefore, the main assembly cannot adjust the clock of the transmitted data to correspond to the phase of the received data drift.

In short, under the conventional asymmetric mechanism, the master device may not synchronize with the slave device's clock after waking up because it enters the quiet mode for a period of time, causing the slave device to receive data errors.

Accordingly, it is a primary object of the present invention to provide a slave device for an Ethernet system and associated methods for improving synchronous power consumption.

The present invention discloses a slave device for improving synchronization power consumption in an Ethernet system. The Ethernet system includes a master device, and the slave device includes a receiver, an operation unit, a transmitter, and a timing. Adjust the unit. The receiver is configured to receive an idle sequence of the primary device. The arithmetic unit is coupled to the receiver for generating a phase difference information according to the idle sequence. The transmitter is configured to transmit data to the host device according to the output clock. . The timing adjustment unit is coupled to the operation unit for adjusting the output clock according to the phase difference information.

The invention further discloses a method for improving synchronous power consumption in a slave device of an Ethernet network system, the Ethernet system comprising a master device, the method comprising receiving an idle sequence of the master device, According to the idle sequence, a phase difference information is generated, an output clock is adjusted according to the phase difference information, and data is transmitted to the master device according to the output clock.

The invention further discloses an Ethernet system comprising a master device and a slave device. The main device includes a first receiver and a first transmitter. The first receiver is configured to receive a data. The first transmitter is configured to transmit an idle sequence. The slave device includes a second receiver, a second transmitter, an arithmetic unit and a timing adjustment unit. The second receiver is configured to receive the idle sequence of the master device. The second transmitter is configured to transmit the data according to an output clock. The computing unit is coupled to the second receiver for generating a phase difference information according to the idle sequence. The timing adjustment unit is coupled to the operation unit for adjusting the output clock according to the phase difference information.

Ethernet system

20, 40, 60‧‧‧ master device

112, 122, 210, 410, 710, 910‧‧ Receiver

111, 121, 240, 430, 720, 940‧‧‧ transmitters

220‧‧‧Scratch

230, 420‧‧‧ phase-locked loop unit

120, 90‧‧‧ slave devices

SIN‧‧‧Transfer information

Ph_Data, Ph_AD‧‧‧ phase adjustment data

T_Ph_Data‧‧‧ phase adjustment value

Out_Clk‧‧‧Output clock

PDD‧‧‧ phase difference information

Idl_Seq‧‧‧ Idle sequence

R_Clk‧‧‧Restoration clock

IN‧‧‧ Receiver

510‧‧‧Information Estimation Unit

520‧‧‧ digital recovery circuit

ERRIN‧‧‧Error Information

30, 70, 90‧‧‧ clock synchronization process

300, 302, 304, 306, 308, 310, 700, 702, 704, 706, 708, 90, 902, 904, 906, 908, 910 ‧ ‧ steps

Figure 1 is a schematic diagram of an Ethernet system.

FIG. 2 is a schematic diagram of a main apparatus for an Ethernet system according to an embodiment of the present invention.

FIG. 3 is a flowchart of a clock synchronization process for a host device of an Ethernet system according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a main apparatus for an Ethernet system according to another embodiment of the present invention.

Figure 5 is a schematic diagram of a receiver for a host device in accordance with an embodiment of the present invention.

Figure 6 is a schematic diagram of a main device for an Ethernet system according to an embodiment of the present invention.

FIG. 7 is a flowchart of a clock synchronization process for a host device of an Ethernet system according to an embodiment of the present invention.

Figure 8 is a schematic diagram of a main device for an Ethernet system according to an embodiment of the present invention.

FIG. 9 is a flowchart of improving synchronization power consumption in a main device of an Ethernet system according to an embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of an Ethernet system 10 according to the present invention. The Ethernet system 10 operates on one of the Giga Ethernet networks under the asymmetric mechanism. The Ethernet system 10 includes a master device 110 and a slave device 120. The main device 110 includes a transmitter 111 for transmitting signals and a receiver 112 for receiving signals from the slave device 120. The slave device 120 includes a transmitter 121 for transmitting signals to the receiver 112 of the master device 110, and a receiver 122 for receiving signals. When the master device 110 and the slave device perform data transfer, the clock synchronization relationship between the two must be maintained to optimize the phase state of the receiver at the time of sampling. That is, the clock phase must be the same or maintain a fixed phase difference between the master and slave.

When the Giga Ethernet system operates in an asymmetric mechanism, the master device 110 enters a Quiet Mode, its transmitter 111 is turned off, and the transmitter 121 of the slave device 120 continuously transmits a signal to the receiver of the master device 110. 112. The present invention provides a clock synchronization method. When the main device 110 starts transmitting the first data after waking up from the quiet mode, the main device 110 knows how many phases the received data has drifted during the period, so that the clock of the transmitted data can be adjusted. The phase corresponds to the clock phase of the received data, so as to prevent the data from being corrupted due to the asynchronous transmission of the data and the received data.

The Ethernet system 10 employs a loop timing system (Loop Timing), which is clocked by the slave device 120 based on the received signal. For example, the transmitter 111 of the master device 110 transmits a signal using a Free Running Clock. After receiving the transmission signal from the receiver 122 of the device 120, the slave device 120 performs a Timing Recovery operation to generate a clock recovery clock that is the same as the free operation clock of the master device 110. The transmitter 121 And the receiver 122 transmits or samples the signal according to the reply clock. When the receiver 111 receives the signal transmitted by the slave device 120 according to the reply clock, the receiver 111 synchronizes so that the clock of the receiver 111 is the same as the reply clock.

Please refer to FIG. 2, which is a schematic diagram of a main device 20 for an Ethernet system according to an embodiment of the present invention. The master device 20 can be the master device 110 of the Ethernet system 10 for improving the wake-up mechanism to resolve the non-synchronization problem that occurs when the master device 20 enters the quiet mode. The main device 20 includes a receiver 210, a register 220, a phase locked loop unit 230, and a transmitter 240. The receiver 210 is configured to generate a phase adjustment data Ph_Data for indicating an increase or decrease of the phase of the output clock according to the transmission data SIN of the slave device when the master device operates in a mode switching. The mode switching master device 20 enters a wake-up mode (Wake-up Mode) by a Quiet Mode. The transmission data SIN of the slave device contains the clock information of the reply clock. Therefore, the master device 20 can solve the reply clock through the transmission data SIN from the device to obtain the phase information. The register 220 is coupled to the receiver 210 for accumulating the phase adjustment data Ph_Data to output a phase adjustment value T_Ph_Data. The phase-locked loop unit 230 is coupled to the register 220 for adjusting the phase of an output clock Out_Clk according to the phase adjustment value T_Ph_Data to maintain a phase difference between the phase of the output clock Out_Clk and the phase of the return clock. In other words, through the phase adjustment value T_Ph_Data stored in the register 220, the master device 20 can know how many phases the clock traverses as time increases in the quiet mode, so that the clock phase of the transmitted data can be adjusted. Corresponding to the clock of the received data Phase to maintain a fixed phase difference with the phase of the return clock. When the master wakes up from the quiet mode, the transmitter 240 transmits the first data according to the output clock Out_Clk to avoid data corruption caused by the data being out of sync with the received data. The master's transmitter then replies to using a fixed Free Running Clock to transmit the signal.

In short, when the master device 20 wakes up from the quiet mode and transmits the first data transmission, the output clock Out_Clk phase is adjusted to correspond to the clock phase of the received data, and the transmitter 240 transmits the signal according to the output clock Out_Clk to maintain A fixed phase difference with the reply clock to avoid data loss caused by the fact that the transmitted data and the received data are out of sync.

Please refer to FIG. 3, which is a clock synchronization process 30 for a host device of an Ethernet system according to an embodiment of the present invention, which includes the following steps: Step 300: Start.

Step 302: When a master device operates in a mode switch, phase-phase adjustment data Ph_Data is generated according to the data SIN transmitted by the slave device.

Step 304: Accumulate the phase adjustment data Ph_Data to output a phase adjustment value T_ph_Data.

Step 306: Adjust the phase Out_Clk of an output clock according to the phase adjustment value T_ph_Data, so that the phase of the output clock Out_Clk and the phase of the return clock maintain a fixed phase difference.

Step 308: When the master device operates in the mode switching, transmit an initial data to the slave device according to the output clock Out_Clk.

Step 310: End.

The flow 30 is used to explain the clock synchronization operation of the main device 20 of FIG. 2, so please refer to the foregoing description for details, and details are not described herein. Therefore, by the process 30, the main device 20 After waking up from the quiet mode, the transmitter can adjust its first phase to synchronize the phase of the transmitted data.

On the other hand, regarding the implementation of the process 30, those skilled in the art can make appropriate modifications according to actual needs. For example, please refer to FIG. 4, which is a schematic diagram of a main device 40 for an Ethernet system according to an embodiment of the present invention. The main device 40 can be the main device 110 of the Ethernet system 10, and its architecture is similar to that of the main device 20 of FIG. 2, except that after the receiver 410 receives the phase adjustment data Ph_Data, the phase-locked loop unit 420 adjusts the output immediately. The phase of the pulse Out_Clk. The main device 40 includes a receiver 410, a phase locked loop unit 420 and a transmitter 430. The receiver 410 operates in the same manner as the receiver 210 of the main device 20, and details are not described herein again. The phase-locked loop unit 420 is configured to adjust the clock phase of the transmitted data to correspond to the clock phase of the received data according to the phase adjustment data Ph_Data, and maintain a fixed phase difference with the reply clock when transmitting the first data, thereby avoiding The data is corrupted due to the inconsistency between the transmitted data and the received data. The master's transmitter then replies to using a fixed Free Running Clock to transmit the signal.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a receiver 50 for a main device according to an embodiment of the present invention. The receiver 50 can be the receiver 210 of the main device 20 or the receiver 410 of the main device 40, and includes a receiving end IN, a data estimating unit 510 and a digital return circuit 520. The receiving end IN is configured to receive a data transmitted by the slave device, such as the aforementioned transmission data SIN. The data estimation unit 510 can perform signal processing such as power control and channel estimation, and is mainly used to generate an error information ERRIN according to the data transmitted by the slave device. The digital recovery circuit 520 is operative to generate a phase adjustment data Ph_AD based on the error information ERRIN. The phase adjustment data Ph_AD may be the aforementioned phase adjustment data Ph_Data for generating an up (Up) or down (Dpwn) signal to indicate that the phase locked loop unit of the transmitting end adjusts the phase of the output clock.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of a main device 60 for an Ethernet system according to an embodiment of the present invention. The main device 60 operates in a quiet mode for synchronizing with a slave device, and dynamically adjusts the wake-up time by the gap between the two clocks to re-synchronize the clock. The main device 60 includes a receiver 610, a transmitter 620, a detecting unit 630, and a synchronization unit 640. Receiver 610 is configured to receive a slave device data SIN. The data SIN transmitted from the device includes phase information of the clock R_Clk from one of the devices. Therefore, after the receiver receives the data SIN, the phase information of the reply clock R_Clk can be solved by the internal circuit operation. Transmitter 620 operates on a first clock FR_Clk. Preferably, the first clock FR_Clk is a free-action clock. The detecting unit 630 is coupled to the receiver 610 and the transmitter 620 for detecting a clock phase difference between the master device and the slave device according to the first clock FR_Clk and the reply clock R_Clk. The synchronization unit 640 is configured to compare the clock phase difference Ph_Delta with a tolerance value X. When the clock phase difference exceeds the tolerance value X, the control master device 60 performs a program synchronized with the slave device. The program synchronized with the slave device includes the master device 60 transmitting an idle sequence (Idle Sequence) to the slave device. From the device, the clock is synchronized and synchronized by the received idle sequence.

For example, the tolerance value X is set to 5 clock cycles. In this case, when the pulse phase difference Ph_Delta exceeds 5 phase differences, the master device 60 wakes up from the quiet mode and transmits an idle sequence to the slave device. From the device, the clock is synchronized and synchronized by the received idle sequence. Conversely, when the pulse phase difference Ph_Delta does not exceed 5 clock cycles, the main device 60 continues to maintain a quiet mode to save power. Therefore, the main device 60 can dynamically adjust the wake-up time to avoid power consumption problems caused by abnormal wake-up.

Please refer to FIG. 7. FIG. 7 is a flowchart of a clock synchronization process 70 for a host device 60 of an Ethernet system according to an embodiment of the present invention, which includes the following steps: Step 700: Start.

Step 702: Receive a slave device data SIN.

Step 704: Detect a clock phase difference Ph_Delta between the master device and the slave device according to a first clock FR_Clk and a reply clock.

Step 706: Compare the clock phase difference Ph_Delta with the tolerance value X, and control the main device to execute a program synchronized with the slave device.

Step 708: End.

The process 70 is used to explain the clock synchronization operation of the main device 60 of FIG. 6. Therefore, please refer to the foregoing description for details, and details are not described herein. Thus, by flow 70, the master dynamically adjusts the wake-up time to resynchronize the clock.

Please refer to FIG. 8. FIG. 8 is a schematic diagram of a slave device 80 for an Ethernet system according to an embodiment of the present invention. The slave device 80 is used to improve the synchronous power consumption problem of the Ethernet system. The slave device 80 includes a receiver 810, an arithmetic unit 820, a timing adjustment unit 830, and a transmitter 840. The receiver 810 is configured to receive an idle sequence Id1_Seq of the primary device, where the idle sequence Id1_Seq includes free running clock information from one of the primary devices. The operation unit 820 is coupled to the receiver 810 and generates a phase difference information PDD according to the idle sequence Id1_Seq. The transmitter 840 is configured to transmit data to the main device according to an output clock Out_Clk. The timing adjustment unit 830 is coupled to the operation unit 820 for adjusting the output clock Out_Clk according to the phase difference information PDD. When the master device wakes up from the quiet mode at intervals to transmit an idle sequence Id1_Seq to maintain synchronization, the slave device 80 receives the idle sequence Id1_Seq and knows the clock information of the master device contained therein. Through the arithmetic unit, the phase difference between the clock of the data currently transmitted by the transmitter 840 and the clock information of the master device is calculated to generate the phase difference information PDD. When the phase difference information PDD is greater than the threshold value Y, the timing adjustment unit 840 adjusts the clock of the transmission data to correspond to the clock information included in the idle sequence Id1_Seq. Such as In this way, the time interval for the master device to send the idle sequence Id1_Seq can be extended to avoid the power consumption problem caused by the main device often waking up from the quiet mode and achieve the purpose of synchronization.

Please refer to FIG. 9. FIG. 9 is a flowchart of a method for improving synchronous power consumption in a slave device 80 of an Ethernet system according to an embodiment of the present invention, which includes the following steps: Step 900: Start.

Step 902: Receive an idle sequence Id1_Seq of one of the master devices.

Step 904: Generate a phase difference information PDD according to the idle sequence Id1_Seq.

Step 906: Adjust an output clock Out_Clk according to the phase difference information PDD.

Step 908: Transmit data to the host device according to the output clock Out_Clk.

Step 910: End.

The process 90 is used to describe the main device 80 of FIG. 8. Therefore, please refer to the foregoing description for details, and details are not described herein. Therefore, by the process 90, the master device controls the time interval for transmitting the idle sequence to achieve the purpose of power saving synchronization.

In summary, in the embodiment of the present invention, the main device adds a set of phase-locked loops, and when the main device wakes up from the quiet mode, when the first data is transmitted, the clock of the adjustable initial phase is oscillated to correspond to the receiving. The clock phase of the data maintains a fixed phase difference. In this way, the problem that the master device and the slave device must be asleep together or the asymmetric mechanism cannot be synchronized in the prior art is improved, thereby achieving the purpose of power saving. In addition, by changing the wake-up mechanism, the main device can be sent to the idle time interval to avoid the power consumption problem caused by the sudden wake-up from the quiet mode.

20‧‧‧Main device

210‧‧‧ Receiver

220‧‧‧transmitter

230‧‧‧ phase-locked loop unit

240‧‧‧ register

SIN‧‧‧Transfer information

Ph_Data‧‧‧ phase adjustment data

T_Ph_Data‧‧‧ phase adjustment value

Out_Clk‧‧‧Output clock

Claims (12)

A slave device for improving synchronization power consumption in an Ethernet system, the Ethernet system includes a master device, and the slave device includes: a receiver for receiving an idle sequence of the master device a transmitter for transmitting data to the host device according to an output clock; an arithmetic unit coupled to the receiver for generating a phase difference information according to the idle sequence; and a timing adjustment unit, And being coupled to the operation unit, configured to adjust the output clock according to the phase difference information; wherein, when the master device is switched from a quiet mode to an awake mode, the output clock of the slave device and a reply time The phase of the pulse maintains a fixed phase difference. The slave device of claim 1, wherein the Ethernet system is a Giga Ethernet system. The slave device of claim 1, wherein the idle sequence includes clock information corresponding to one of the master devices. The slave device of claim 1, wherein the timing adjustment unit adjusts the second clock to correspond to the clock information when the phase difference information is greater than a first threshold. A method for improving synchronous power consumption in a slave device of an Ethernet system, the Ethernet system including a master device, the method comprising: receiving an idle sequence of the master device; a sequence, generating a phase difference information; adjusting an output clock according to the phase difference information; Transmitting data to the main device according to the output clock; wherein, when the main device is switched from a quiet mode to an awake mode, the output clock of the slave device maintains a fixed phase difference with a return clock phase . The method of claim 5, wherein the Ethernet system is a Giga Ethernet system. The method of claim 5, wherein the idle sequence includes clock information corresponding to one of the master devices. The method of claim 5, wherein the timing adjustment unit adjusts the second clock to correspond to the clock information when the phase difference information is greater than a threshold. An Ethernet system includes: a main device, comprising: a first receiver for receiving a data; and a first transmitter for transmitting an idle sequence; and a slave device comprising: a second receiver for receiving the idle sequence of the master device; a second transmitter for transmitting the data according to an output clock; an arithmetic unit coupled to the second receiver for And generating, according to the idle sequence, a phase difference information; and a timing adjustment unit coupled to the operation unit, configured to adjust the output clock according to the phase difference information; wherein, when the master device is switched from a quiet mode to a In an awake mode, the output clock of the slave device maintains a fixed phase difference with the phase of a return clock. For example, the Ethernet system described in claim 9 wherein the Ethernet system is a Giga Ethernet system. The Ethernet system of claim 9, wherein the idle sequence includes clock information corresponding to one of the master devices. The Ethernet system of claim 9, wherein the timing adjustment unit adjusts the second clock to correspond to the clock information when the phase difference information is greater than a first threshold.