TWI489301B - Circuits for soft logical functions - Google Patents

Description

Circuit for soft logic function Cross-references for related applications

The present application claims the advantages of U.S. Provisional Application Serial No. 61/156,794, filed on March 2, 2009, which is incorporated herein by reference.

This application is related to U.S. Provisional Patent Application Serial No. 61/156,721, filed on March 2, 2009, entitled "Signal Mapping", and US Provisional Patent entitled "Belief Propagation Processor", dated January 11, 2010. U.S. Provisional Patent Application Serial No. 61/156,721, entitled "Belief Propagation Processor", filed on Serial No. 61/293,999, filed on March 2, 2009. The contents of the above application are incorporated herein by reference.

The present application also has a U.S. Provisional Patent Application Serial No. 61/156,735, entitled "Circuits for Soft Logical Functions", filed on March 2, 2009.

Field of invention

This application is related to statistical processing circuitry, including, for example, circuitry that performs soft logic functions.

Background of the invention

Statistical inferences use statistical data to make assertions based on incomplete or inaccurate information. It can be used in applications that need to self-observe data that is distorted in some way. For example, in a communication system, data transmitted via a communication channel, for example in the form of a radio signal, can be distorted by noise, interference and/or reflection. Upon receipt of the radio signals, a receiver will utilize statistical inference to obtain and process soft (probabilistic) information to recover the originally transmitted signal from the distorted signals.

In some implementations, the processing of soft information can be implemented in an analog domain, such as by using a continuous time statistical processing circuit that performs soft logic functions such as soft equal or soft mutex or soft logic functions. In some examples, such analog circuits are constructed using conventional translinear circuitry (eg, adders or multipliers) in which the probability distribution represented by the current signal can be added in the linear domain. And / or multiply. Some of these translinear circuits are assembled by utilizing the IV characteristics of the exponential form of a particular type of transistor, such as a metal oxide semiconductor field effect transistor (MOSFET) operating in a subcritical region and dual loading. Subjunction transistor (BJT).

Summary of invention

At one level, in general, a circuit implementing a software logic processing network includes one of analog processing elements including soft logic gates including one or more soft equal gates, Each soft equal gate includes a plurality of circuit portions, each portion including an input that is configured to receive a voltage signal representation of a soft multi-level number; and a conversion portion that is configured to represent the received voltage A current signal representation corresponding to one of the number of soft logics. Each soft equal gate further includes a signal combining portion coupled to the converting portions of the plurality of circuit portions and configured to form a signal representation of a sum of the number of the soft logics represented by the current signals And an output for providing a signal formed by the combined portion of the signal.

The level may include one or more of the following features.

The voltage signals represent representations that each comprise a corresponding probability value substantially based on a logarithm.

The voltage signals represent representations that each comprise a probability ratio substantially based on a logarithm.

In each circuit portion, the input is configured to receive a differential voltage signal representation of one of the number of soft logic on the plurality of signal lines.

Each of the signal lines is coupled to a transistor corresponding to one of the conversion portions that is configured to operate in a super-threshold mode, the transistors providing the soft logic represented by the received differential voltage signal The quantity is substantially proportional to one of the differential current signals.

In each circuit portion, the transistors that provide the differential currents are coupled to a current regulating component to regulate a sum of the currents provided by the transistors.

Each of the transistors is coupled to the current regulating element via a resistive element.

The resistive elements are controllable to affect one of the input and output characteristics of the soft equal gate.

The input to output characteristic includes a linear characteristic.

Each of the resistive elements includes a MOS transistor that is assembled to function in a linear region.

The signal combining portion includes a signal conductor that couples the converting portions of the converting portions and provides a differential current signal substantially equal to a combination of one of the sums of the differential currents provided by the converting portions .

The signal combination portion includes a current to voltage conversion element, and the signal representation of the sum of the number of soft logics includes a differential voltage representation.

The signal combining portion further includes a signal conductor coupled between the conversion portion and the current to voltage conversion element.

In each circuit portion, the input is configured to receive an M-th order voltage signal representation of the number of soft logics on the plurality of signal lines, the number of soft logics representing one of a plurality of classes.

The soft logic processing network implements a factor graph.

The soft logic gates further include one or more soft mutex or gates, each soft mutex or gate coupled to one or more of the soft equal gates.

In another aspect, in general, a circuit implementing a soft logic processing network includes one of analog processing elements including soft logic gates that include one or more soft logic gates Each soft logic gate includes a plurality of circuit portions, each portion including an input that is configured to receive a voltage signal representation of a soft logic quantity; and a conversion portion that is assembled to utilize the received voltage Represents the formation of a current signal that is dependent on one of the number of soft logics. In at least a first circuit portion of the plurality of circuit portions, the conversion portion is configured to convert the received voltage representation to provide a current signal representation corresponding to one of the number of soft logics. In at least one second circuit portion of the plurality of circuit portions, the switching portion is configured to combine the received voltage representation with a current signal representation provided by another of the circuits to provide a current signal Said. The soft logic gate further includes the conversion portion coupled to one or more of the circuits to form a current signal representation of one of the outputs of the soft logic gate.

The level may include one or more of the following features.

The voltage signals represent representations that each comprise a corresponding probability value substantially based on a logarithm.

The voltage signals represent representations that each comprise a probability ratio substantially based on a logarithm.

The logic function is selected from the group consisting of a phase and a function, a function, a NAND function, and a mutual exclusion or function.

At least one of the soft logic gates is configured to implement a gate selected by the group consisting of a soft logic and a gate, a soft logic or gate, a soft logic and a non-gate, and a soft mutex or gate.

At least one of the soft logic gates is configured to implement a gate selected from at least two of a soft and a gate, a soft or a gate, a soft and a non-gate, and a soft mutex or gate .

In each circuit portion, the input is configured to receive a differential voltage signal representation of one of the number of soft logic on the plurality of signal lines.

Each signal line is coupled to a transistor that is associated with one of the switching portions that are configured to operate in a high threshold mode.

The transistors of the first circuit portion are combined to provide a differential current that is substantially proportional to the number of soft logics represented by the received differential voltage signal.

The transistors of the second circuit portion are assembled to provide an amount represented by the number of the soft logic represented by the received differential voltage signal and the current signal provided by the other of the circuit portions One of the products is substantially proportional to one of the differential currents.

The signal combining portion is configured to form a current signal representation that is substantially proportional to the product of one of the received soft logic numbers, whereby the logic gate implements a soft mutual exclusion or function.

The conversion sections each include a differential amplifier.

At least some of the differential amplifiers each comprise a group of power distribution group elements that control one of the characteristics of the differential amplifier.

The circuit further includes a plurality of memory elements, the plurality of memory elements providing the voltage signals represented by at least some of the soft logic gates receiving the soft logic number.

At another level, in general, a memory includes a plurality of electrical storage elements, each of which carries a respective stored value. The memory further includes a plurality of conversion elements, each of the conversion elements coupled to a respective electrical storage element to selectively convert the corresponding stored value into a current signal. A current combining component is used to combine the current signals to form an output signal.

The level may include one or more of the following features.

Each conversion element includes a current converter and a switching element.

The switching element is assembled to be driven by a selection signal.

The memory further includes a control circuit for generating the selection signal based on an input.

The input includes a specification of one of a subset of the electrical storage elements to be accessed.

The plurality of electrical storage elements includes a plurality of charge storage elements each carrying a charge.

Each charge storage element includes a capacitive element.

Each of the conversion elements includes a transistor-based circuit for selectively converting a respective charge into a corresponding current signal.

The output signal provides one of the combinations of the current signals for continuous value encoding.

The output signal represents a combination of the selected stored values.

The output signal includes one of the signals encoded by the different currents.

In general, other aspects relate to a memory comprising a group of electrical storage elements, each electrically storage element carrying a respective stored value; a plurality of conversion elements each coupled to a respective electrical storage element for selective Converting the corresponding stored value into a current signal; and a current combining component for combining the current signals to form an output signal.

Embodiments may include one or more of the following features.

Each conversion element can include a current converter and a switching element. The switching element can be assembled to be driven by a selection signal. The memory can further include a control circuit for generating one of the selection signals in accordance with an input. In some examples, the input includes one of the specifications of the one of the electrical storage elements to be accessed.

The group of electrical storage elements can include a plurality of charge storage elements each carrying a charge. Each charge storage element can include a capacitive element (eg, a pair of capacitors). Each of the conversion elements can include a transistor-based circuit (e.g., a differential amplifier) for selectively converting a respective charge into a corresponding current signal.

The output signal of the memory can provide one of the combinations of the current signals for continuous value encoding. In some examples, it represents a combination of one of the selected values. In some examples, the output signal includes one of the signals encoded by the differential current.

Other features and advantages of the invention will be apparent from the description and appended claims.

Simple illustration

Figure 1 is a circuit schematic of one embodiment of a soft equal gate.

Figure 2 is a circuit schematic of a second embodiment of a soft equal gate.

Figure 3 is a circuit schematic of a third embodiment of a soft equal gate.

Figure 4 is a circuit schematic of a fourth embodiment of a soft equal gate.

Figure 5 is a circuit schematic of a fifth embodiment of a soft equal gate.

Figure 6 is a circuit schematic diagram of one embodiment of a soft mutex or gate.

Figure 7 is a block diagram of a memory.

Figure 8 is a circuit schematic diagram of one embodiment of the memory in Figure 7.

Figure 9 is a diagram of one embodiment of other types of soft gates.

Detailed description of the preferred embodiment

A network of processing elements implementing logic functions for representing values in an analogous (eg, substantially continuous) form can be used, for example, in various processing methods based on probability, statistics, or understanding, in this specification For the benefit of the discussion, these processing methods are referred to as a soft logic processing method, and the values depicted are referred to as a number of soft logics. In calculations that include such values, the analog values may represent probabilities or related quantities, such as likelihood, likelihood, confidence, or median. Soft logic processing can be used in many applications, for example, including implementing belief propagation (a form sometimes referred to as a "sum product" algorithm) by passing a message as an analog quantity to a probability graph model (eg, a factor) Figure) and operate.

Circuitry for continuous time soft logic processing can be fabricated using analog components. In some examples, in such a circuit, the probability distribution is a voltage or current that is processed in the linear domain by an addition and/or multiplication operation implemented in a network of analog processing elements (ie, utilization probability) Expressed in relation to the substantial proportional relationship between voltage and/or current values. The following description focuses on analog processing elements suitable for forming nodes in a soft logical processing network, for example, each implementing a soft logical operation, including soft equality, soft mutual exclusion, soft and soft OR, (optionally "soft logic gates" or "soft gates" that accept multiple soft probability representations (eg, expressed as an analogy) and output one of the results as a soft probability (eg, the same or a different representation) .

In some examples, it may be useful to process a quantity based probability in a logarithmic domain or some other continuous and substantially monotonic transform domain in a non-linear domain. For example, the analog input and output of the circuit components approximate the log probability ratio (LLR) representation of the probability distribution. Other compression and/or double bend conversions of probability can also be used.

In some examples, as described below, the amount of soft logic can be represented as utilizing multiple analog signals, for example, as different currents or different voltages for signal links to each quantity, or in some embodiments, Use more links than the two signal links.

The following description provides some examples of soft gate circuits that are assembled using this method.

1 soft equal gate

1.1 Soft equal gates with variables of binary values

In a fully digital circuit that processes binary data, the inputs and outputs of a logic gate are either 0 or 1. Through a class of logic gates (or a soft gate), the inputs and outputs represent probabilities or possibilities and can vary between 0% and 100%, with a constraint that the probability of all possible outputs is 100% in total.

In some embodiments, a three-variable soft equal gate performs the following functions:

Where x and y are input variables, Z is the output variable, and γ is the normalization factor such that P ( Z =0)+ P ( Z =1)=1. Here, each variable assumes two possible values, namely 0 and 1, and the probability distribution of each variable (such as the variable x ) is represented by, for example, P ( x =0), P ( x =1). In some examples, the two input variables x and y may represent two independent observers, each of which provides an estimate of one of the output variables Z.

In some examples, one of the soft gates in a factor graph is bidirectional. More specifically, the edge entering or leaving the soft gate is actually bidirectional and one of the more than three variables can be implemented with three one-way soft gates, each gate receiving two input variables to produce an output variable.

One embodiment of the soft equal gate described above utilizes a cross-conductor multiplier, in which case the probability distributions of the input variables are multiplied as current encoded signals in the circuit to form the input P ( Z = 0), P ( Z =1).

Another embodiment of the soft equal gate utilizes the sum of the currents in the log probability ratio (LLR) state. More specifically, given equations (1a) and (1b), one can obtain:

Convert equation (2) to the logarithmic domain, giving the following:

By using "LLR" to represent the log probability ratio of a binary variable, such as for a variable x Equation (3) can be rewritten as:

LLR _Z = LLR _x + LLR _y (4)

In other words, the output of the LLR Z by the variable can be added to the variable x such input LLR y of those obtained.

Now consider, in a more specific case, an output variable Z with N ( N 2) Independent observers are conditional, each of which produces an estimate of P ( Z = 0), expressed as P ₁ ,..., P _N . Give the following observations,

The LLR of the variable Z can be expressed as:

In essence

In other words, the LLR of the output variable Z can be obtained by summing the individual LLRs of the observers. This can be implemented using an adder circuit in which the input and output respectively represent (or approximate) the input LLR and the output LLR.

Figure 1 shows an example of a circuit structure 100 that utilizes a sum of currents to operate a four-variable (i.e., three-input) soft equal function. Note that in factor-based applications, a four-variable soft equal gate will involve calculating all four variables, each of which is calculated using the other three variables.

These four calculations can be implemented in a set of four circuits, each receiving three variables to produce the fourth variable. The examples described below implement one of four circuits. The other three circuits are assembled using the same technique, but the input and output variables are changed.

Here, the circuit 100 includes three different pairs of circuits 110, 120, and 130, each of which receives a respective input signal (in the form of a different voltage) to form a signal that is substantially proportional to the input (at different currents) Form). For example, in circuit 110, a different voltage signal Δ v ₁ (i.e., v ₁ ⁺ - v ₁ ^- ) is provided as an input to circuit 110 to produce a different current signal Δ i ₁ (i.e., i ₁ ⁺ - i ₁ ^- )), which is proportional to the voltage Δ v ₁ . The current signals of all three circuits 110, 120 and 130 are then summed to produce a circuit output Δ I _OUT (Δ v ₁ + Δ v ₂ + Δ v 3).

In this circuit 100, each of the three input different voltage signals can represent (e.g., have a magnitude of scaling) an additional input LLR. Thus, the output Δ I _OUT can represent an output LLR that is the sum of the three input LLRs, as shown in equation (6).

Note that when assembled to receive inputs and outputs in the form of the LLR, the circuit 100 operates effectively as a soft equal gate that does not require multiplication by current summing. This provides several advantages over traditional soft equal gates that utilize the cross-wire approach. For example, the method allows for increased fan-in (i.e., the number of inputs for a logic gate) without increasing the supply voltage VDD or the number of components (e.g., transistors) used in the circuit. In contrast, some cross-conductor soft equal gates may require the designer to 1) stack the voltages of the transistors or 2) use current mirror overlap to add fan-in. In this first case, the number of transistors required in the cross-wire method grows faster than the method. In this second case, the current mirror can be referred to as one of the bottlenecks for speed, for example, when there is a small current due to their capacitance.

Another advantage of this method is the simplicity of the hardware configuration, since current summation is actually one of the cheapest and accurate available analog operations. Since soft equal gates are ubiquitous in statistical processing (ie, factor graph based processing), the efficient design of soft equal gates allows for improved overall circuit efficiency.

A third advantage is that the actual transfer function of one of the soft equal gates is very similar to the mathematical transfer function of the design (ie, the sum of the LLRs) because the current is effectively linearly added according to the Cosiehoff current law (KCL). In the circuit.

Figure 2 shows another example of a circuit structure 200 that is operable to perform a four variable soft equal gate function. Here, instead of outputting a different current signal Δ I _OUT , the circuit 200 forms a different voltage signal Δ V _OUT representing the output LLR using a pair of resistive loads. The three input LLRs are again represented by different voltage signals Δ v ₁ , Δ v ₂ and Δ v ₃ , respectively.

Figure 3 shows a third example of one of the circuit structures 300 operable to perform a four variable soft equal function. Here, the circuit 300 receives three different voltage signals representing three input LLRs to produce an output differential voltage signal representative of one of the output LLRs. In some applications, the use of a cathode structure 340 at the output can improve certain aspects of circuit performance, such as increasing the input-output isolation voltage and increasing the circuit bandwidth.

Note that Figures 1 through 3 are schematic diagrams of circuits that can be operated as soft equal gates (using analog components). Various alternative power designs are possible, including, for example, circuits having structures similar to those described above but with additional active and/or passive circuit components such as resistors and transistors.

For example, Figure 4 shows a variation of the circuit structure 100 shown in Figure 1. In this example, each of these different (e.g., circuit 410) comprises a circuit of transistors are coupled to the T _{T. 1} and one of the _{two pairs} of fixed resistors R ₁ and R _2. In some applications, the presence of such resistors in the different pairs of circuits increases the linearity of the circuit transfer function. Such variations are similarly applicable to the circuit structures shown in Figures 2 and 3.

Figure 5 shows another example of a circuit 500 that is operable to perform a four variable soft equal gate. Here, each of these different (e.g., circuit 510) comprises a pair of circuits can be set with the resistive element, such as a transistor are respectively coupled to the T R ₁ and T ₂ of ₁ and R _2. The composable resistive elements can be passive resistors (e.g., variable resistors) or, alternatively, active components that function as resistors. One example of an active component suitable for use herein is the biasing of one MOS transistor in the triode region as a resistor. In some examples, the configurable resistive elements R ₁ and R ₂ can have varying IV characteristics that are controlled by an applied signal, such as a signal provided by a controller 540. In some applications, the configuration of the resistive elements causes the different pair of circuits and/or the effective transfer function of the entire circuit 500 to be adjusted as needed.

Other examples of soft equal gates are described in U.S. Provisional Patent Application Serial No. 61/156,735, filed on March 2, 2009, entitled "Circuit for Soft Logical Functions".

1.2 Soft equal gates with variables of order M

Although the above description illustrates soft equal gates for processing variables of binary values, such general techniques can be easily extended to handle M-order variables, i.e., variables having m possible values, where m > For purposes of illustration, an example of a circuit that can be used as a soft equal gate operation to process m-th order variables is briefly described below.

Assume that a random variable Z can have m possible values, namely 1,..., m . The probability of having Z for each of these values can be obtained using N independent observers, each of which can provide an estimate of these values. For example, the ith observer gives a probability distribution expressed as p _i ( Z =1), p _i ( Z = 2), ..., p _i ( Z = N ).

The probability that the variable Z is 1 is:

P(Z =1 ) = γ. p ₁ (Z =1 )p ₂ (Z =1 ) ... p _N (Z =1 ) (7)

And P ( Z = 2) is similar, and so on, where γ is a normalization factor, indicating

Select the probability of a variable as a reference, for example, P ( Z = m ). For any k value, 1 of them The logarithmic probability of k < m , P ( Z = k ) with respect to P ( Z = m ) is obtained as follows:

Where LLRz _k represents the LLR having the value k with respect to the variable Z of the reference m , LLR _i,k representing the LLR having the value k with respect to the ith observation of the reference m . Note that, similar to equation (6), equation (9) can be implemented by summing, for example, using circuits similar to those of the first to fifth figures to obtain m - 1 k values. One of the LLRz _k .

2 soft mutex or gate

2.1 Soft Mutual Rejection or Gate with Variables of Binary Value

In some embodiments, one of the two logic circuits in a complete logic circuit is mutually exclusive or the gate performs a two-plus-add function. In this analog domain, a three-variable soft mutex or gate can perform the following functions:

Where x and y are input variables and z is an output variable. Here, each variable assumes two possible values, namely 0 and 1. This three-variable soft mutex or function can also be expressed as Z = x ⊕ y .

The soft mutex or gate represented by equations (10a) and (10b) can be implemented in the LLR system using the following techniques.

Given a variable one x LLR, ie, The differential probability of this variable (ie P ( x =0) - P ( x =1)) is actually equal to tanh ( LLR _x /2, as shown below:

Similarly, for the variable y , one is available:

Tanh(LLR _y / 2 ) = P(y =0 )-P(y =1 ) (12),

And for the variable Z, one is available:

Tanh( LLR _Z /2)= P ( Z =0)- P ( Z =1) (13)

Note that tanh ( LLRz /2) can be rewritten using equations (10a) and (10b) as follows:

Tanh( LLR _Z /2)= P ( Z =0)- P ( Z =1)=( P ( x =0)‧ P ( y =0)+ P ( x =1)‧ P ( y =1) )-( P ( x =0)‧ P ( y =1)+ P ( x =1)‧ P ( y =0))=( P ( x =0)- P ( x =1)) ‧( P ( y =0)- P ( y =1)) (14)

Further generating by using equations (11) and (12)

Tanh(LLR _Z / 2 ) = tanh(LLR _x / 2 ) ‧ tanh(LLR _y / 2 ) (15)

Thus, given LLR _x and LLR _y as inputs to a soft mutex or gate, the output LLR _z can be expressed as

L LR _Z =2‧ tanh ^-1 ( (tanh(LLR _x / 2 ) ‧ tanh(LLR _x / 2 ) ) (16)

This describes one of the theoretical three-variable soft mutex or function in the LLR domain.

Figure 6 depicts an example of a circuit 700 that is operable to approximate the theoretical soft mutex or function shown in equation (16). Here, the gate 700 receives two differential input signals Δ x and Δ y (both in voltage form) to produce an output differential signal Δ I _OUT (in current form). Structurally, the gate 700 includes two input portions. The first input portion includes a differential amplifier 710 that receives a first differential voltage input Δ _x to form a differential current signal Δ i ₁ (ie, i ₁ ⁺ - i ₁ ^- ), Δ i _{1 is} approximately One of the first inputs is a tangent (or double bend) function, ie Δ i ₁ Tanh(Δ _x ). The second input portion includes a pair of differential amplifiers 720 and 730 each receiving a second differential voltage input Δ _y . The outputs of the pair of differential amplifiers are connected such that the differential output Δ I _OUT (i.e., i ₂ ⁺ - i ₂ ^- ) of the circuit 700 approximates a tangent (or double bend) function of the second input, i.e., Δ i _OUT Tanh(Δ _x ). Note that each of the transistors in the second input portion also receives one of the differential currents i ₁ ⁺ , i ₁ ^- generated by the differential amplifier 710 at its source terminal. Therefore, the differential output Δ I _{OUT of} the circuit 700 is also resized by Δ i ₁ , which is given by:

For inputs and outputs that fall within the typical operating range of the circuit 700, the tanh ^-1 function can approximate a linear function whose output increases approximately proportionally to the input. In other words, tanh ^-1 ( v ) k ‧ v . Therefore, the gate output Δ I _{O UT} can be seen as follows:

Note that equation (18) is similar to equation (16). Indeed, when the input circuit 700 of the differential Δ x and Δ y respectively (e.g., proportional to the magnitude was provided) when the LLR _x / 2 and the LLR _y / 2, the output of the circuit 700 of differential Δ I _OUT approximates the LLR _z, the LLR _z as equation (16) of the definition of LLR _x / 2 and the soft LLR _y / 2 of the XOR gate function. In other words, the actual transfer function of the circuit 700 approximates the theoretical soft mutex or gate in the LLR domain.

In some cases, the similarity of the actual circuit transfer function to the theoretical soft repulsion or function can be improved, for example, by controlling the resistive elements in the circuit. For example, each of the differential amplifiers 710, 720, and 730 in the circuit includes a pair of variable/controllable resistive elements (such as R ₁ and R ₂ ), and the resistivity of the variable/controllable resistive element will Affects the transfer function of the differential amplifier. By varying the resistivity of selected or all resistive elements, the actual circuit transfer function can be assembled to closely approximate the theoretical soft mutex or function in the LLR domain.

For the differential amplifier 710, when R → 0, its transfer function acts as a double bending function, and when R becomes larger than the differential amplifier The transfer function of the differential amplifier 710 effectively becomes an upper limit linear function. In some applications, such separate resistance element to change (such as R ₁ and R ₂₎ The resistivity is useful to achieve a differential amplifier for a particular one of the desired transfer function. In some applications, it is also useful to control the resistive elements in more than one differential amplifier such that the circuit 700 can provide a combined transfer function that is similar to the theoretical soft mutual in the LLR domain. Repel or brake. The resistive elements in the gate circuit can take a variety of forms, such as passive resistors or transistors that exhibit resistors in some configurations.

Note that similar to the soft equal gate, the soft mutex or gate described herein can also be combined in a variety of alternative ways. One example is a variation of circuit 700 that utilizes one of the outputs to generate a differential voltage output signal to the resistive load in place of a differential current output signal.

The above description illustrates a circuit element operable to implement one of the three variable soft mutex or gates in the LLR domain. In some examples, a larger N-variable (N>3) soft mutex can be implemented based on a small 3-variable soft mutex or gate-related function collection as described below.

Assume that x ₁ , x ₂ ,... x _{N - 1} are N-1 number of independent observers, each of which estimates the value of the variable x _N . An N-variable soft mutex or gate performs a modulo-2 summation operation on these N disguised phases as follows:

By introducing a new set of variables y ₂ ,... y _{N -1} , equation (19) can be represented by a new set of equations containing only one of the three variables:

In a hardware configuration, this means that an N-variable soft mutex or gate can be broken down into a series (or a tree) of central modules, each central module generating one of the output signals based on two input signals. Soft Mutex or, when implemented in the LLR domain, an N variable soft mutex or may be constructed using a series of 3 input soft mutex or gate as shown in Figure 6. For example, based on equation (15), one can get

An N-variable soft mutex or gate may be combined to generate an output differential signal representative of the LLRx _N by connecting the N-1 input portions in a series manner, wherein each input portion receives a representation corresponding to Enter LLRx _i (1 A differential voltage input of i < N ). In this manner, the fan-in of a soft mutex or gate can be improved by introducing another 3 variable soft mutex or gate into the circuit.

3 other types of soft gates

The methods and techniques described above are not limited to soft equals and soft mutex or gates, and can be easily extended to other types of operations, such as soft or soft. Some examples of trivariate soft gate operation can be described by the following equation, which illustrates a circuit component of the three variable soft gate that receives X and Y as two input variables to produce Z as an output variable. .

In some applications, various types of soft gates can be assembled using the techniques described above. Figure 9 illustrates a diagram of one of the core circuits that can be combined to implement different soft gates. For example, the circuit includes four output conductors, each having a current corresponding to one of a pair of inputs (ie, X ⁺ Y ^- , X ⁺ Y ⁺ , X ^- Y ⁺ , X ^- Y ^- ). The output of a soft gate can be obtained by combining the appropriate sets of output conductors. For example, the Z ⁺ of the NAND gate can be obtained by connecting X ⁺ Y ^- , X ^- Y ⁺ , X ^- Y ^- wires, and the Z ^- of the NAND gate can be obtained by the X ⁺ Y ⁺ Wire formation. Other soft brakes can be assembled using the same method.

4 applications

4.1 analog memory

One application of such soft shutters described herein relates to data storage, for example, for extracting stored values from a class of memory. In some embodiments, it is useful to perform a soft equal gate operation in reading an analog memory device having an analog memory device in a subset of the selected memory cells. As mentioned above, one way to perform a soft equal gate is to utilize current summation in the LLR domain. In the memory application, this can be generated by forming a current signal representative of the stored values of a selected set of memory cells and then summing the current signals (the output can be further provided to a soft Mutually exclusive or gates are used for error correction).

Figure 7 shows an example of a memory device 900 coupled to a soft equal gate for extracting stored values. The memory device 900 includes a set of storage elements, such as 910A-C, each of which is configured to carry a respective stored value. The storage elements can be capacitive elements (eg, capacitors) or other types of energy storage elements (eg, electromagnetic elements). Each storage element can be assembled into a memory unit. In some applications, the memory cells store analog values that represent such messages that are passed between the soft logic gates that are part of a belief propagation calculation. Further discussion of the present application is provided by U.S. Provisional Patent Application Serial No. 61/293,999, entitled "Belief Propagation Processor", filed on Jan. 11, 2010, and entitled "Belief Propagation Processor", issued March 2, 2009. U.S. Provisional Patent Application Serial No. 61/156,721.

To retrieve the stored value in a selected storage element 910, a transform element 920 is configured to convert the corresponding stored value into a current signal. The current signals representing the stored values of the selected storage elements are then combined (eg, summed) by a current combining circuit 930 (eg, a circuit including a common bus) to produce an output. A signal that is actually a soft equal output of one of the selected stored values.

In some examples, each of the transform elements 920 includes a converter 920 (eg, a transistor-based converter for converting a charge into a current signal) and for coupling the current signal to the current One of the combination circuits 930 is a switch 924. Each switch 924 can be further configured to respond to, for example, external control of a selection signal provided by a controller 940 that specifies the physical address of the subset of storage elements 910 to be accessed in each read operation. take.

In some examples, the controller 940 is configured to receive one of a selected subset of the storage elements in each read operation to generate a selection signal to drive the respective switches such that the selected storage elements are represented The current signals of the stored values are equally operated by the soft. In some examples, the memory device can be arranged as a subset of memory cells, for example, each subset is located in a unique physical area and coupled to a respective common bus, the common bus can be associated with the memory unit The read value of the subset performs the soft equality operation. Or in other words, a subset of the memory cells that need to be fed into the same soft equal gate will be coupled to a shared hardware (eg, a common bus). In such a case, the controller 940 can have a subset identifier that points to the physical location of the corresponding subset of memory cells that are input to a common soft equal gate in each read operation. Scheduled range.

Note that in some conventional memory architectures, each memory value needs to be fetched on one of the independent output lines of the memory and then sent to an independent equal gate, as opposed to the conventional memory structure, in the method, The input stage of the soft equal gate is included in the memory to allow the stored values of the subset of memory cells to be retrieved via the shared hardware component (eg, a common bus). For example, instead of having eight individual lines respectively coupled to eight memory cells for delivering a current signal that needs to be fed into an eight-input equal gate, the current signals from the eight memory cells can be superimposed On a single line, the single line actually soft equals the stored values to produce an output signal for processing in a subsequent circuit (e.g., a soft mutex or gate). As currents from multiple lines are combined into one line, memory access will consume less power because fewer lines need to be driven.

Fig. 8 shows a detailed circuit diagram of an example of the memory unit 900. In this example, each storage element 1010A includes a pair of capacitors that carry a stored value represented by a differential voltage (or charge). Transforming element 1020A includes a differential amplifier that is switchably coupled to a current source 1050A. To read the stored value, a "read select signal" drives the switch 1024A to couple the current source 1050A to the differential amplifier, which then converts the differential voltage representing the stored value into a difference Dynamic current signal Δ i ₁ . The differential current signal is provided to the current combining circuit to combine with other differential current signals to produce an output that is actually a soft equal function of one of the selected stored values.

4.2 error correction decoder

Another application relates to soft error correction decoding, in which case the soft gates described herein can be used to perform the functions of reflecting the digital gates used in a digital decoder. Some examples of soft gates in error correction decoding are described in U.S. Patent Application Serial No. 61/156,721, entitled "Signal Mapping" and U.S. Provisional Patent Application Serial No. 61/293,999, entitled "Belief Propagation Processor." The contents of the above application are incorporated herein by reference.

5 alternative examples

In this description, the circuit examples are illustrated as being combined to process input and output signals in differential form. Note that a circuit that performs a single-ended signal is also possible. In some applications, it may be useful to employ a differential signal of excess single-ended signals in the circuit design. Advantages of the differential signal may include, for example, a large dynamic range of circuit operation and higher noise immunity (such as common mode rejection). For example, if a continuous noise is introduced into the two lines of the differential input (or output), it is possible that the design will ignore this continuous additive factor and will only echo the difference between the signals on the two lines (primary ) The gate circuit.

In some applications, it is useful that the same representation (eg, the LLR representation) is used for the input and output of each gate in a soft inference processor (eg, a soft decoder) without converting different representations. The signal between the two. In some other applications, it is also possible that a gate circuit takes an input in one of its representations (eg, a linear probability) and produces its output in another representation (eg, in LLR). In some decoders based on a bipartite graph (eg, a soft equal gate is always fed into a soft mutex or gate and vice versa), when transitioning from one representation to another (eg, from When a soft equal gate of probability conversion to LLR) is matched with a soft mutex or gate (or other constraint gate) that performs the inverse transform (eg, transition from LLR to probability), the decoders will still perform the correct Order of operation. This also applies to factor graph based inference processors other than decoders and soft gates other than soft equal gates and soft mutex or gates, as long as there is a consistent representation at each point of the graph. .

In some embodiments, there are nonlinearities associated with the circuits that feed the soft gates and other non-ideal characteristics of the circuits. Finally, this representation of each input/output may not necessarily be an LLR representation. For example, a decoder input (e.g., a signal generated by a de-correspondence circuit) may use a slightly modified LLR representation. For example, by slightly compensating for the irrational nature of the circuit, a slightly non-linear mapping from one of the LLRs to the voltage signal can perform better.

The above-mentioned soft gates can be used in statistical reasoning in which information needs to be observed from one of the data classified in some way. It can also be used in applications where information is not determined due to incomplete data sets. It can also be used in applications where different information needs to be weighted by its relevance or statistical significance, for example, in medical diagnosis.

It is to be understood that the above description is intended to be illustrative, and not restrictive of the scope of the invention as defined by the scope of the appended claims. Other embodiments are within the scope of the following patent claims.

100. . . Circuit structure, circuit

110. . . Circuit

120. . . Circuit

130. . . Circuit

200. . . Circuit structure, circuit

300. . . Circuit structure, circuit

340. . . Gate-cathode structure

410. . . Circuit

500. . . Circuit

510. . . Circuit

540. . . Controller

700. . . Circuit, gate

710. . . Differential amplifier

720. . . Differential amplifier

730. . . Differential amplifier

900. . . Memory device, memory cell

910A. . . Storage element

910B. . . Storage element

910C. . . Storage element

930. . . Current combination circuit

940. . . Controller

1010A. . . Storage element

1020A. . . Transforming element

1024A. . . switch

1050A. . . Battery

Figure 1 is a circuit schematic of one embodiment of a soft equal gate.

Figure 2 is a circuit schematic of a second embodiment of a soft equal gate.

Figure 3 is a circuit schematic of a third embodiment of a soft equal gate.

Figure 4 is a circuit schematic of a fourth embodiment of a soft equal gate.

Figure 5 is a circuit schematic of a fifth embodiment of a soft equal gate.

Figure 6 is a circuit schematic diagram of one embodiment of a soft mutex or gate.

Figure 7 is a block diagram of a memory.

Figure 8 is a circuit schematic diagram of one embodiment of the memory in Figure 7.

Figure 9 is a diagram of one embodiment of other types of soft gates.

100. . . Circuit structure, circuit

110, 120, 130. . . Circuit

Claims (28)

A circuit for implementing a software logic processing network, comprising one of a plurality of analog processing elements, the analog processing elements comprising a plurality of soft logic gates, the soft logic gates comprising one or more soft equal gates, each The soft equal gate includes: a plurality of circuit portions, each portion including: an input configured to receive a voltage signal representation of a soft logic value, and a conversion portion configured to convert the accepted voltage representation into the a current signal representation corresponding to one of the soft logic magnitudes; a signal combination portion coupled to the conversion portions of the plurality of circuit portions and configured to form the soft logic quantities represented by the current signals One of the sums of the values is a signal representation; an output for providing a signal formed by the combination of signals; wherein in each circuit portion, the input group is configured to receive one of the soft logic magnitudes on the plurality of signal lines a differential voltage signal is indicated, and each signal line is coupled to a corresponding one of the conversion portions that are configured to operate in a supercritical mode, and the transistor is provided with the received The soft logic signal indicative of the magnitude of the actuation voltage substantially proportional to one of the differential currents. The circuit of claim 1, wherein the voltage signals each represent a representation of a corresponding probability value substantially based on a logarithm. The circuit of claim 1, wherein the voltage signals are Representing one of each of the probability ratios is substantially based on a representation of the logarithm. The circuit of claim 1, wherein in each circuit portion, the transistors that provide the differential currents are coupled to a current regulating component to regulate the currents provided by the transistors. One and one. The circuit of claim 4, wherein each of the transistors is coupled to the current regulating element via a resistive element. The circuit of claim 5, wherein the resistive elements are controllable to affect one of the input and output characteristics of the soft equal gate. The circuit of claim 6 wherein the input to output characteristic comprises a linear characteristic. The circuit of claim 5, wherein each of the resistive elements comprises a MOS transistor that is configured to operate in a triode region. The circuit of claim 1, wherein the signal combining portion includes a signal conductor that couples the converting portions of the converting portions and provides substantially equal to the ones provided by the converting portions A differential current signal combined with one of the sums of the differential currents. The circuit combination portion includes a current to voltage conversion element, and the signal representation of the sum of the soft logic magnitudes includes a differential voltage representation. The circuit of claim 10, wherein the signal combining portion further comprises a tandem portion coupled between the signal conductor and the current to voltage converting element coupled to the converting portion. The circuit of claim 1, wherein in each circuit portion, the input group is configured to receive the soft logic magnitude on the plurality of signal lines One M-th order voltage signal indicates that the soft logic magnitude represents one of a plurality of categories. The circuit of claim 1, wherein the soft logic processing network implements a factor graph. The circuit of claim 1, wherein the soft logic gate further comprises one or more soft mutex or gates, each soft mutex or gate coupled to one or more of the soft equal gates . A circuit implementing a soft logic processing network, comprising one of a plurality of analog processing elements, the analog processing elements comprising a plurality of soft logic gates, the soft logic gates comprising one or more soft logic gates, each The soft logic gate includes: a plurality of circuit portions, each portion including: an input configured to receive a voltage signal representation of a soft logic value, and a conversion portion configured to utilize the received voltage representation to form a dependency a current signal of one of the soft logic magnitudes; wherein, in at least one first circuit portion of the plurality of circuit portions, the conversion portion is configured to convert the accepted voltage representation to provide one of the soft logic magnitudes Corresponding current signal representation; and wherein in at least one second circuit portion of the plurality of circuit portions, the conversion portion is configured to provide the received voltage representation with another circuit portion of the circuit portions Current signal representations are combined to provide a current signal representation; wherein the soft logic gate further includes a portion coupled to the circuits a signal combination portion of the one or more of the conversion portions to form a current signal representation of one of the outputs of the soft logic gate; and wherein at least one of the soft logic gates is at least one or a group A gate selected from a group consisting of a soft and a gate, a soft or gate, and a soft reverse gate is provided. The circuit of claim 15, wherein the voltage signals represent one of a corresponding probability value each being substantially based on a logarithmic representation. The circuit of claim 15, wherein the voltage signals each represent a representation of a probability ratio substantially based on a logarithm. The circuit of claim 15, wherein the output of the soft logic gate comprises a logic function, and wherein the logic function is selected from a function, a function, a function, and a mutual exclusion Or a group of functional components. The circuit of claim 15, wherein at least one of the soft logic gates is configured to be implemented by a soft and a soft, a soft or a gate, a soft reverse gate, and a soft mutual exclusion or One of the groups of gates constitutes a gate. The circuit of claim 15, wherein at least one of the soft logic gates is configured to be implemented by a soft and a soft, a soft or a gate, a soft reverse gate, and a soft mutual exclusion or One of the at least two groups of gates in the gate. The circuit of claim 15, wherein in each of the circuit portions, the input group is configured to receive a differential voltage signal representation of the one of the soft logic magnitudes on the plurality of signal lines. Such as the circuit described in claim 21, wherein each signal line is coupled A transistor corresponding to one of the switching sections that is configured to operate in a high critical mode is coupled. The circuit of claim 21, wherein the transistors of the first circuit portion are configured to provide a differential current, the differential current and the softness represented by the received differential voltage signal. The logical magnitude is substantially proportional. The circuit of claim 23, wherein the transistors of the second circuit portion are configured to provide a differential current substantially proportional to a product of the soft logic magnitude and a magnitude. The soft logic magnitude is represented by the received differential voltage signal, the magnitude being represented by the current signal provided by the other of the circuit portions. The circuit of claim 24, wherein the signal combination portion is configured to form a current signal representation substantially proportional to a product of the received soft logic values, whereby the logic gate implements a Soft mutual exclusion or function. The circuit of claim 15, wherein the conversion sections each comprise a differential amplifier. The circuit of claim 26, wherein at least some of the differential amplifiers each comprise one of the characteristics of the differential amplifier that can be configured to form a resistive element. The circuit of claim 15 further comprising a plurality of memory elements, the plurality of memory elements providing the voltage signals of a soft logic magnitude received by at least some of the soft logic gates Said.