TWI488428B - Lnb down conversion chip circuit, lnb down conversion chip, lnb down conversion circuit applying the lnb down conversion chip circuit and down conversion method applying the down conversion chip circuit - Google Patents

Description

LNB down-frequency chip circuit and chip, LNB frequency reduction circuit and method

The present invention relates to a circuit for signal processing a wafer, and more particularly to an LNB down-converting chip circuit. The present invention relates to an LNB down-converting wafer. The invention also relates to a signal processing circuit, and more particularly to an LNB down frequency circuit. The invention also relates to an LNB down-clocking method.

LNB, the Low Noise Block, commonly known as the high frequency head, is a device placed at the reflection focus of the satellite receiving antenna to amplify and downconvert the satellite signal.

Most of the current LNBs use discrete components, including high frequency amplifying transistors, passive bandpass filters, dielectric oscillators, mixers, intermediate frequency amplifiers, voltage regulators, bias circuits, negative voltage generation circuits, and 22 kHz detection circuits. The composition is as shown in Figs. 1 and 2.

The disadvantages of the traditional scheme are:

1. The dielectric oscillator has a large temperature drift characteristic, so the frequency stability of the LNB is not high.

2. A passive bandpass filter is needed to filter out the signals outside the band, especially the mirrored portion, which has improved the noise performance of the LNB. The bandpass filter has attenuation characteristics while occupying precious plate area.

3. Since the LNB is generally small in size, a large number of discrete components cause great inconvenience to maintenance and commissioning.

The technical problem to be solved by the present invention is to provide an LNB down-converting chip circuit, a chip using the LNB down-converting chip circuit, an LNB down-converting circuit using the LNB down-converting chip circuit, and an LNB down-converting using the LNB down-frequency chip circuit. The method can have a high image rejection function, can save valuable plate space occupied by the band pass filter, and ensure excellent noise performance of the LNB.

In order to solve the above technical problem, the technical solution of the LNB down-converting chip circuit of the present invention comprises: a pre-amplifier, receiving an intermediate-stage high-frequency amplified output of the front-end circuit, and improving a noise figure of the chip to avoid deterioration of noise of the entire LNB system, At the same time, the single-ended signal sent by the intermediate stage high-frequency amplification is converted into two differential signals to improve the common mode noise suppression performance of the chip. The two differential signals are the first differential signal of 0° phase and the first phase of 180° phase. Two differential signals; a four-phase voltage-controlled oscillator that outputs four local oscillation signals with phase differences of 90°, the four local oscillation signals being a first local oscillation signal of a phase of 90° and a second local oscillation signal of a phase of 0°, respectively. a third local oscillation signal of a phase of 270° and a fourth local oscillation signal of a phase of 180°; a quadrature mixer that receives four local oscillation signals from the four-phase voltage controlled oscillator, and a preamplifier output Two differential signals, the quadrature mixer mixing the first local oscillation signal with the first differential signal to generate a first intermediate frequency signal of a phase of 90°, and the second local oscillation signal Mixing with the first differential signal to generate a second intermediate frequency signal of 0° phase, mixing the third local oscillation signal with the second differential signal to generate a third intermediate frequency signal of 270° phase, and the fourth local oscillation signal The two differential signals are mixed to generate a fourth intermediate frequency signal of 180° phase; the IQ intermediate frequency amplifier receives four intermediate frequency signals output by the quadrature mixer to improve the driving capability of the quadrature mixer and prevent signal attenuation; The multi-phase filter receives the output of the IQ intermediate frequency amplifier in the chip, filters the four intermediate frequency signals, eliminates the image signal, and achieves the image suppression function of the chip, and then the first intermediate frequency signal among the four intermediate frequency signals. And adding the second intermediate frequency signal, the third intermediate frequency signal and the fourth intermediate frequency signal are added to generate two signal outputs.

The invention also discloses an LNB frequency down circuit, the technical proposal comprising the above LNB down frequency chip circuit and a peripheral circuit of the LNB down frequency chip circuit, the peripheral circuit comprising: vertical stage high frequency amplification, receiving the radio frequency vertical signal and Amplifying the electromagnetic wave in the vertical direction of the satellite transmission signal received by the satellite receiving antenna, the vertical level is high The frequency amplification has a band-pass characteristic in the receiving frequency band; the horizontal-level high-frequency amplification receives the RF horizontal signal and amplifies the electromagnetic wave in the horizontal direction of the satellite transmission signal received by the satellite receiving antenna, and the horizontal-level high-frequency amplification is in the receiving frequency band. The utility model has the band-pass characteristic; the intermediate-stage high-frequency amplification receives the output signal of the vertical-level high-frequency amplification and the horizontal-level high-frequency amplification, and the intermediate-stage high-frequency amplification is always in the normally-on state, and the signal sent by the first-stage high-frequency amplification is outputted. Perform a second amplification to increase the overall gain of the amplifier in front of the mixer and reduce the noise figure of the entire LNB system.

The invention further discloses an LNB down-converting chip, wherein the LNB down-converting chip integrates the LNB down-converting chip circuit, and the LNB down-converting chip circuit is down-converted by the LNB down-frequency chip pin and the LNB The peripheral circuits of the chip circuit are connected.

The invention further discloses an LNB frequency reduction method achieved by using the LNB down-frequency chip circuit described above, wherein the technical solution is that the pre-amplifier pre-amplifies the received signal to improve the noise figure of the chip, so as not to deteriorate the entire LNB system. Noise, and simultaneously convert the received single-ended signal into two differential signals to improve the common mode noise suppression performance of the chip. The two differential signals are the first differential signal of 0° phase and the second differential signal of 180° phase, respectively. The four-phase voltage-controlled oscillator outputs four local oscillation signals whose phases are sequentially different by 90°, and the four local oscillation signals are respectively a first local oscillation signal of a phase of 90°, a second local oscillation signal of a phase of 0°, and 270 a third local oscillation signal of a phase and a fourth local oscillation signal of a phase of 180°; a quadrature mixer that mixes the first local oscillation signal with the first differential signal to generate a first intermediate frequency signal of a phase of 90°, The second local oscillation signal is mixed with the first differential signal to generate a second intermediate frequency signal of 0° phase, and the third local oscillation signal is mixed with the second differential signal to generate a phase of 270° phase The intermediate frequency signal, the fourth local oscillation signal is mixed with the second differential signal to generate a fourth intermediate frequency signal of 180° phase; and then the IQ intermediate frequency amplifier receives the four intermediate frequency signals output by the orthogonal mixer, Improve the driving ability of the quadrature mixer to prevent signal attenuation; then receive the output of the IQ intermediate frequency amplifier in the chip by the multi-phase filter, filter the four intermediate frequency signals, eliminate the image signal, and achieve the mirror image of the wafer. Suppressing function, then adding the first intermediate frequency signal and the second intermediate frequency signal among the four intermediate frequency signals, adding the third intermediate frequency signal and the fourth intermediate frequency signal to generate two signal outputs; finally transmitting the intermediate frequency The amplifier receives the output of the polyphase filter, drives the 75 ohm cable line outside the chip, ensures output matching, and outputs the intermediate frequency signal.

The invention integrates most of the discrete component parts of the existing discrete LNB solution, simplifies the application, production and maintenance of the LNB, and saves the cost; the integrated phase-locked loop greatly improves the frequency stability of the LNB; the integrated image suppression function, It can save the bandpass filter on the PCB board, save the cost of the board and improve the noise performance; make up for the shortcomings of the prior art in the production of low yield, improve the yield of the production process, and improve the production efficiency.

The invention discloses an LNB down-converting chip circuit, as shown in FIG. 3, comprising: a pre-amplifier, receiving an intermediate-stage high-frequency amplified output of the front-end circuit, and increasing a noise figure of the chip to avoid deterioration of noise of the entire LNB system, At the same time, the single-ended signal sent by the intermediate stage high-frequency amplification is converted into two differential signals to improve the common mode noise suppression performance of the chip. The two differential signals are the first differential signal of 0° phase and the first phase of 180° phase. Two differential signals; a four-phase voltage-controlled oscillator that outputs four local oscillation signals with phase differences of 90°, the four local oscillation signals being a first local oscillation signal of a phase of 90° and a second local oscillation signal of a phase of 0°, respectively. a third local oscillation signal of a phase of 270° and a fourth local oscillation signal of a phase of 180°; a quadrature mixer that receives four local oscillation signals from the four-phase voltage controlled oscillator, and a preamplifier output Two differential signals, the first local oscillator signal is mixed with the first differential signal to generate a first intermediate frequency signal of 90° phase, and the second local oscillation signal is first difference The partial signal mixing generates a second intermediate frequency signal of 0° phase, the third local oscillation signal is mixed with the second differential signal to generate a third intermediate frequency signal of 270° phase, and the fourth local oscillation signal and the second differential signal are combined. Mixing to generate a fourth intermediate frequency signal of 180° phase; an IQ intermediate frequency amplifier receiving four intermediate frequency signals output by the quadrature mixer, The driving ability of the high quadrature mixer prevents signal attenuation; the multi-phase filter receives the output of the IQ intermediate frequency amplifier in the chip, filters the four intermediate frequency signals, eliminates the image signal, and achieves the image suppression function of the wafer. Then, among the four intermediate frequency signals, the first intermediate frequency signal and the second intermediate frequency signal are added, and the third intermediate frequency signal and the fourth intermediate frequency signal are added to generate two signal outputs.

The LNB down-converting chip circuit further includes an intra-wafer high-frequency amplifying transistor control circuit and a vertical horizontal switching circuit, and a vertical-level high-frequency amplification, a horizontal-level high-frequency amplification, and an intermediate-level high-frequency amplification connected to the peripheral circuit of the wafer, in the wafer. The high frequency amplifying transistor control circuit provides a bias circuit for the source, the drain and the gate of the high frequency amplifying transistor in the vertical high frequency amplification, the horizontal high frequency amplification, and the intermediate high frequency amplification, and will be high The operating current of the frequency amplifying transistor is controlled within a range of normal operation, and the vertical horizontal switching circuit turns on or off the bias applied to the high frequency amplifying transistor according to the vertical/horizontal switching voltage to achieve a vertical and horizontal signal. The receiving switch is switched, and at the same time, the intermediate stage high frequency amplification is always controlled in the normally open state.

The LNB down-converting chip circuit further includes an in-wafer intermediate frequency amplifier that receives the output of the polyphase filter and drives the off-chip 75-ohm cable to ensure output matching, especially to ensure matching with the set-top box. And output the intermediate frequency signal.

The four-phase voltage-controlled oscillator, as shown in Figs. 4 and 5, includes two mutually coupled voltage-controlled oscillator units VCO1 and VCO2, and outputs four local oscillation signals with phase differences of 90°, respectively, at a phase of 90°. The first local oscillation signal IP, the second local oscillation signal QP of the phase of 0°, the third local oscillation signal IN of the phase of 270°, and the fourth local oscillation signal QN of the phase of 180°.

The invention selects the hartley structure to achieve the image suppression function. According to the implementation principle of the hartley structure frequency reducer, the present invention must generate a four-phase orthogonal local oscillation signal. There are generally three implementation methods for orthogonal local oscillator signals, a multi-phase filter scheme, a two-way scheme, and a four-phase voltage-controlled oscillator scheme.

The invention adopts a four-phase voltage-controlled oscillator scheme, which avoids the driving problem of the multi-phase filter at high frequency, and if the voltage-controlled oscillator is used in the two-way scheme It is necessary to oscillate twice the local oscillation. For the local oscillation frequency of 10.6 GHz in the Ku band, the voltage controlled oscillator needs to operate at 21 GHz. At such a high frequency, the implementation of the CMOS crossover is very difficult.

As shown in Figures 4 and 5, the four-phase voltage controlled oscillator achieves a four-phase local oscillation signal with a phase difference of 90° through mutual coupling between two voltage controlled oscillator (VCO) units. The two voltage controlled oscillator units are composed of a main oscillating tube (M1, M2, M5, M6) and a coupling tube (M3, M4, M7, M8). The output signal IP, IN of the first stage voltage-controlled oscillator VCO1 is input to the coupling tube of the second voltage-controlled oscillator VCO2, and the output QP and QN of the second-stage voltage-controlled oscillator VCO2 are input to the first-stage voltage-controlled oscillation. Coupling tube of VCO1. Thereby, a phase difference of 90° between IP, QP, IN, and QN is ensured.

The voltage controlled oscillator is connected with a phase locked loop and a prescaler circuit. The frequency stability of the voltage controlled oscillator is achieved through a phase locked loop, that is, the output signal of the voltage controlled oscillator is transmitted through the prescaler circuit, and the frequency is continuously divided. To the reference clock frequency, the phase-locked loop compares the divided output signal with the reference clock frequency, and the frequency error is continuously adjusted by the phase-locked loop to adjust the variable capacitor of the voltage-controlled oscillator to achieve accurate local oscillation frequency. .

In order to ensure that the local oscillation signal generated by the voltage-controlled oscillator does not change with environmental changes such as temperature, the local oscillation signal of the voltage-controlled oscillator must be phase-locked through the phase-locked loop (PLL) to implement a precise local oscillation signal. To overcome the shortcomings of the unstable frequency of the dielectric oscillator (DRO) in the discrete scheme. In a specific implementation, the local oscillator signal of the voltage controlled oscillator is divided by a prescaler, and the frequency is divided to a frequency near a reference clock (ie, a crystal clock), and the phase locked loop performs the reference clock frequency with the reference clock frequency. In comparison, the comparison error is compensated by continuously adjusting the variable capacitance of the voltage-controlled oscillator to achieve the phase-locking function for the local oscillation frequency. Since the crystal has a very high Q value, the frequency stability is extremely high, and the phase-locked loop will be pressed. The frequency of the oscillator is phase-locked to the crystal frequency to ensure the frequency stability of the voltage controlled oscillator.

In order to improve the frequency stability and phase noise performance of the LNB system, the present invention can integrate a phase-locked loop and a crystal oscillator to accurately control the frequency of the voltage-controlled oscillator and filter out the low-frequency phase noise of the voltage-controlled oscillator.

As shown in Figure 6, the prescaler transmits a high-frequency signal near 10 GHz from a four-phase voltage-controlled oscillator composed of two voltage-controlled oscillator units, which is continuously divided to the vicinity of the crystal oscillation frequency and sent to the phase detector. At the same time, the crystal oscillator sends the stable crystal frequency signal to the phase detector. The phase detector compares the phase error of the two sets of frequency signals, sends the corresponding control signal to the charge pump, and the loop filter outputs the signal to the charge pump. Filtering is a control voltage signal that changes with phase to control the variable capacitor inside the voltage controlled oscillator to achieve precise adjustment of the voltage of the voltage controlled oscillator.

The invention adopts a four-phase cross-coupled voltage-controlled shock oscillator composed of two voltage-controlled oscillators. The phases of the two VCOs are different, but the oscillation frequency is completely the same, so the loop filter only needs to filter the control voltage and simultaneously send Give two VCOs.

The entire phase-locked loop has a negative feedback characteristic, so that the phase of the voltage-controlled oscillator, that is, the frequency is completely proportional to the phase and frequency of the crystal oscillator. Since the crystal has a very high Q value, its frequency stability is extremely high, thereby ensuring The frequency stability of the voltage controlled oscillator.

The voltage-controlled oscillator sends a 10 GHz high-frequency signal to the phase-locked loop, and sends a 10 GHz signal to the mixer to achieve the frequency-reduction function.

The passive polyphase filter includes four paths corresponding to four intermediate frequency signals. As shown in FIG. 6, each path includes a plurality of resistors connected in series, and the front end of each resistor of the previous path is transmitted through a The capacitor is connected to the rear end of the corresponding resistor of the latter path, and the front end of each resistor of the last path is connected to the rear end of the corresponding resistor of the first path through a capacitor.

The invention adopts the hartley structure to achieve the image suppression function. According to the implementation principle of the hartley structure frequency reducer, it can be known that after the RF signal is down-converted by the quadrature mixer, the signal of the mirror position needs to be filtered out through the multi-phase filter. Since the LNB system requires an L-band intermediate frequency signal output of 950 MHz to 2150 MHz, the present invention employs a four-stage passive multi-phase filter structure. As shown in Fig. 7, the polyphase filter has a band-stop characteristic for a negative frequency (or positive frequency) signal while maintaining a band-pass characteristic of a positive frequency (or negative frequency) signal, and at the same time, the number of stages determines its The width of the stop band, the more the number of stages, the greater the width of the stop band, but the greater the insertion loss of the pass band, the through-resistance of the present invention With a compromise between width and passband insertion loss, a four-stage polyphase filter structure was chosen.

The LNB down-frequency chip circuit further includes a 22 kHz detection circuit in the chip, which responds to the received 22 kHz signal. When there is a 22 kHz signal, the detection circuit sends a high voltage level to the phase locked loop, and the phase locked loop controls the voltage controlled oscillation. The device operates at high local oscillation. Once the 22 kHz signal disappears, the detection circuit will send a low voltage level, and the phase-locked loop will lock the voltage-controlled oscillator at a low local oscillation.

The LNB down-converting chip circuit further includes a negative voltage generating circuit in the chip to generate a negative voltage, which is a gate bias of the high-frequency amplification, vertical-level high-frequency amplification, and high-frequency amplification of the intermediate-stage high-frequency amplification. The pressure provides the required bias point.

The LNB down-converting chip circuit also includes an in-chip voltage stabilizing circuit that provides power to other portions of the LNB down-converting chip circuit.

The LNB down-converting chip circuit also includes an in-wafer crystal oscillating circuit that provides a reference frequency for other portions of the LNB down-converted wafer circuit.

The invention also discloses an LNB down-converting circuit, comprising the above-mentioned LNB down-converting chip circuit, and a peripheral circuit of the LNB down-converting chip circuit, the peripheral circuit comprising: vertical-level high-frequency amplification, receiving radio frequency vertical signals and receiving by the satellite receiving antenna The vertical electromagnetic wave of the satellite transmission signal is amplified, and the vertical-level high-frequency amplification has band-pass characteristics in the receiving frequency band; the horizontal-level high-frequency amplification receives the radio frequency horizontal signal and transmits the satellite transmission signal received by the satellite receiving antenna. The electromagnetic wave in the horizontal direction is amplified, the horizontal-level high-frequency amplification has a band-pass characteristic in the receiving frequency band; the intermediate-stage high-frequency amplification receives the vertical-level high-frequency amplification and the horizontal-level high-frequency amplified output signal, and the intermediate-stage high-frequency amplification Always in the normally open state, the signal amplified by the first stage high frequency amplification is secondarily amplified, the overall gain of the amplifier in front of the mixer is increased, and the noise figure of the entire LNB system is reduced.

The peripheral circuit further includes an off-chip high-frequency amplifying transistor control circuit and a vertical horizontal switching circuit, and the vertical-level high-frequency amplification connected to the peripheral circuit, the horizontal-level high-frequency amplification, and the intermediate-stage high-frequency amplification, the external high-frequency of the wafer The amplifying transistor control circuit is the high frequency amplification in the vertical stage, the high frequency amplification in the horizontal stage, and the high frequency in the intermediate stage high frequency amplification. The source, the drain and the gate of the amplifying transistor provide a bias circuit, and the operating current of the high frequency amplifying transistor is controlled within a range of normal operation, and the vertical horizontal switching circuit is turned on according to the vertical/horizontal switching voltage. Or turn off the bias applied to the high-frequency amplifier transistor to achieve the reception switching between the vertical and horizontal signals. At the same time, the intermediate-stage high-frequency amplification is always controlled in the normally open state.

The peripheral circuit further includes an off-chip intermediate frequency amplifier that receives the output of the polyphase filter, drives the off-chip 75 ohm cable, ensures output matching, and outputs the intermediate frequency signal.

The high frequency amplifying transistor control circuit and the vertical horizontal switching circuit and the intermediate frequency amplifier may be integrated in the LNB down-converting chip circuit, or may be integrated in the peripheral circuit as described above.

The peripheral circuit further includes an off-chip 22 kHz detection circuit that responds to the received 22 kHz signal. When there is a 22 kHz signal, the off-chip 22 kHz detection circuit sends a high voltage level to the phase locked loop, and the phase locked loop controls the voltage control. The oscillator operates at a high local oscillation. Once the 22 kHz signal disappears, the 22 kHz detection circuit outside the chip will send a low voltage level, and the phase-locked loop will oscillate the voltage-controlled oscillator at a low local oscillation.

The 22 kHz detection circuit can be integrated into the LNB down-converting chip circuit, i.e., the 22 kHz detection circuit within the wafer, or integrated into the peripheral circuit as previously described. Or, a 22 kHz detection circuit is integrated in the LNB down-conversion chip circuit and in the peripheral circuit, and the LNB down-conversion circuit can select one of them to achieve the corresponding function.

The 22 kHz detection circuit is integrated in the chip circuit or in the peripheral circuit. The 22 kHz detection circuit sends a corresponding control signal to the prescaler through the detection of the 22 kHz signal to change the frequency division ratio with the prescaler. As shown in Figure 6. For example, when a 22 kHz signal is detected, a high voltage level is sent to the prescaler, and when no 22 kHz signal is detected, a low voltage level is sent to the prescaler. The prescaler switches different frequency division ratios according to the received voltage of the 22 kHz detection circuit to achieve the function of switching the oscillation frequency of the voltage controlled oscillator, thereby changing the local oscillation frequency.

The usual Ku-band LNB needs to support local oscillators of 9.75GHz and 10.6GHz. The swash frequency, no 22 kHz signal is 9.75 GHz local oscillation, and when the 22 kHz signal is present, it is switched to 10.6 GHz local oscillation.

The peripheral circuit further includes an off-chip negative voltage generating circuit that generates a negative voltage, which provides a need for the horizontal-level high-frequency amplification, the vertical-level high-frequency amplification, and the gate bias of the high-frequency amplification transistor in the intermediate-stage high-frequency amplification. The bias point.

The negative voltage generating circuit can be integrated in the LNB down-converting chip circuit, that is, the in-wafer negative voltage generating circuit, or integrated in the peripheral circuit as described above. Or, a negative voltage generating circuit is integrated in the LNB down-converting chip circuit and in the peripheral circuit, and the LNB down-converting circuit can select one of them to achieve the corresponding function.

The peripheral circuit also includes an off-chip voltage regulator circuit that provides power to the LNB down-converting chip circuit.

The LNB down-frequency chip circuit and the peripheral circuit can be integrated with a voltage stabilizing circuit to fully ensure a stable power supply for the LNB down-frequency chip circuit.

The peripheral circuit also includes an off-chip crystal oscillator circuit that provides a reference frequency for the LNB down-converting chip circuit.

The crystal oscillating circuit can be integrated in the LNB down-converting chip circuit, that is, the intra-wafer crystal oscillating circuit, or integrated in the peripheral circuit as described above. Or, a crystal oscillating circuit is integrated in the LNB down-converting chip circuit and in the peripheral circuit, and the LNB down-converting circuit can select one of them to provide a reference frequency for the LNB down-converting chip circuit.

The invention also discloses an LNB down-converting chip, the LNB down-converting chip integrated with the LNB down-converting chip circuit, the LNB down-converting chip circuit transmitting the pin of the LNB down-converting chip and the peripheral circuit of the LNB down-converting chip circuit Connected.

Figure 3 is a specific embodiment of the present invention. The present invention employs a Hartley receiver structure, the main purpose of which is to achieve image rejection performance of the wafer. Since the noise of the image frequency portion deteriorates the noise figure of the receiver by 3 dB, the performance of image rejection is particularly important for systems such as the LNB which require extremely high noise figure.

The invention also discloses an LNB down-conversion implemented by the above LNB down-conversion circuit The method pre-amplifies the received signal by a pre-amplifier to improve the noise figure of the chip, so as not to deteriorate the noise of the entire LNB system, and convert the received single-ended signal into two differential signals to improve the common mode noise of the chip. Suppressing performance, the two differential signals are a first differential signal of 0° phase and a second differential signal of 180° phase respectively; the four-phase voltage-controlled oscillator outputs four local oscillation signals whose phases are sequentially different by 90°, The four local oscillation signals are respectively a first local oscillation signal of a phase of 90°, a second local oscillation signal of a phase of 0°, a third local oscillation signal of a phase of 270°, and a fourth local oscillation signal of a phase of 180°; orthogonal mixing a frequency converter, mixing the first local oscillation signal with the first differential signal to generate a first intermediate frequency signal of a phase of 90°, mixing the second local oscillation signal with the first differential signal to generate a second intermediate frequency signal of a phase of 0° Mixing the third local oscillation signal with the second differential signal to generate a third intermediate frequency signal of 270° phase, and mixing the fourth local oscillation signal with the second differential signal to generate a fourth phase of 180° The intermediate frequency signal; then, the IQ intermediate frequency amplifier receives the four intermediate frequency signals output by the quadrature mixer, improves the driving capability of the quadrature mixer, and prevents signal attenuation; and then receives the intra-wafer by the multi-phase filter. The output of the IQ IF amplifier filters the four IF signals, eliminates the image signal, achieves the image rejection function of the chip, and then adds the first IF signal and the second IF signal among the four IF signals. The third intermediate frequency signal and the fourth intermediate frequency signal are added to generate two signal outputs; finally, the output of the polyphase filter is received through the intermediate frequency amplifier, and the output of the off-chip 75 ohm cable is ensured. Match and output the IF signal.

The frequency stability of the voltage controlled oscillator is achieved through a phase-locked loop, that is, the output signal of the voltage controlled oscillator is transmitted through the prescaler circuit, and is continuously divided to the reference clock frequency, and the phase-locked loop divides the output signal with the output signal. The reference clock frequency is compared, and the frequency error is compensated by continuously adjusting the variable capacitor of the voltage controlled oscillator through the phase-locked loop to achieve an accurate local oscillation frequency.

The high frequency amplifying transistor control circuit provides a bias circuit for the source, the drain and the gate of the high frequency amplifying transistor in the vertical high frequency amplification, the horizontal high frequency amplification, and the intermediate high frequency amplification, and The operating current of the high frequency amplifying transistor is controlled within a range of normal operation, and the vertical horizontal switching circuit has a large switching voltage according to vertical/horizontal Small, open or close the bias applied to the high frequency amplifying transistor to achieve the switching between the vertical and horizontal signals. At the same time, the intermediate stage high frequency amplification is always controlled in the normally open state.

The intermediate frequency amplifier receives the output of the polyphase filter, drives the off-chip 75 ohm cable, ensures output matching, and outputs the intermediate frequency signal.

The frequency stability of the voltage controlled oscillator is implemented by a phase-locked loop, that is, the output signal of the voltage controlled oscillator is transmitted through the prescaler circuit, and the frequency is continuously divided to the reference clock frequency, and the phase-locked loop divides the output signal with the output signal. The reference clock frequency is compared, and the frequency error is compensated by continuously adjusting the variable capacitor of the voltage controlled oscillator through the phase-locked loop to achieve an accurate local oscillation frequency.

The 22 kHz detection circuit responds to the received 22 kHz signal. When there is a 22 kHz signal, the detection circuit sends a high voltage level to the phase locked loop, and the phase locked loop controls the voltage controlled oscillator to operate at a high local oscillation once 22 kHz. When the signal disappears, the detection circuit will send a low voltage level, and the phase-locked loop will oscillate the voltage-controlled oscillator at a low local oscillation.

A negative voltage generating circuit generates a negative voltage to provide a desired bias point for the horizontal high frequency amplification, the vertical high frequency amplification, and the gate bias of the high frequency amplification transistor in the intermediate stage high frequency amplification.

The basic principle of the Hartley structure used in the present invention is to down-convert the radio frequency signal through a quadrature local oscillating signal (Quadrature LO) and a quadrature mixer, and then use the passive polyphase filter to mix the orthogonals. The frequency signal is phase shifted by 90° to ensure that the image signal is filtered out and the image rejection function is achieved.

The invention can achieve an image rejection rate of approximately 25 dB, and substantially eliminates the deterioration of the image frequency to noise. At the same time, due to the traditional LNB products using discrete components, in order to meet the noise figure below 1dB, a bandpass filter needs to be added to the PCB. After the invention is adopted, since the invention adopts the frequency reduction structure of the Hartley structure, the image signal is eliminated by the frequency reduction of the quadrature mixer and the phase shift of the multi-phase filter is eliminated, the band pass filter can be omitted, and the saving is saved. PCB area simplifies application.

A key issue in implementing the Hartley architecture is how to generate four-phase local oscillations. The signal, especially for the Ku-band LNB chip, requires a local oscillation signal with a frequency range of 9.75 GHz and 10.75 GHz, and even requires a high frequency of 11.3 GHz. Therefore, how to generate a four-phase local oscillation signal becomes a difficult problem to be solved by the present invention.

There are generally three schemes for generating four-phase local oscillation signals, a multi-phase filter scheme, a two-way scheme, and a four-phase voltage-controlled oscillator scheme. The present invention adopts a four-phase voltage-controlled oscillator scheme, thereby avoiding multi-phase at high frequencies. The driving problem of the filter, and if the voltage-controlled oscillator in the two-way scheme requires two local oscillations, the implementation of the two-way frequency is very difficult.

While implementing a hartley receiver with image rejection performance, the present invention also utilizes the CMOS chip to facilitate integration, and integrates 22 kHz signal detection and negative voltage generation circuits and receivers in the same wafer, which greatly saves LNB production. cost.

The invention integrates most of the discrete component parts of the existing discrete LNB solution, simplifies the application, production and maintenance of the LNB, and saves the cost; the integrated phase-locked loop greatly improves the frequency stability of the LNB; the integrated image suppression function, It can save the bandpass filter on the PCB board, save the cost of the board and improve the noise performance; integrate negative voltage, 22kHz signal detection and high frequency amplification transistor control, which greatly saves LNB production cost; make up the existing technology in production. The disadvantage of low rate increases the yield of the production process and improves production efficiency.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. FIG. 1 and FIG. 2 are structural diagrams of a conventional LNB down-converting circuit; FIG. 3 is a structural diagram of an LNB down-converting circuit of the present invention; FIG. And FIG. 5 is a schematic diagram of a voltage controlled oscillator in the LNB frequency down circuit of the present invention; FIG. 6 is a schematic diagram of a phase locked loop circuit in the LNB frequency down circuit of the present invention; and FIG. 7 is a multiphase in the LNB down frequency circuit of the present invention; Schematic diagram of the filter.

Claims (25)

An LNB down-converting chip circuit, comprising: a preamplifier, receiving an intermediate stage high frequency amplified output of the front end circuit, and increasing a noise figure of the chip, so as not to deteriorate the noise of the entire LNB system, and simultaneously amplifying the intermediate stage high frequency The sent single-ended signal is converted into two differential signals to improve the common mode noise suppression performance of the chip. The two differential signals are a first differential signal of 0 phase and a second differential signal of 180 degrees, respectively; four phases The voltage controlled oscillator outputs four local oscillation signals with a phase difference of 90°, wherein the four local oscillation signals are respectively a first local oscillation signal of a phase of 90°, a second local oscillation signal of a phase of 0°, and a phase of 270° a third local oscillating signal and a fourth local oscillating signal of 180° phase; a quadrature mixer receiving four local oscillating signals from the four phase voltage controlled oscillator and two differential signals output by the preamplifier, The quadrature mixer mixes the first local oscillation signal with the first differential signal to generate a first intermediate frequency signal of a phase of 90°, and mixes the second local oscillation signal with the first differential signal Generating a second intermediate frequency signal of 0° phase, mixing the third local oscillation signal with the second differential signal to generate a third intermediate frequency signal of 270° phase, and mixing the fourth local oscillation signal with the second differential signal to generate a fourth intermediate frequency signal of 180° phase; an IQ intermediate frequency amplifier that receives four intermediate frequency signals output by the quadrature mixer to improve the driving capability of the quadrature mixer and prevent signal attenuation; multiphase filter, reception The output of the IQ intermediate frequency amplifier in the chip filters the four intermediate frequency signals to eliminate the image signal to achieve the image suppression function of the chip, and then the four intermediate frequency signals, the first intermediate frequency signal and the second intermediate frequency signal. Adding, the third intermediate frequency signal and the fourth intermediate frequency signal are added to generate two signal outputs. The LNB down-converting chip circuit according to claim 1, wherein the intra-wafer high-frequency amplifying transistor control circuit and the vertical horizontal switching circuit are connected to a vertical high-frequency amplification and a horizontal high-frequency of the peripheral circuit of the wafer. Amplification and intermediate-stage high-frequency amplification, the intra-wafer high-frequency amplification transistor control circuit is the source of the high-frequency amplification transistor in the vertical-stage high-frequency amplification, the horizontal-level high-frequency amplification, and the intermediate-stage high-frequency amplification. The pole and the gate provide a bias circuit, and the operating current of the high frequency amplifying transistor is controlled within a normal working range. The vertical horizontal switching circuit is turned on or off according to the vertical/horizontal switching voltage, and is sent to the high frequency amplifying power. The crystal is biased to achieve reception switching between vertical and horizontal signals, while the intermediate stage high frequency amplification is always controlled in a normally open state. The LNB down-converting chip circuit according to claim 1, wherein the intra-wafer intermediate frequency amplifier receives the output of the polyphase filter and drives the off-chip 75 ohm cable to ensure output matching. And output the IF signal. The LNB down-converting chip circuit according to claim 1, wherein the four-phase voltage-controlled oscillator comprises two mutually coupled voltage-controlled oscillator units, and outputs four local oscillation signals whose phases are sequentially different by 90°. The LNB down-converting chip circuit according to claim 4, wherein the voltage-controlled oscillator is connected with a phase-locked loop and a pre-frequency dividing circuit, and the frequency stability of the voltage-controlled oscillator is achieved through a phase-locked loop. The output signal of the voltage controlled oscillator is transmitted through the prescaler circuit and continuously divided to the reference clock frequency. The phase locked loop compares the divided output signal with the reference clock frequency, and the frequency error is continuously adjusted through the phase locked loop. The variable capacitor of the voltage controlled oscillator is compensated to achieve an accurate local oscillation frequency. The LNB down-converting chip circuit according to claim 1, wherein the multi-phase filter includes four paths corresponding to four intermediate frequency signals, each path including a plurality of resistors connected in series, the previous path The front end of each resistor is connected to the rear end of the corresponding resistor of the latter via a capacitor. The front end of each resistor of the last path is connected to the rear end of the corresponding resistor of the first via through a capacitor. The LNB down-conversion chip circuit according to claim 1, wherein the 22 kHz detection circuit in the chip responds to the received 22 kHz signal, and when there is a 22 kHz signal, the detection circuit sends a high voltage level to the phase lock. Loop, phase-locked loop control The voltage-controlled oscillator operates at high local oscillation. Once the 22kHz signal disappears, the detection circuit will send a low voltage level, and the phase-locked loop will lock the voltage-controlled oscillator at low local oscillation. The LNB down-converting chip circuit according to claim 1, wherein the negative voltage generating circuit in the chip generates a negative voltage for the horizontal high frequency amplification, the vertical high frequency amplification, and the intermediate high frequency amplification. The gate bias of the high frequency amplifying transistor provides the required bias point. The LNB down-converting chip circuit of claim 1, wherein the in-wafer voltage stabilizing circuit supplies power to other portions of the LNB down-converting chip circuit. The LNB down-converting chip circuit of claim 1, wherein the in-wafer crystal oscillation circuit provides a reference frequency for other portions of the LNB down-converting chip circuit. An LNB down-converting circuit, comprising: the LNB down-converting chip circuit according to any one of claims 1 to 10, and the peripheral circuit of the LNB down-converting chip circuit, the peripheral circuit comprising: vertical The high-frequency amplification, receiving the radio frequency vertical signal and amplifying the electromagnetic wave in the vertical direction of the satellite transmission signal received by the satellite receiving antenna, the vertical-level high-frequency amplification has a band-pass characteristic in the receiving frequency band; the horizontal-level high-frequency amplification, receiving The radio frequency horizontal signal amplifies the electromagnetic wave in the horizontal direction of the satellite transmission signal received by the satellite receiving antenna, the horizontal high frequency amplification has a band pass characteristic in the receiving frequency band; the intermediate stage high frequency amplification, and the receiving vertical level high frequency amplification And the horizontal-level high-frequency amplified output signal, the intermediate-stage high-frequency amplification is always in a normally open state, and the signal amplified by the first-stage high-frequency amplification is secondarily amplified, thereby improving the overall gain of the amplifier in front of the mixer, and reducing the overall The noise figure of the LNB system. The LNB down-converting circuit according to claim 11, wherein the peripheral circuit further comprises an off-chip high-frequency amplifying transistor control circuit and a vertical horizontal switching circuit, and the vertical-level high-frequency amplification and level connected to the peripheral circuit Level high frequency amplification and intermediate stage high frequency amplification, the external high frequency amplification transistor control circuit is the source of the high frequency amplification transistor in the vertical stage high frequency amplification, horizontal level high frequency amplification and intermediate stage high frequency amplification The bucking pole and the gate provide a bias circuit, and the operating current of the high frequency amplifying transistor is controlled within a normal working range, and the vertical horizontal switching circuit is based on vertical/ The horizontal switching voltage is turned on or off to turn on the bias of the high frequency amplifying transistor to achieve the switching between the vertical and horizontal signals. At the same time, the intermediate stage high frequency amplification is always controlled in the normally open state. The LNB down-converting circuit of claim 11, wherein the peripheral circuit further comprises an off-chip intermediate frequency amplifier that receives the output of the polyphase filter and drives the off-chip 75 ohm cable. Ensure that the output matches and output the IF signal. The LNB down-converting circuit of claim 11, wherein the peripheral circuit further comprises an off-chip 22 kHz detection circuit responsive to the received 22 kHz signal, and when there is a 22 kHz signal, the off-chip 22 kHz detection circuit sends out The high voltage level is given to the phase-locked loop, and the phase-locked loop control voltage-controlled oscillator operates at high local oscillation. Once the 22 kHz signal disappears, the off-chip 22 kHz detection circuit will send a low voltage level, and the phase-locked loop will be voltage-controlled. The oscillator lock frequency oscillates at a low local level. The LNB down-converting circuit of claim 11, wherein the peripheral circuit further comprises an off-chip negative voltage generating circuit for generating a negative voltage, the horizontal high frequency amplification, the vertical high frequency amplification, and the intermediate stage. The gate bias of the high frequency amplifying transistor in high frequency amplification provides the required bias point. The LNB down-converting circuit of claim 11, wherein the peripheral circuit further comprises an off-chip voltage stabilizing circuit for supplying power to the LNB down-converting chip circuit. The LNB down-converting circuit of claim 11, wherein the peripheral circuit further comprises an off-chip crystal oscillator circuit for providing a reference frequency for the LNB down-converting chip circuit. The LNB down-converting chip circuit according to claim 1 is characterized in that the LNB down-converting chip circuit is connected to a peripheral circuit of the LNB down-converting chip circuit through a pin of the LNB down-converting chip. An LNB down-converting method using the LNB down-converting chip circuit as described in claim 1, wherein the preamplifier is used to pre-amplify the received signal to improve the noise figure of the chip so as not to deteriorate the entire LNB system. Noise while Converting the received single-ended signal into two differential signals to improve the common mode noise suppression performance of the chip, the two differential signals are a first differential signal of 0° phase and a second differential signal of 180° phase; The phase-voltage controlled oscillator outputs four local oscillation signals whose phases are sequentially different by 90°, and the four local oscillation signals are respectively a first local oscillation signal of a phase of 90°, a second local oscillation signal of a phase of 0°, and a phase of 270°. a third local oscillation signal and a fourth local oscillation signal of a phase of 180[deg.]; a quadrature mixer, mixing the first local oscillation signal with the first differential signal to generate a first intermediate frequency signal of a phase of 90[deg.], The oscillating signal is mixed with the first differential signal to generate a second intermediate frequency signal of 0° phase, and the third local oscillating signal is mixed with the second differential signal to generate a third intermediate frequency signal of 270° phase, and the fourth local oscillating signal is Mixing with the second differential signal to generate a fourth intermediate frequency signal of 180 degrees; and then receiving, by the IQ intermediate frequency amplifier, four intermediate frequency signals output by the quadrature mixer to improve the driving capability of the quadrature mixer, prevent Signal attenuation; the multi-phase filter receives the output of the IQ intermediate frequency amplifier in the chip, filters the four intermediate frequency signals, eliminates the image signal, achieves the image suppression function of the wafer, and then the four intermediate frequency signals, An intermediate frequency signal and a second intermediate frequency signal are added, and the third intermediate frequency signal and the fourth intermediate frequency signal are added to generate two signal outputs; finally, the output of the polyphase filter is received through the intermediate frequency amplifier, and is external to the chip. The 75 ohm cable is driven to ensure that the output matches and the IF signal is output. The LNB frequency reduction method according to claim 19, wherein the frequency stability of the voltage controlled oscillator is achieved by a phase locked loop, that is, the output signal of the voltage controlled oscillator is transmitted through the prescaler circuit, and the frequency is continuously divided. To the reference clock frequency, the phase-locked loop compares the divided output signal with the reference clock frequency, and the frequency error is continuously adjusted by the phase-locked loop to adjust the variable capacitor of the voltage-controlled oscillator to achieve accurate local oscillation frequency. . The LNB frequency reduction method according to claim 19, wherein the high frequency amplifying transistor control circuit and the vertical horizontal switching circuit are connected to a vertical high frequency amplification, a horizontal high frequency amplification, and a middle of the peripheral circuit of the wafer. Level high frequency amplification, the high frequency amplification transistor control circuit provides the source, the drain and the gate of the high frequency amplification transistor in the vertical stage high frequency amplification, the horizontal level high frequency amplification and the intermediate stage high frequency amplification The bias circuit controls the operating current of the high frequency amplifying transistor within a range of normal operation, and the vertical horizontal switching circuit turns on or off the bias applied to the high frequency amplifying transistor according to the vertical/horizontal switching voltage. In order to achieve the reception switching between the vertical and horizontal signals, the intermediate stage high frequency amplification is always controlled in the normally open state. The LNB down-clocking method according to claim 19, wherein the intermediate frequency amplifier receives the output of the polyphase filter, drives the 75 ohm cable line outside the chip, ensures output matching, and outputs the intermediate frequency signal. Output. The LNB frequency reduction method according to claim 19, wherein the voltage controlled oscillator is connected with a phase locked loop and a prescaler circuit, and the frequency stability of the voltage controlled oscillator is achieved by a phase locked loop. The output signal of the voltage controlled oscillator is transmitted through the prescaler circuit and continuously divided to the reference clock frequency. The phase locked loop compares the divided output signal with the reference clock frequency, and the frequency error is continuously adjusted through the phase locked loop. The variable capacitor of the oscillator is compensated to achieve an accurate local oscillation frequency. The LNB frequency reduction method according to claim 19, wherein the 22 kHz detection circuit responds to the received 22 kHz signal, and when there is a 22 kHz signal, the 22 kHz detection circuit sends a high voltage level to the phase locked loop. The phase-locked loop controls the voltage-controlled oscillator to operate at a high local oscillation. Once the 22 kHz signal disappears, the 22 kHz detection circuit will send a low voltage level, and the phase-locked loop will oscillate the voltage-controlled oscillator at a low local oscillation. The LNB frequency reduction method according to claim 19, wherein the negative voltage generating circuit generates a negative voltage, which is high in the horizontal high frequency amplification, the vertical high frequency amplification, and the intermediate high frequency amplification. The gate bias of the frequency amplifying transistor provides the required bias point.