TWI483374B - Semiconductor package with electromagnetic interference shielding film and method of manufacturing same - Google Patents

Description

Semiconductor package with electromagnetic interference shielding film and method of manufacturing same

The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having an electromagnetic interference shielding film and a method of fabricating the same.

In order to avoid electromagnetic interference, the semiconductor package is usually covered with an electromagnetic interference shielding element on the outer side of the semiconductor package.

However, conventional EMI shielding elements typically extend along the sides of the substrate of the semiconductor package to the lower surface of the substrate. In this way, it is easy to make a short circuit by making electrical contact with an electrical contact located on the lower surface of the substrate.

The present invention relates to a semiconductor package and a method of fabricating the same, which avoids short-circuiting of an electromagnetic interference shielding component of a semiconductor package and an electrical contact provided on a lower surface of the substrate.

According to an embodiment of the invention, a semiconductor package is proposed. The semiconductor package includes a substrate, a semiconductor device, a circuit component, a package, and an electromagnetic interference shielding film. The substrate has an upper surface and includes a grounding element. The semiconductor device is disposed on an upper surface of the substrate. The circuit component is disposed on the upper surface of the substrate and has a grounding portion electrically connected to the grounding component of the substrate. The package encloses the semiconductor device and the circuit component and has an opening, the opening exposing the ground portion of the circuit component. The electromagnetic interference shielding film covers the package and electrically contacts the ground portion of the circuit component via the opening.

According to another embodiment of the present invention, a method of fabricating a semiconductor package is provided. The manufacturing method includes the following steps. Providing a substrate, wherein the substrate has an upper surface and includes a grounding member; a semiconductor device and a circuit component are disposed on the upper surface of the substrate, wherein the circuit component has a grounding portion, and the grounding portion is electrically connected to the grounding component of the substrate; Forming a package-covered semiconductor device and circuit component; forming an opening in the package, wherein the opening exposes a ground portion of the circuit component; forming an electromagnetic interference shielding film covering the package, wherein the electromagnetic interference shielding film is electrically connected through the opening Contacting the grounding portion of the circuit component; and forming a cutting slit, wherein the cutting slit passes through the electromagnetic interference shielding film, the package body and the substrate.

According to another embodiment of the present invention, a method of fabricating a semiconductor package is provided. The manufacturing method includes the following steps. Providing a substrate, wherein the substrate has an upper surface and includes a grounding member; a semiconductor device and a circuit component are disposed on the upper surface of the substrate, wherein the circuit component has a grounding portion, and the grounding portion is electrically connected to the grounding component of the substrate; Forming a package-covered semiconductor device and circuit component; forming an opening in the package, wherein the opening exposes a ground portion of the circuit component; forming a first cutting slit, wherein the first cutting slit passes through the package; forming a The electromagnetic interference shielding film covers the package, wherein the electromagnetic interference shielding film electrically contacts the ground portion of the circuit component via the opening; and a second cutting slit is formed, wherein the second cutting slit passes through the substrate.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

Referring to FIG. 1, a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention is shown. The semiconductor package 100 includes a substrate 110 , a semiconductor device 120 , a circuit component 130 , a package 140 , an electromagnetic interference shielding film 150 , at least one pad 160 , and at least one electrical contact 170 .

The substrate 110 has an outer side surface 110s and an opposite upper surface 110u and a lower surface 110b. The outer side surface 110s extends between the upper surface 110u and the lower surface 110b to define a boundary of the substrate 110.

The substrate 110 is, for example, a multilayer organic substrate or a ceramic substrate. The substrate 110 includes at least one grounding element 111. The ground element 111 provides a ground path between the circuit component 130 and the pad 160. In this embodiment, the grounding element 111 includes at least one patterned circuit layer 1111 and at least one conductive via 1112. The via hole 1112 is electrically connected to the two patterned circuit layers 1111, so that the circuit component 130 can be electrically connected via the ground path. Connected to the pad 160. In another embodiment, the grounding element 111 is, for example, a conductive post.

The semiconductor device 120 is disposed on the upper surface 110u of the substrate 110. In this embodiment, the semiconductor device 120 is in a "face-down" orientation and is electrically connected to the substrate 110 through a plurality of solder balls. Such a structure may be referred to as "flip- Chip)". In another embodiment, the semiconductor device 120 is in a "face-up" orientation and is connectable to the substrate 110 through a plurality of bond wires.

The circuit component 130 is disposed on the upper surface 110u of the substrate 110. The circuit component 130 has at least one grounding portion 131 and/or at least one electrical contact 132. The grounding portion 131 is electrically connected to the grounding element 111 of the substrate 110. Circuit component 130 can include a transistor, a diode, an inductor, a capacitor, a resistor, a semiconductor wafer, a semiconductor package, and/or other circuit components.

The ground portion 131 may include a conductive via, a conductive layer, or an electrical contact. The grounding portion 131 has an upper surface 130u and a lower surface 130b. The grounding portion 131 can extend from the upper surface 130u to the lower surface 130b along the inside or the outside of the circuit component 130. In this embodiment, the grounding portion 131 is along the opposite ends of the circuit component 130. The outer side extends from the upper surface 130u to the lower surface 130b. The upper surface 130u of the grounding portion 131 electrically contacts the electromagnetic interference shielding film 150, and the lower surface 130b of the grounding portion 131 electrically contacts the patterned wiring layer 1111 of the substrate 110. Further, the length L1 of the circuit component 130 is about 0.6 centimeters (mm), the height H1 of the circuit component 130 is about 0.3 mm, and the width W2 of the circuit component 130 (shown in FIG. 2) is about 0.3 mm. The short side width W1 (shown in FIG. 2) of the ground portion 131 of the circuit component 130 is between about 0.15 mm and 0.3 mm.

The package body 140 encloses the semiconductor device 120 and the circuit component 130 and has at least one opening 141. The opening 141 exposes the ground portion 131 of the circuit component 130. The opening 141 exposes an opening from the upper surface 140u of the package body 140. In this embodiment, the inner diameter D1 of the opening is, for example, 400 micrometers. Preferably, but not limited to, the inner side wall 141s of the opening 141 is inclined, so that the thickness of the electromagnetic interference shielding film 150 formed on the inner side wall of the opening 141 is uniform. Since the inner side wall 141s of the opening 141 is inclined, the bottom inner diameter D2 of the opening 141 is smaller than the opening inner diameter D1. For example, the bottom inner diameter D2 of the opening 141 is about 150 micrometers. In another embodiment, the inner sidewall 141s of the opening 141 may be a vertical surface that is substantially perpendicular to the upper surface 130u of the ground portion 131 or the upper surface 140u of the package 140. Further, the pitch H2 of the bottom of the opening and the upper surface 140u of the package body 140 is about 400 μm.

The package body 140 further has an outer side surface 140s and an upper surface 140u. In this embodiment, the outer side surface 140s of the package body 140 is substantially aligned with the outer side surface 110s of the substrate 110, for example, coplanar.

The material of the package body 140 may include a novola-based resin, an epoxy-based resin, a silicone-based resin, or other suitable coating agents. The package 140 may also include a suitable filler such as powdered cerium oxide. In an embodiment, the package body 140 is a molding compound. In another embodiment, the package 140 can be a prepreg lamination.

The electromagnetic interference shielding film 150 covers the upper surface 140u of the package 140 and the inner sidewall 141s of the opening 141 and electrically contacts the ground portion 131 of the corresponding circuit component 130 via the opening 141. The material of the electromagnetic interference shielding film 150 may be selected from the group consisting of aluminum, copper, chromium, tin, gold, silver, nickel, stainless steel, and combinations thereof. Further, the electromagnetic interference shielding film 150 may be a single layer or a multilayer material. For example, the electromagnetic interference shielding film 150 is a three-layer structure, the inner layer is a stainless steel layer, the intermediate layer is a copper layer, and the outer layer is a stainless steel layer; or the electromagnetic interference shielding film 150 is a two-layer structure, and the inner layer is a copper layer. The outer layer is made of stainless steel.

The pads 160 are formed on the lower surface 110b of the substrate 110, and the electrical contacts 170 are formed on the corresponding pads 160. The electrical contacts 170 are, for example, solder balls or bumps. The electrical contact 170 of the present embodiment is described by taking a solder ball as an example, so that the semiconductor package 100 is a Ball Grid Array (BGA) structure. In another embodiment, the semiconductor package 100 can omit the electrical contacts 170 and become a Land Grid Array (LGA) structure. In addition, one of the electrical contacts 170 is electrically grounded to the ground portion 131 of the circuit component 130 through the substrate 110 . The electrical contact 171 is electrically connected to the ground of an external circuit.

In this embodiment, the pad 160 may extend to the outer side 110s of the substrate 110. Further, since the electromagnetic interference shielding film 150 does not extend to the outer surface 110s of the substrate 110, even if the pad 160 (such as the rightmost pad 160 of FIG. 1) extends to the side 110s connected to the substrate 110, The rightmost pad 160 in FIG. 1 is not electrically contacted with the electromagnetic interference shielding film 150. In addition, since the pad 160 can extend to the outer side 110s of the substrate 110, when the semiconductor package 100 is disposed on a circuit board (not shown), the battery 160 can be observed and tested through the pad 160 extending to the outer side 110s. The welding condition of the sexual contact 170. In another embodiment, the pads 160 may not extend to the outer side 110s of the substrate 110, that is, the pads 160 are spaced apart from the outer surface 110s of the substrate 110 along the extending direction of the pads 160.

Referring to FIG. 2, a top view of the semiconductor package of FIG. 1 is illustrated.

The number of openings 141 may be plural, and the distribution points may be determined by the line design and are not limited by the distribution of FIG. In this embodiment, the cross-sectional shape of the opening 141 is a circular shape. In another embodiment, the cross-sectional shape of the opening 141 may be elliptical or polygonal, such as a rectangle, a trapezoid or a triangle. Wait. In this embodiment, the shapes of the openings 141 are completely the same; in another embodiment, the cross-sectional shapes of the openings 141 may be identical or not identical.

As shown in the enlarged view of the portion A' in Fig. 2, the inner diameter D1 of the opening 141 is larger than the short side width W1 of the ground portion 131, so that the contact area of the electromagnetic interference shielding film 150 and the ground portion 131 can be increased. In another embodiment, the inner diameter D1 of the opening 141 can be greater than the short side width W1 of the ground portion 131 and the width W2 of the circuit component 130. In another embodiment, the inner diameter D1 of the opening 141 may be smaller than the short side width W1 of the ground portion 131 and the width W2 of the circuit component 130.

Referring to FIG. 3, a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention is shown.

The semiconductor package 200 includes a substrate 110 , a semiconductor device 120 , a circuit component 130 , a package 140 , an electromagnetic interference shielding film 150 , at least one pad 160 , and at least one electrical contact 170 .

The substrate 110 has an upper surface 110u, a first outer side surface 110s1, and a second outer side surface 110s2. The first outer side surface 110s1 and the second outer side surface 110s2 of the substrate 110 are not coplanar, that is, the first outer side surface 110s1 and the second outer side surface 110s2 of the substrate 110 are staggered. In this embodiment, the first outer side surface 110s1 and the second surface are The outer side surface 110s2 is staggered along the extending direction of the upper surface 110u of the substrate 110.

The package body 140 covers the semiconductor device 120 and the circuit component 130. The package body 140 has at least one opening 141, wherein the opening 141 exposes the ground portion 131 of the circuit component 130. The package body 140 further has an outer side surface 140s. In this embodiment, the outer side surface 140s of the package body 140 is substantially aligned with the first outer side surface 110s1 of the substrate 110, for example, coplanar.

The electromagnetic interference shielding film 150 covers the outer surface 140s of the package 140 and the first outer surface 110s1 of the substrate 110, and electrically contacts the ground portion 131 of the corresponding circuit component 130 via the opening 141. Since the first outer side surface 110s1 and the second outer side surface 110s2 are staggered (not coplanar), the electromagnetic interference shielding film 150 is not extended to contact the pad 160.

Referring to FIG. 4, a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention is shown.

The semiconductor package 300 includes a substrate 110 , a semiconductor device 120 , a circuit component 130 , a package 140 , an electromagnetic interference shielding film 150 , at least one pad 160 , and at least one electrical contact 170 .

The substrate 110 has an upper surface 110u and an outer side surface 110s and includes at least one grounding element 111.

The package body 140 covers the semiconductor device 120 and the circuit component 130. The package body 140 has at least one opening 141, wherein the opening 141 exposes the ground portion 131 of the circuit component 130. The package body 140 has an outer side surface 140s, wherein the outer side surface 140s of the package body 140 and the outer side surface 110s of the substrate 110 are non-coplanar, that is, the outer side surface 140s of the package body 140 is offset from the outer side surface 110s of the substrate 110. The outer surface 140s of the package body 140 and the outer surface 110s of the substrate 110 are staggered along the extending direction of the upper surface 110u of the substrate 110.

The electromagnetic interference shielding film 150 covers the outer surface 140s of the package 140 and electrically contacts the ground portion 131 of the corresponding circuit component 130 via the opening 141.

Referring to FIG. 5A, a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention is shown.

The semiconductor package 400 includes a substrate 110 , a semiconductor device 120 , a circuit component 430 , a package 140 , an electromagnetic interference shielding film 150 , at least one pad 160 , and at least one electrical contact 170 .

The substrate 110 has an upper surface 110u and an outer side surface 110s, and includes at least one grounding element 111.

The package body 140 covers the semiconductor device 120 and the outer surface 430s of the circuit component 430, and has at least one opening 141 and an outer side surface 140s. The opening 141 exposes the ground portion 431 of the circuit component 430. In this embodiment, the upper surface 140u of the package body 140 exposes an opening from the opening 141. The inner diameter D1 of the opening is, for example, 400 micrometers, and the distance H2 between the bottom of the opening and the upper surface 140u of the package body 140 is, for example, 150 micrometers. .

The electromagnetic interference shielding film 150 covers the upper surface 140u of the package 140 and electrically contacts the ground portion 431 of the circuit component 430 via the opening 141. The grounding portion 431 may include a via hole, a conductive layer or an electrical contact. In the embodiment, the grounding portion 431 is exemplified by a via hole. That is, the ground portion 431 extends from the upper surface 430u of the circuit element 430 to the lower surface 430b along the inside of the circuit element 430.

The electromagnetic interference shielding film 150 has an outer surface 150s, wherein the outer surface 150s of the electromagnetic interference shielding film 150 and the outer surface 140s of the package 140 are substantially aligned with the outer surface 110s of the substrate 110, for example, coplanar.

Please refer to FIG. 5B, which shows a top view of FIG. 5A (FIG. 5A is a cross-sectional view of the direction 5A-5A' in FIG. 5B). In this embodiment, the circuit component 430 is disposed on the metal pad of the annular circuit board, and the annular circuit board is disposed on the upper surface 110u of the substrate 110, and the grounding portion 431 is connected to the ground component of the circuit component 430 and the substrate 110. 111 electrical connection. The circuit component 430 is disposed along a closed loop path and surrounds the semiconductor device 120, and the semiconductor device 120 is exposed from the annular circuit board. In another embodiment, circuit component 430 can also be disposed along an open path. In other embodiments, the circuit component 430 can include a plurality of discrete sub-circuit boards that are disposed on the upper surface 110u of the substrate 110 and can be disposed around the semiconductor device 120.

Please refer to FIG. 6, which is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

The semiconductor package 500 includes a substrate 110 , a semiconductor device 120 , a circuit component 430 , a package 140 , an electromagnetic interference shielding film 150 , at least one pad 160 , and at least one electrical contact 170 .

The substrate 110 has an upper surface 110u and an outer side surface 110s and includes at least one grounding element 111. The package body 140 covers the upper surface 430u of the semiconductor device 120 and the circuit component 430, and has at least one opening 141 and an outer side 140s. The opening 141 exposes the ground portion 431 of the circuit component 430.

The electromagnetic interference shielding film 150 covers the upper surface 140u of the package 140 and electrically contacts the ground portion 431 of the circuit component 430 via the opening 141. Further, the outer surface 150s of the electromagnetic interference shielding film 150, the outer surface 140s of the package 140, and the outer surface 430s of the circuit element 430 are substantially aligned with the outer surface 110s of the substrate 110, for example, coplanar.

Please refer to FIGS. 7A to 7G for a manufacturing process diagram of the semiconductor package of FIG. 1.

As shown in FIG. 7A, a substrate 110 is provided, wherein the substrate 110 has an upper surface 110u and includes at least one grounding element 111.

As shown in FIG. 7B, at least one semiconductor device 120 and at least one circuit component 130 are disposed on the upper surface 110u of the substrate 110 using, for example, a surface mount technology (SMT), wherein the circuit component 130 has at least one ground portion 131, The grounding portion 131 is electrically connected to the grounding element 111 of the substrate 110.

As shown in FIG. 7C, the package body 140 is formed to cover the semiconductor device 120 and the circuit component 130 and cover the substrate 110 by, for example, compression molding, injection molding, or transfer molding. Upper surface 110u.

As shown in FIG. 7D, at least one opening 141 is formed on the upper surface 140u of the package body 140 by using a patterning technique, wherein the opening 141 exposes the ground portion 131 of the circuit component 130. The above patterning techniques include photolithography, chemical etching, laser drilling, or mechanical drilling.

As shown in FIG. 7E, the electromagnetic interference shielding film 150 is formed to cover the upper surface 140u of the package 140 and the inner sidewall 141s of the opening 141. The electromagnetic interference shielding film 150 electrically contacts the grounding portion of the circuit component 130 via the opening 141. 131. The electromagnetic interference shielding film 150 can be applied, for example, to Chemical Vapor Deposition (CVD), electroless plating, electroplating, printing, spraying, sputtering, or vacuum deposition. The technology is made, so its thickness is very thin, which can reduce the size of the semiconductor package.

As shown in FIG. 7F, at least one electrical contact 170 is formed on the lower surface 110b of the substrate 110, wherein the electrical contact 170 electrically contacts the corresponding pad 160, and one of the electrical contacts 170 The electrical contact 171 is, for example, a ground contact.

As shown in FIG. 7G, at least one slit S1 is formed, wherein the slit S1 passes through the electromagnetic interference shielding film 150, the package 140, the substrate 110, and the pad 160 to form at least one semiconductor as shown in FIG. Package 100. The cutting mode of this embodiment is a full-cut, that is, the cutting slit S1 penetrates through the substrate 110. In another embodiment, the cutting slit S1 may not pass through the pad 160.

Please refer to FIGS. 8A to 8D , which illustrate a manufacturing process diagram of the semiconductor package of FIG. 3 . The following description is made after the formation of the opening 141. The step before the opening 141 is formed is similar to the manufacturing process of the semiconductor package 100, and will not be described again.

As shown in FIG. 8A, at least one first slit slit S2 is formed, wherein the first slit slit S2 passes through a portion of the package body 140 and the substrate 110. After the first cutting slit S2 is formed, the package body 140 forms the outer side surface 140s, and the substrate 110 forms the first outer side surface 110s1. The outer surface 140s of the package body 140 is substantially aligned with the first outer side surface 110s1 of the substrate 110, for example, coplanar. The cutting method of this embodiment is a half-cut, that is, the first cutting slit S2 does not penetrate the substrate 110.

As shown in FIG. 8B, the electromagnetic interference shielding film 150 is formed to cover the upper surface 140u and the outer surface 140s of the package 140 while covering the first outer surface 110s1 of the substrate 110, wherein the electromagnetic interference shielding film 150 is electrically connected via the opening 141. The ground portion 131 of the circuit component 130 is contacted.

As shown in FIG. 8C, at least one electrical contact 170 is formed on the lower surface 110b of the substrate 110. The electrical contact 170 is electrically connected to the corresponding pad 160, and one of the electrical contacts 170 is, for example, a ground contact.

As shown in FIG. 8D, at least one second dicing slit S3 is formed, wherein the second dicing slit S3 passes through the substrate 110 and the pad 160 to form at least one semiconductor package 200 as shown in FIG. In another embodiment, the cutting slit S3 may not pass through the pad 160. After the second cutting slit S3 is formed, the substrate 110 forms a second outer side surface 110s2, wherein the first outer side surface 110s1 and the second outer side surface 110s2 of the substrate 110 are staggered along the extending direction of the upper surface 110u of the substrate 110.

Please refer to FIG. 9 , which illustrates a manufacturing process diagram of the semiconductor package of FIG. 4 . The steps of forming the first dicing slit S1 are described below, and the remaining steps are similar to the corresponding steps of forming the semiconductor package 200, and thus will not be described again.

As shown in FIG. 9, at least one first cutting slit S1 is formed, wherein the first cutting slit S1 terminates on the upper surface 110u of the substrate 110, that is, the first cutting slit S1 is not cut to the substrate 110. In this way, after the subsequent second dicing slit S3 (shown in FIG. 8D) is formed, the semiconductor package 300 of FIG. 4 can be formed.

Please refer to FIGS. 10A to 10F for a manufacturing process diagram of the semiconductor package of FIG. 5A.

As shown in FIG. 10A, at least one semiconductor device 120 and circuit component 430 are disposed on the upper surface 110u of the substrate 110. The circuit component 430 includes at least one grounding portion 431 and has an upper surface 430u and an outer side surface 430s. The grounding portion 431 of the circuit component 430 is electrically connected to the grounding component 111 of the substrate 110.

The circuit component 430 is, for example, a metal pad disposed on a ring circuit board, and the ring circuit board is disposed on the upper surface 110u of the substrate 110, and the grounding portion 431 is electrically connected to the ground component 111 of the substrate 110 through the circuit component 430. . The circuit component 430 is disposed along a closed loop path and surrounds the semiconductor device 120, and the semiconductor device 120 is exposed from the annular circuit board. In another embodiment, circuit component 430 can also be disposed along an open circular path. In other embodiments, the circuit component 430 can include a plurality of separate sub-circuit boards that are separately disposed on the upper surface 110u of the substrate 110 and disposed around the semiconductor device 120.

As shown in FIG. 10B, the package body 140 is formed to cover the semiconductor device 120 and the circuit component 430 and cover the upper surface 110u of the substrate 110 using, for example, compression molding, injection molding, or transfer molding techniques.

As shown in FIG. 10C, at least one opening 141 is formed in the package body 140 by using the above-described patterning technique, wherein the opening 141 exposes the ground portion 431 of the corresponding circuit component 430.

As shown in FIG. 10D, the electromagnetic interference shielding film 150 is formed to cover the upper surface 140u of the package 140 and the inner sidewall 141s of the opening 141. The electromagnetic interference shielding film 150 electrically contacts the grounding portion of the circuit component 430 via the opening 141. 431.

As shown in FIG. 10E, at least one electrical contact 170 is formed on the lower surface 110b of the substrate 110, wherein the electrical contact 170 is electrically connected to the corresponding pad 160, and one of the electrical contacts 170 The electrical contact 171 is, for example, a ground contact.

As shown in FIG. 10F, at least one slit S1 is formed, wherein the slit S1 passes through the electromagnetic interference shielding film 150, the package 140, the substrate 110 and the pad 160 to form at least one semiconductor as shown in FIG. 5A. Package 100. In another embodiment, the cutting slit S3 may not pass through the pad 160. After the dicing slit S1 is formed, the outer surface 150s of the electromagnetic interference shielding film 150 and the outer surface 140s of the package 140 are substantially aligned with the outer surface 110s of the substrate 110, for example, coplanar. The cutting method of this embodiment is a full cutting method. In another embodiment, the semiconductor package 400 can also be cut by a half-cutting method.

Please refer to FIG. 11 , which illustrates a manufacturing process diagram of the semiconductor package of FIG. 6 . The following describes the step of forming the dicing slit S1, and the remaining steps are similar to the corresponding steps of forming the semiconductor package 400, and thus will not be described again.

As shown in FIG. 11, at least one slit S1 is formed, wherein the slit S1 passes through the electromagnetic interference shielding film 150, the package 140, the circuit component 430 and the substrate 110 to form at least one as shown in FIG. Semiconductor package 500. After the dicing slit S1 is formed, the outer surface 150s of the electromagnetic interference shielding film 150, the outer surface 140s of the package 140, and the outer surface 430s of the circuit element 430 are substantially aligned with the outer surface 110s of the substrate 110, for example, coplanar. The cutting method of this embodiment is a full cutting method. In another embodiment, the cutting of the semiconductor package 500 can also be performed by a half-cutting method.

In the semiconductor package of the above embodiment of the present invention and the method of manufacturing the same, the electromagnetic interference shielding component of the semiconductor package is not easily electrically connected to the electrical contact on the lower surface of the substrate to cause a short circuit. In addition, the semiconductor package can be completed by a full cut or a half cut.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400, 500. . . Semiconductor package

110. . . Substrate

111. . . Grounding element

110u, 130u, 140u, 430u. . . Upper surface

110b, 130b. . . lower surface

110s, 140s, 150s, 430s. . . Outer side

1111. . . Patterned circuit layer

1112‧‧‧through hole

120‧‧‧Semiconductor device

130, 430‧‧‧ circuit components

131, 431‧‧‧ Grounding Department

132‧‧‧Electrical contacts

140‧‧‧Package

141‧‧‧opening

141s‧‧‧ inner side wall

150‧‧‧Electromagnetic interference shielding film

160‧‧‧ pads

170, 171‧‧‧ electrical contacts

D1, D2‧‧‧ inside diameter

L1‧‧‧ length

H1‧‧‧ Height

H2‧‧‧ spacing

S1‧‧‧ cutting slit

S2‧‧‧ first cutting slit

S3‧‧‧Second cutting slit

W1, W2‧‧‧ width

1 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

2 is a top view of the semiconductor package of FIG. 1.

3 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

4 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

5A is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

Fig. 5B is a top view of Fig. 5A.

6 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

7A to 7G are views showing a manufacturing process of the semiconductor package of Fig. 1.

8A to 8D are views showing a manufacturing process of the semiconductor package of Fig. 3.

FIG. 9 is a view showing a manufacturing process of the semiconductor package of FIG. 4.

10A to 10F are views showing a manufacturing process of the semiconductor package of FIG. 5A.

11 is a view showing a manufacturing process of the semiconductor package of FIG. 6.

100‧‧‧Semiconductor package

110‧‧‧Substrate

111‧‧‧ Grounding components

110u, 130u, 140u‧‧‧ upper surface

110b, 130b‧‧‧ lower surface

1111‧‧‧ patterned circuit layer

1112‧‧‧through hole

120‧‧‧Semiconductor device

130‧‧‧ circuit components

131‧‧‧ Grounding Department

132‧‧‧Electrical contacts

140‧‧‧Package

141‧‧‧opening

141s‧‧‧ inner side wall

150‧‧‧Electromagnetic interference shielding film

160‧‧‧ pads

170, 171‧‧‧ electrical contacts

D1, D2‧‧‧ inside diameter

L1‧‧‧ length

Claims (17)

A semiconductor package comprising: a substrate having an upper surface and including a grounding member; a semiconductor device disposed on the upper surface of the substrate; a circuit component disposed on the upper surface of the substrate, the circuit component having a grounding portion and an electrical contact, the grounding portion and the electrical contact are respectively connected to two different patterned circuit layers of the substrate, the grounding portion is connected to the grounding component of the substrate, and the grounding portion And the electrical contact is only a part of the circuit component; a package covering the semiconductor device and the circuit component and having an opening, the opening exposing the ground portion of the circuit component; and an electromagnetic Interfering with the shielding film, covering the package and electrically contacting the ground portion of the circuit component via the opening. The semiconductor package of claim 1, wherein the substrate has an outer side, the package has an outer side, and the outer side of the substrate is substantially aligned with the outer side of the package; The electromagnetic interference shielding film covers the outer side surface of the package and the outer side surface of the substrate. The semiconductor package of claim 1, wherein the package has an upper surface and an outer surface, the electromagnetic interference shielding film covering the upper surface of the package, but not covering the outer surface of the package side. The semiconductor package of claim 1, wherein the substrate has an outer side, the package has an outer side, and the outer side of the substrate is offset from the outer side of the package; An electromagnetic interference shielding film covers the outer side of the package. The semiconductor package of claim 1, wherein the substrate has a first outer side surface and a second outer side surface, and the first outer side surface of the substrate is offset from the second outer side surface, the package body The first outer side surface of the substrate is substantially aligned with the outer side surface of the package body; wherein the electromagnetic interference shielding film covers the outer side surface of the package body and the first outer side surface of the substrate. The semiconductor package of claim 1, wherein the circuit component comprises a circuit board from which the semiconductor device is exposed. The semiconductor package of claim 6, wherein the package has an outer side, the substrate has an outer side, and the circuit board has an outer side, wherein the outer side of the circuit board, the package The outer side of the body is substantially aligned with the outer side of the substrate. The semiconductor package of claim 6, wherein the electromagnetic interference shielding film has an outer side, the outer side of the electromagnetic interference shielding film, the outer side of the circuit board, and the outer side of the package It is substantially aligned with the outer side of the substrate. The semiconductor package of claim 1, wherein the circuit component comprises a capacitor. A method of fabricating a semiconductor package, comprising: providing a substrate, wherein the substrate has an upper surface and including a grounding member; and providing a semiconductor device and a circuit component on the upper surface of the substrate, wherein the circuit component has a ground And an electrical contact, the ground And the electrical contact are respectively connected to two different patterned circuit layers of the substrate, the grounding portion is connected to the grounding component of the substrate, and the grounding portion and the electrical contact are only the circuit component Forming a package covering the semiconductor device and the circuit component; forming an opening in the package, wherein the opening exposes the ground portion of the circuit component; forming an electromagnetic interference shielding film covering the package, wherein The electromagnetic interference shielding film electrically contacts the ground portion of the circuit component via the opening; and forms a cutting slit, wherein the cutting slit passes through the electromagnetic interference shielding film, the package and the substrate. The manufacturing method of claim 10, wherein in the step of disposing the semiconductor device and the circuit component on the upper surface of the substrate, the circuit component comprises a circuit board, the semiconductor device from the circuit The board is exposed. The manufacturing method of claim 11, wherein in the step of forming the cutting slit, the cutting slit passes through the circuit component. The manufacturing method of claim 10, wherein the circuit component comprises a capacitor. A method of manufacturing a semiconductor package, comprising: providing a substrate, wherein the substrate has an upper surface and includes a grounding member; and a semiconductor device and a circuit component are disposed on the upper surface of the substrate, wherein the circuit component has a Grounding part and an electrical contact, the connection The grounding portion and the electrical contact are respectively connected to two different patterned circuit layers of the substrate, the grounding portion is connected to the grounding component of the substrate, and the grounding portion and the electrical contact are only the circuit component Forming a package covering the semiconductor device and the circuit component; forming an opening in the package, wherein the opening exposes the ground portion of the circuit component; forming a first cutting slit, wherein The first cutting slit passes through the package; forming an electromagnetic interference shielding film covering the package, wherein the electromagnetic interference shielding film electrically contacts the ground portion of the circuit component via the opening; and forming a second cutting slit a slit, wherein the second cutting slit passes through the substrate. The manufacturing method of claim 14, wherein the substrate is in the step of forming the first cutting slit, the first cutting slit is stopped on the upper surface of the substrate. The manufacturing method of claim 14, wherein in the step of forming the first cutting slit, the first cutting slit passes through a portion of the substrate; forming the electromagnetic interference shielding film to cover the package In this step, the electromagnetic interference shielding film covers the portion of the substrate. The manufacturing method of claim 14, wherein the circuit component comprises a capacitor.