TWI482163B - Method and apparatus of changing device identification codes of a memory integrated circuit device - Google Patents

Description

System and method for changing device identification code in a memory integrated circuit device

This technology relates to a programmable identification code for an integrated circuit device.

Each memory device has an identification code to represent the type, density, manufacturer, or even other important parameters that need to be understood by the system. In general, these identification codes are stored by the anti-fuse and are immutable. If the memory device is replaced by another provider or other type, the system or controller may fail due to the identification of the old memory that is expected to be replaced. This creates an obstacle to using another different provider and/or other types to replace the current memory. For example, it is very costly and time consuming to update a system or controller to its hardware or software to have new recognition capabilities.

The present technology discloses an integrated circuit memory device. The integrated circuit memory device includes an integrated circuit substrate, a plurality of application memory cells on the integrated circuit substrate, a plurality of devices identifying non-volatile memory cells on the integrated circuit substrate, and a plurality of devices identifying non-volatile memory. The cell is on the integrated circuit substrate and the control circuit.

The control circuit (i) performing the plurality of operations of identifying a plurality of device identification codes of the non-volatile memory cells, the plurality of device identification codes including a plurality of bits identifying the memory device type of the integrated circuit, (ii) Performing a plurality of stylization, erasing, and reading operations for identifying selection data of the non-volatile memory cells, the selection data being distinguished from the plurality of device identification codes.

In one embodiment, the control circuit reads a device identification code from the plurality of identified non-volatile memory cells in response to a device identification code reading command, and the device identification code selects non-volatile memory by the plurality of identifications. The selection data of the cells is distinguished from the other device identification codes in the plurality of non-volatile memory cells.

In one embodiment, the type of the integrated circuit memory device is resolved by a device identification code of the plurality of device identification codes, the plurality of device identification codes including a manufacturer identification code of the integrated circuit memory device.

In one embodiment, the type of the integrated circuit memory device is resolved by a device identification code of the plurality of device identification codes, the plurality of device identification codes including manufacturing data of the integrated circuit memory device.

In one embodiment, the type of the integrated circuit memory device is resolved by a device identification code of the plurality of device identification codes, the plurality of device identification codes including product specification data of the integrated circuit memory device.

Another object of the present technology is to provide a method for replacing an integrated circuit memory device in an application, comprising: providing a first integrated circuit memory device configuration configured to have a first memory device identification code a compatible system; providing a second integrated circuit memory device type having no first memory device identification code; configuring the second integrated circuit memory device type having the at least portion of the first memory device identification code And integrating the second integrated circuit memory device type with the system.

In one embodiment, the configuring includes: programming a plurality of devices in the second integrated circuit memory device type to identify the non-volatile memory cell having the at least portion of the first memory device identification code, and thus reading the When the device identification code in the second integrated circuit memory device mode is operated, the at least part of the first memory device identification code is read from the plurality of devices identifying the non-volatile memory cells.

In one embodiment, the configuring includes: staging the plurality of devices in the second integrated circuit memory device type to identify the non-volatile memory cells having the selected data from the second integrated circuit memory device type The at least part of the first memory device identification code is distinguished by the plurality of memory device identification codes, and when the device identification code operation in the second integrated circuit memory device type is read, the plurality of devices are identified from the plurality of devices The volatilized memory cell reads the at least a portion of the first memory device identification code.

In one embodiment, the configuring includes: programming a plurality of devices in the second integrated circuit memory device type to identify the non-volatile memory cell having the at least portion of the first memory device identification code, and thus reading the When the device identification code in the second integrated circuit memory device mode operates, the plurality of devices are identified from the plurality of devices to recover at least a portion of the first memory device identification code to the system.

In one embodiment, the configuring includes: staging the plurality of devices in the second integrated circuit memory device type to identify the non-volatile memory cells having the selected data from the second integrated circuit memory device type The at least part of the first memory device identification code is distinguished by the plurality of memory device identification codes, and when the device identification code operation in the second integrated circuit memory device type is read, the plurality of devices are identified from the plurality of devices The volatile memory cell should have at least a portion of the first memory device identification code to the system.

In an embodiment, prior to the configuration, the memory device identification code read operation in the second integrated circuit memory device type cannot respond to at least a portion of the first memory device identification code.

In an embodiment, prior to the configuration, the second integrated circuit memory device type without the first memory device identification code is not compatible with the system.

In an embodiment, after the configuration, the memory device identification code read operation in the second integrated circuit memory device type may correspond to at least a portion of the first memory device identification code.

In an embodiment, after the configuration, the second integrated circuit memory device type without the first memory device identification code can be compatible with the system.

In one embodiment, the first device identification code comprises a manufacturer identification code of the integrated circuit memory device.

In an embodiment, the first device identification code comprises manufacturing data of the integrated circuit memory device.

In an embodiment, the first device identification code includes product specification data of the integrated circuit memory device.

A further object of the present technology is to provide a method for manufacturing an integrated circuit memory device, comprising: providing an integrated circuit substrate; providing a plurality of application memory cells on the integrated circuit substrate; and providing a plurality of devices for identifying non-volatile memory Generating on the integrated circuit substrate; providing a plurality of devices for identifying and selecting non-volatile memory cells on the integrated circuit substrate; and providing a control circuit for (i) performing a plurality of device identifications for identifying the plurality of non-volatile memory cells The operation of the code, the plurality of device identification codes comprising a plurality of bits identifying the type of the integrated circuit memory device, and (ii) performing the stylization, erasing and reading of the selection data of the plurality of selected non-volatile memory cells In the operation, the selection data is distinguished from the plurality of device identification codes.

In one embodiment, the control circuit reads a device identification code from the plurality of identified non-volatile memory cells in response to a device identification code reading command, and the device identification code selects non-volatile memory by the plurality of identifications. The selection data of the cells is distinguished from the other device identification codes in the plurality of non-volatile memory cells.

In one embodiment, the type of the integrated circuit memory device is resolved by a device identification code of the plurality of device identification codes, the plurality of device identification codes including a manufacturer identification code of the integrated circuit memory device.

In an embodiment, the type of the integrated circuit memory device is by the plurality of A device identification code of the device identification code is resolved, and the plurality of device identification codes include manufacturing materials of the integrated circuit memory device.

In one embodiment, the type of the integrated circuit memory device is resolved by a device identification code of the plurality of device identification codes, the plurality of device identification codes including product specification data of the integrated circuit memory device.

In various embodiments, these memory cells can be non-volatile and/or volatile.

A non-volatile memory cell (such as a flash memory device) can still not lose stored data even when there is no power source. Non-volatile memory cells are used in different embodiments to store the identification code and can be updated by stylizing or erasing such array data. In this case, the memory identification code is programmable and can be flexibly adjusted for different systems that expect different memory identification codes. Otherwise, different systems will require cracking and expensive changes to place a new identification code for the different memory devices.

Figures 1A and 1B show the implementation of a typical memory identification circuit. In Fig. 1A, an identification memory cell is repeatedly present in an array structure, and the data is output in a byte mode or a character mode. A more detailed schematic diagram of identifying memory cells is shown in FIG. 1B and includes a connection that depends on a metal layer and a transistor that pulls the output bit line BL to ground through an N-type MOS transistor, or alternatively The P-type MOS transistor is slightly pulled high and the output bit line BL is maintained at the supply voltage (Vdd). Therefore, the identification code of a memory device can be changed by modifying the metal layer of the memory device. However, such an embodiment is less flexible because it requires changing the mask of the metal layer to different memory device identification codes, and it is necessary to determine the identification code of the memory device at the time of manufacture (so it cannot be modified after manufacture). The identification code of this memory device).

Figures 2A and 2B show schematic and flow diagrams of many different embodiments, respectively. In Figure 2A, each memory device identification code bit has a connection to a series of pull-down NMOS transistors, and each NMOS transistor of a particular bit position in the series is selected by a different memory device identification code. The same specific bit position is selected. The upper column of the NMOS transistor reads all the bit positions of the memory device identification code ID0, and the lower column of the NMOS transistor reads all the bit positions of the memory device identification code ID1. For example, the leftmost one of the series NMOS transistors corresponds to the output memory device identification code bit position 7, and within the series, the higher NMOS transistor represents the bit position 7 of the memory device identification code ID0. And the lower NMOS transistor represents the bit position 7 of the other memory device identification code ID1. The point between the higher NMOS transistor and the lower NMOS transistor is represented in different embodiments, and the circuit can be customized to have a specific number of memory device identification codes, such as a different number of columns. In addition, the circuitry can be customized to have a particular number of bit locations within each memory device identification code, such as a different number of rows.

Different memory device identification code selections are stored in a non-volatile memory and are extracted into the scratchpad when the power source initiates a read. For a particular bit position, if any memory device identification code (e.g., memory device identification code ID0 or ID1) is a logic high level, the pull-down transistor path for that bit position is turned on. In this case, the integrated circuit may output one of the multiple memory device identification codes based on one or more memory device identification code bits stored in one or more non-volatile memory cells. Fig. 2B is a flow chart showing the process of extracting the memory device identification selection code, and then extracting the memory device identification code selected by the memory device identification selection code when the power source starts reading. After step 11 of the power-on read, step 13 extracts the memory device identification code from the non-volatile memory cell. In step 15, one of the multiple memory device identification codes is selected using the memory device identification code. Then, in step 17, the selected memory device identification selection code is output.

Figures 3A and 3B show schematic diagrams of other embodiments. Figure 3A is a memory device identification code register array structure. The registers of different memory device identification codes are enabled by different enable signals (EN#) and output to the data bus bars ID0~ID7, while the other memory device identification code registers are not receiving the enable signal. Still remain closed. Figure 3B shows a schematic diagram of an example unit identification register having an "Lpad" signal to latch the memory device identifier read from the non-volatile memory cell and the enable signal "EN" to set the pin The lock starts. Since the memory device identification code is stored and extracted from the non-volatile memory cells, the memory device identification code can be modified by stylizing or erasing the memory cell.

Figure 4 shows a flow chart of how to extract and update the memory device identification code selection bit. At step 21, a memory device to be programmed is issued to identify the selection code. The operation of the stylized memory device to identify the selection code begins in step 23. The verification procedure in step 25 determines whether the stylization succeeds or fails. If the determination is that the stylization failed, then in step 27 it is determined whether the maximum number of stylized attempts has been reached. If the maximum number of stylized attempts has not been reached, go back to step 23 and program again. If the maximum number of stylized attempts has been reached, then in step 29 it is determined that the stylization operation failed. If it is determined in step 25 that the programming is successful, then the algorithm proceeds to step 31 for power-on reading. The memory device identification selection code is extracted into the non-volatile memory cell at step 33. After having the memory device identification selection code, a memory device identification code is selected in step 35. The memory device identification code identified by the memory device identification code is then output at step 37.

Figure 5 shows a flow chart of how to re-extract and update the memory device identification bits. At step 41, a memory device to be programmed is issued to identify the selection code. The operation of the stylized memory device to identify the selection code begins in step 43. The verification procedure in step 45 determines whether the stylization succeeds or fails. If the determination is that the stylization failed, then in step 47 it is determined if the maximum number of stylized attempts has been reached. If the maximum number of stylized attempts has not been reached, then re Go back to step 43 and perform the stylization again. If the maximum number of stylized attempts has been reached, then in step 49 it is determined that the stylization operation failed. If it is determined in step 45 that the programming is successful, then the algorithm proceeds to step 51 for power-on reading. The memory device identification selection code is extracted into the non-volatile memory cell at step 53. This memory device identification code is then output at step 55.

Figure 6 shows an exemplary variable memory device identification selection code and variable memory device identification code application. At step 61 a system is provided that is configured to be compatible with the first integrated circuit memory device type having the first memory device identification code. An example of such compatibility is that the system interrogates the first integrated circuit memory device type and the system performs normal operation after receiving the first memory device identification code from the first integrated circuit memory device type. At step 63, a second integrated circuit memory device type having no first memory device identification code is provided. At this time, since the second integrated circuit memory device type does not have the first memory device identification code, the system is not configured to be compatible with the second integrated circuit memory device type. Although lack of compatibility, the system may still be compatible with the second integrated circuit memory device type. For example, the system can be configured to interrupt normal operation if the first memory device identification code is not obtained as expected when the system interrogates the second integrated circuit memory device type. Without the presently described techniques, such systems must be modified and updated to accept different memory device identification codes associated with the second integrated circuit memory device type. At step 65, the second integrated circuit memory device type is configured to have at least a portion of the first memory device identification code, at least the first memory device identification code portion with the system expected to continue normal operation. Such a configuration is referred to as updating the variable memory device identification selection code and/or the variable memory device identification code of the second integrated circuit memory device type. At step 67, the second integrated circuit memory device type is integrated with the system. Such integration can occur before or after the configuration of the second integrated circuit memory device type.

Figure 7 shows a simplified schematic of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit 750 includes using a non-volatile memory cell with application data. 700. Non-volatile memory cells 752 having device identification codes and non-volatile memory cells 754 having selected data are implemented in one or more memory arrays in the manner described herein. A column of decoders 701 is coupled to a plurality of word lines 702 arranged along the direction of the memory array column. Row decoder 703 is coupled to a plurality of bit lines 704 arranged along the row direction of the memory array to read and program data from the memory cells of the array. The address is provided by bus bar 705 to row decoder 703 and column decoder 701. The sense amplifier and data input structure in block 706 is coupled to row decoder 703 via data bus 707. The data is supplied to the data input line 711 by the input/output port on the integrated circuit 750, or is input to the data input structure in block 706 by other internal/external data sources of the integrated circuit 750. The controller used in this embodiment uses a bias adjustment state mechanism 709 and controls the application of bias voltage adjustment supply voltage generated or provided by the voltage supply source or block 708, such as reading, erasing, Stylize, erase verification, and stylize verification voltages. The controller can be utilized with special purpose logic circuitry as is well known to those skilled in the art. In an alternate embodiment, the controller includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller is a combination of special purpose logic circuitry and a general purpose processor.

Different embodiments use different forms of memory device parameters such as identification codes, patterns, densities, specifications, and the like.

The programmable identification code method and apparatus according to an embodiment of the present invention is not limited to use in a memory application, and can be applied to other circuits that provide flexible content material.

In addition to non-volatile memory, the invention can also be used in fuse or metal layer selective connection devices. The storage element can be any type of medium such as a memory cell, a fuse or a metal layer connection.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Replacement and modification styles have been previously described It is suggested in the description, and other alternatives and modifications will be considered by those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

750‧‧‧ integrated circuit

700‧‧‧Non-volatile memory cells with applied data

752‧‧‧ Non-volatile memory cells with device identification code

754‧‧‧Non-volatile memory cells with selected data

701‧‧‧ column decoder

702‧‧‧ character line

703‧‧‧ line decoder

704‧‧‧ bit line

705, 707‧‧ ‧ busbar

706‧‧‧Sense Amplifier/Data Entry Structure

709‧‧‧Stylized, erased and read adjustment bias state mechanism

708‧‧‧ bias adjustment supply voltage

711‧‧‧ data input line

715‧‧‧ data output line

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments will be described in conjunction with the drawings in the sections of the following embodiments, wherein: Figures 1A and 1B show an implementation of a typical memory identification circuit.

Figures 2A and 2B show a schematic diagram and a flow chart, respectively, of various embodiments of a memory identification code circuit.

3A and 3B are schematic illustrations showing other embodiments of a memory identification code circuit.

Figure 4 shows a flow chart of how to extract and update the memory device identification code selection bit.

Figure 5 shows a flow chart of how to re-extract and update the memory device identification bits.

Figure 6 shows an exemplary variable memory device identification selection code and variable memory device identification code application.

Figure 7 shows a simplified schematic of an integrated circuit in accordance with an embodiment of the present invention.

Claims (14)

An integrated circuit memory device comprising: an integrated circuit substrate; a device identification code register storing a selected device identification code from a plurality of device identification codes, the selected device identification code being provided in response a requirement from the outside of the integrated circuit memory device; a plurality of application memories are on the integrated circuit substrate; a plurality of devices identify the non-volatile memory cells on the integrated circuit substrate; and the plurality of devices identify the non-volatile memory cells On the integrated circuit substrate, the plurality of devices identify the selected non-volatile memory cells and store a plurality of memory device identification selection codes; and the control circuit, wherein (i) performing the plurality of device identification codes for identifying the plurality of non-volatile memory cells The operation, the plurality of device identification codes includes a plurality of bits identifying the integrated circuit memory device type, and (ii) performing the plurality of operations for identifying the selected data of the non-volatile memory cells, the memory device identifying the selection One of the codes is extracted to select a device identification code, such that the selected data is distinguished from the plurality of device identification codes, the plurality of The device identification code includes at least a first device identification code and a second device identification code, the plurality of device identification codes are stored on the integrated circuit memory device other than the device identification code register, and (iii) is applicable Copying the selected device identification code from the plurality of device identification codes to the device identification code register. The memory device of claim 1, wherein the control circuit reads a device identification code from the plurality of non-volatile memory cells in response to a device identification code reading command, the device identification code The selection data identifying the non-volatile memory cells is distinguished from the other device identification codes in the plurality of non-volatile memory cells. The memory device of claim 1, wherein the integrated circuit memory device is distinguished by a device identification code of the plurality of device identification codes, the plurality of device identification codes including the integrated circuit memory At least one of the manufacturer's manufacturer identification code, manufacturing materials, and product specifications. A method of replacing an integrated circuit memory device in an application, comprising: providing a system configured to be compatible with a first integrated circuit memory device having a first memory device identification code; providing a a second integrated circuit memory device type, wherein the identification code of the second integrated circuit memory device type does not have a first memory device identification code; and the second integrated circuit memory device type has The at least part of the first memory device identification code is copied to the second memory device by at least part of the plurality of device identification codes stored in the second integrated circuit memory device The identification code register of the integrated circuit memory device type; and integrating the second integrated circuit memory device type with the system; wherein the first memory device identification code is selected to be non-volatile according to the plurality of memory device identification A plurality of memory devices stored in the memory cells are selected to identify one of the selection codes. The method of claim 4, wherein the configuring comprises: staging the plurality of devices in the second integrated circuit memory device type to identify the non-volatile memory cell having the at least portion of the first memory device The identification code, when the device identification code operation in the second integrated circuit memory device type is read, the at least part of the first memory device identification code is read from the plurality of devices identifying the non-volatile memory cells. The method of claim 4, wherein the configuring comprises: staging the plurality of devices in the second integrated circuit memory device type to identify the non-volatile memory cells having the selected data from the second product The plurality of memory device identification codes in the body circuit memory device type distinguish the at least part of the first memory device identification code, and when the device identification code operation in the second integrated circuit memory device type is read, The at least part of the first memory device identification code is read from the plurality of devices identifying the non-volatile memory cells. The method of claim 4, wherein before the configuration, a memory device identification code reading operation in the second integrated circuit memory device type cannot respond to at least a portion of the first memory device Identifier. The method of claim 4, wherein the second integrated circuit memory device type without the first memory device identification code is not compatible with the system prior to the configuration. The method of claim 4, wherein after the configuration, a memory device identification code reading operation in the second integrated circuit memory device type can return at least part of the first memory device Identifier. The method of claim 4, wherein the second integrated circuit memory device type without the first memory device identification code is compatible with the system after the configuration. The method of claim 4, wherein the first device identification code comprises at least one of a manufacturer identification code, manufacturing data, and product specification data of the integrated circuit memory device. A method of manufacturing an integrated circuit memory device, comprising: providing an integrated circuit substrate; providing a device identification code register for storing a selected device identification code from among a plurality of device identification codes, the selected The device identification code is provided in response to a request from the external device memory device; a plurality of application memory cells are provided on the integrated circuit substrate; and a plurality of devices are provided to identify the non-volatile memory cells on the integrated circuit substrate Providing a plurality of device identification selection non-volatile memory cells on the integrated circuit substrate, and storing a plurality of device identification selection codes for identifying the non-volatile memory cells in the plurality of devices; and providing a control circuit, wherein (i) performing the a plurality of operations for identifying a plurality of device identification codes of the non-volatile memory cells, the plurality of device identification codes including a plurality of bits identifying the integrated circuit memory device type, and (ii) performing the plurality of identification selection non-volatile memories Selecting one of the memory device identification selection codes to select a device identification code to cause the selection data to be selected Distinguishing from the plurality of device identification codes, the plurality of device identification codes including at least a first device identification code and a second device identification code, the plurality of device identification codes being stored outside the device identification code register The integrated circuit memory device, and (iii), is adapted to copy the selected device identification code from the plurality of device identification codes to the device identification code register. The method of claim 12, wherein the control circuit reads a device identification code from the plurality of identified non-volatile memory cells in response to a device identification code reading command, the device identification code The selection data identifying a plurality of non-volatile memory cells is distinguished from the other device identification codes in the plurality of non-volatile memory cells. The method of claim 12, wherein the integrated circuit memory device is distinguished by a device identification code of the plurality of device identification codes, the plurality of device identification codes including the integrated circuit memory device At least one of the manufacturer's identification number, manufacturing materials, and product specifications.