TWI481938B - In-cell touch display panel - Google Patents

Description

In-line touch display panel

The present invention relates to a touch display panel, and more particularly to an in-cell touch display panel.

With the rapid development and application of information technology, wireless mobile communication and information appliances, many information products have been transformed from traditional keyboards or mouse input devices to use for the convenience of portability, light weight and user-friendly operation. The touch panel is used as an input device.

Currently, touch panels can be roughly classified into resistive, capacitive, infrared, and ultrasonic touch panels. Among them, resistive touch panels and capacitive touch panels are the most common products. In the case of a capacitive touch panel, the multi-touch feature provides a more user-friendly operating mode, making the capacitive touch panel popular in the market.

Generally, the touch display panel has a display area and a peripheral area, wherein the display area is provided with a sensing array to sense the occurrence of a touch event. Here, a plurality of signal transmission lines connected to the sensing array are disposed in the peripheral area, and the signal transmission line can be The signal sensed by the sensing array is passed to the backend processing unit. However, in order to set a large number of signal transmission lines, the peripheral area of the touch display panel will occupy a certain area. As a result, it will be difficult to meet the narrow bezel design requirements of the touch display panel.

The invention provides an in-cell touch display panel which meets the requirements of a narrow bezel design.

The in-cell touch display panel of the present invention includes an active device array substrate, an opposite substrate, and a display medium layer. The active device array substrate has a display area, and the active device array substrate includes a plurality of active elements, a plurality of pixel electrodes, a first insulating layer, a second insulating layer, and a plurality of common electrodes. The array of active components is arranged in the display area. The pixel electrodes are located within the display area and are respectively coupled to respective active components. The first insulating layer covers the active device and the pixel electrode. The conductive layer is disposed on the first insulating layer. The conductive layer includes a plurality of pads and a plurality of first connecting lines. The pad is adjacent to one side of the active device array substrate. The first connecting lines respectively extend in the first direction and are located in the display area. The first connecting lines are respectively connected to the corresponding pads. The second insulating layer is disposed on the conductive layer and has a plurality of contact windows. The common electrodes are disposed on the second insulating layer and respectively correspond to the pixel electrodes. The common electrodes are arranged in a plurality of common electrode series extending in the second direction, wherein each two or more common electrode series are connected to form a first electrode line, so that all common electrodes of the active device array substrate are formed along the first direction N first electrode lines arranged in sequence. The Jth first connecting line intersects the Kth to Nth first electrode lines, and is connected to the Kth first electrode via a corresponding contact window Line, J, K, N are positive integers. The opposite substrate corresponds to the active device array substrate. There are a plurality of second electrode lines on the surface of the opposite substrate. The second electrode lines respectively extend in the first direction, and the first electrode lines and the second electrode lines together form a sensing array. The display medium layer is sandwiched between the active device array substrate and the opposite substrate.

The in-cell touch display panel of the present invention includes an active device array substrate, an opposite substrate, and a display medium layer. The active device array substrate has a display area. The active device array substrate includes a plurality of active elements, a plurality of common electrodes, a first insulating layer, a conductive layer, a second insulating layer, and a plurality of pixel electrodes. The array of active components is arranged in the display area. The common electrodes are located in the display area and respectively correspond to the active element arrangement, and the common electrodes are arranged in a plurality of common electrode series extending in the second direction, wherein each two or more common electrode series are connected to each other to form the first electrode The wires are such that all the common electrodes of the active device array substrate form N first electrode lines arranged in the first direction, and N is a positive integer. The first insulating layer covers the active device and the common electrode and has a plurality of contact windows. The conductive layer is disposed on the first insulating layer. The conductive layer includes a plurality of pads and a plurality of first connecting lines. The pad is adjacent to one side of the active device array substrate. The first connecting lines respectively extend in the second direction and are located in the display area. The first connecting lines are respectively connected to the pads, wherein the Jth first connecting lines intersect the Kth to Nth first electrode lines, and are connected to the Kth first electrode lines via corresponding contact windows, J. K is a positive integer. The second insulating layer is disposed on the conductive layer. The pixel electrodes are disposed on the second insulating layer and are located in the display area, and the pixel electrodes are respectively coupled to the corresponding active components. The opposite substrate corresponds to the active device array substrate. a plurality of second electrode lines on the surface of the opposite substrate, the second electrode lines respectively extending in the second direction, and The first electrode line and the second electrode line together form a sensing array. The display medium layer is sandwiched between the active device array substrate and the opposite substrate.

Based on the above, the first connection line is disposed in the display area of the active device array substrate, and the first connection line can transmit the signal of the first electrode line to the pad, thereby reducing the area of the peripheral area, thereby satisfying the touch display. The narrow bezel design needs of the panel.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧In-cell touch display panel

100, 100a, 100b‧‧‧ active device array substrate

102d‧‧‧ display area

102p‧‧‧ surrounding area

103, 105‧‧‧ conductor layer

104, 106‧‧‧Insulation

110‧‧‧Active components

120‧‧‧pixel electrodes

120a‧‧‧ Main Department

120b‧‧‧ Branch

120c‧‧‧ conductive pattern

130‧‧‧First insulation

140‧‧‧ Conductive layer

142‧‧‧ pads

144a, 144a (1) ‧ ‧ first cable

144b‧‧‧second cable

144c‧‧‧ third cable

146‧‧‧Electrical wiring

150‧‧‧Second insulation

160‧‧‧Common electrode

160a‧‧‧Common electrode pattern

160s‧‧‧Common electrode series

170‧‧‧Auxiliary cable

200‧‧‧ opposite substrate

202‧‧‧Substrate

202a‧‧‧Outer surface

202b‧‧‧ inner surface

300‧‧‧Display media layer

A-A’, B-B’, C-C’, D-D’‧‧‧

C1, C3, C4, C5‧‧‧ Connections

C2‧‧‧ conductive pattern

COM‧‧‧Shared wiring

D1‧‧‧ first direction

D2‧‧‧ second direction

E‧‧‧Sensor array

E1, E1 (1), E1 (2), E1 (3), E1 (4) ‧ ‧ first electrode line

E2‧‧‧Second electrode line

D1‧‧‧first spacing

D2‧‧‧second spacing

D3‧‧‧ third spacing

L‧‧‧断差

G‧‧‧ gate

S‧‧‧ source

SL‧‧‧ scan line

DL‧‧‧ data line

CH‧‧‧ channel layer

D‧‧‧汲

P‧‧‧ sub-pixel unit

R1‧‧‧ first district

R2‧‧‧Second District

R3‧‧‧ Third District

H, H1, H2‧‧‧ contact window

FIG. 1A is a schematic cross-sectional view of an in-cell touch display panel according to an embodiment of the invention.

FIG. 1B is a schematic cross-sectional view of an in-cell touch display panel according to another embodiment of the invention.

2 is a top plan view of an active device array substrate of an embodiment.

Figure 3 is a top plan view of the pixel structure.

4A is a partially enlarged schematic view of the active device array substrate of FIG. 2.

4B is a top view of the common electrode and common electrode pattern of FIG. 4A.

5A is a partial cross-sectional view showing an active device array substrate of an embodiment.

FIG. 5B is a partial cross-sectional view showing an active device array substrate according to an embodiment.

FIG. 6 is a partially enlarged schematic view showing the third zone.

7A is a partial cross-sectional view showing an active device array substrate of another embodiment.

7B is a partial cross-sectional view showing an active device array substrate of another embodiment.

7C is a partial cross-sectional view showing an active device array substrate of another embodiment.

8A to 8C are top plan views of a first region, a second region, and a third region of an active device array substrate according to another embodiment of the present invention.

8D is a top plan view of the common electrode, the common electrode pattern, the scan line, and the common wiring of FIGS. 8A to 8C.

9A to 9B are schematic cross-sectional views taken along line C-C' and line D-D' of Fig. 8A, respectively.

FIG. 10 is a top plan view of an active device array substrate according to another embodiment of the present invention.

FIG. 11 is a top plan view of an active device array substrate according to another embodiment of the present invention.

FIG. 1A is a schematic cross-sectional view of an in-cell touch display panel according to an embodiment of the invention. Referring to FIG. 1A , the in-cell touch display panel 10 includes an active device array substrate 100 , a counter substrate 200 , and a display medium layer 300 . The opposite substrate 200 is disposed corresponding to the active array substrate 100, wherein the display medium layer 300 is sandwiched between the active device array substrate 100 and the opposite substrate 200.

2 is a top plan view of the active device array substrate 100. Referring to FIG. 2, the active device array substrate 100 has a display area 102d and a peripheral area 102p. The middle peripheral area 102p is disposed around the display area 102d. The active device array substrate 100 has a plurality of sub-pixel units P thereon, and FIG. 3 illustrates an enlarged schematic view of one of the sub-pixel units P. Referring to FIG. 2 and FIG. 3 , the active device array substrate 100 includes a plurality of active devices 110 , a plurality of pixel electrodes 120 , a first insulating layer 130 , a conductive layer 140 , a second insulating layer 150 , and a plurality of common electrodes 160 . It should be noted that, in order to clearly illustrate the arrangement relationship of the members, the first insulating layer 130 and the second insulating layer 150 are omitted from FIGS. 2 and 3 . Regarding the film layer positions of the first insulating layer 130 and the second insulating layer 150, reference may be made to the cross-sectional schematic views of FIGS. 5A to 5B.

Referring to FIG. 2 and FIG. 3, the active elements 110 are arrayed in the display area 102d. As shown in FIG. 3, the active device 110 includes a gate G, a channel layer CH, a source S, and a drain D. The gate G and the source S of the active device 110 are respectively connected to different signal lines. For example, the gate G is connected to the corresponding scan line SL and the source S is connected to the corresponding data line DL. The active device 110 of this embodiment is exemplified by a bottom gate type thin film transistor. However, in other embodiments, the active device 110 can also be a top gate type thin film transistor or other suitable type of thin film transistor, and the invention is not limited thereto. In addition, the channel layer CH may be a single layer or a multilayer structure, and the material thereof comprises amorphous germanium, polycrystalline germanium, single crystal germanium, microcrystalline germanium, nano germanium, organic semiconductor material, oxide semiconductor material, or other suitable materials, Or a combination of at least two of the above materials.

The pixel electrodes 120 are located in the display area 102d, and the respective pixel electrodes 120 are respectively coupled to the drains D of the corresponding active elements 110. The pixel electrode 120 has, for example, a branched pattern. Specifically, the pixel electrode 120 includes a main portion 120a and a plurality of The branch portion 120b, one end of the branch portion 120b is connected to the main portion 120a, and the branch portion 120b is not connected to other electrodes, wherein the branch portion 120b is extended by the main portion 120a in the first direction D1 to the edge of the sub-pixel unit P. The branches 120b are parallel to each other and have a spacing to form at least one slit (not labeled). The pixel electrode 120 may be a single layer or a multilayer structure, and the material thereof includes a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), transparent organic conductive material, or other suitable transparent conductive material. Or other suitable electrically conductive material, or a combination of at least two of the above electrically conductive materials.

The first insulating layer 130 (shown in FIGS. 5A and 5B ) covers the active device 110 and the pixel electrode 120 described above. The first insulating layer 130 may be a single layer or a multilayer structure, and the material thereof includes an inorganic dielectric material (for example, hafnium oxide, tantalum nitride, hafnium oxynitride or other suitable inorganic dielectric material) or an organic dielectric material (for example) : benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), polyphenylquinoxaline (PPQ), polystyrene (PS) Or other suitable organic dielectric material).

4A is a partially enlarged schematic view of the active device array substrate of FIG. 2. 4B is a top view of the common electrode and common electrode pattern of FIG. 4A. It should be noted that, in order to clearly illustrate the arrangement relationship of the components, FIG. 4A omits part of the components (for example, the scan line SL, the data line DL, the active device 110, and the pixel electrode 120), wherein the active device array substrate 100 The active elements 110 in the different sub-pixel units P are substantially identical in structure to the pixel electrodes 120. Those skilled in the art should understand the actives in the other sub-pixel units P after referring to the sub-pixel elements of FIG. The design of the element 110 and the pixel electrode 120.

Referring to FIG. 2, FIG. 4A and FIG. 4B, the conductive layer 140 is disposed on the first insulating layer 130 (shown in FIGS. 5A and 5B). The conductive layer 140 includes a plurality of pads 142 and a plurality of first connecting lines 144a. The pads 142 are located in the peripheral region 102p. The first connection line 144a is located in the display area 102d, and each of the first connection lines 144a extends in the first direction D1. The first connection line 144a is connected to the corresponding pad 142. It should be noted that the signal lines (such as the scan line SL and the data line DL) are also respectively connected to corresponding signal line pads (not shown). Here, the signal line pads (not shown) are different pads from the aforementioned pads 142. The conductive layer 140 is a single layer or a multilayer structure, and the material thereof includes a metal material, an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, a nitride of an alloy, an oxide of an alloy, and an alloy. Nitrogen oxides, organic conductive materials, or other suitable materials.

The second insulating layer 150 (shown in FIGS. 5A and 5B ) covers the conductive layer 140 and the first insulating layer 130 . The second insulating layer 150 may be a single layer or a multilayer structure, and the material thereof includes an inorganic dielectric material (for example, hafnium oxide, tantalum nitride, hafnium oxynitride or other suitable inorganic dielectric material) or an organic dielectric material (for example) : benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), polyphenylquinoxaline (PPQ), polystyrene (PS) Or other suitable organic dielectric material).

The common electrode 160 is disposed on the second insulating layer 150. Referring to FIG. 3, the arrangement relationship between the common electrode 160 and the pixel electrode 120 is illustrated. In the sub-pixel unit P of FIG. 3, each common electrode 160 is disposed corresponding to one pixel electrode 120, and the common electrode 160 partially covers the pixel electrode. 120. The common electrode 160 has, for example, a plurality of In the slit (not shown), the pixel electrodes 120 are disposed between the slits of the common electrode 160, and the common electrode 160 is disposed between the slits of the pixel electrode 120. As a result, when the pixel electrode 120 and the common electrode 160 are applied with different voltages, an electric field is generated between the pixel electrode 120 and the common electrode 160 to drive the display medium. In other words, the driving mode of the display medium of the present embodiment is substantially a transverse electric field driving mode.

Referring to FIG. 2, FIG. 4A and FIG. 4B, the common electrode 160 is arranged in a plurality of common electrode serials 160s, wherein each of the common electrode serials 160s extends in the second direction D2, and the common electrode serials 160s are along the first The direction D1 is arranged, wherein the second direction D2 is interlaced with the first direction D1, and the present invention is substantially perpendicular to the above two directions, but is not limited thereto. Each of the two or more common electrode serials 160s is connected to form one first electrode line E1(1) to E1(4). In this embodiment, four common electrode serials 160s are connected to form one of the first electrode lines E1(1) to E1(4). Of course, the invention is not limited thereto. In other embodiments, each of the first electrode lines E1(1) to E1(4) includes three, four or more common electrode strings 160s connected to each other.

In addition, all the common electrode serials 160s are connected to form N first electrode lines E1(1) to E1(4) arranged in the first direction D1, and the adjacent first electrode lines E1(1)~ There is a gap L between E1(4) (see FIG. 4A and FIG. 4B), for example, two adjacent first electrode lines E1(1), E(2) are separated from each other and are not connected to each other. The active device array substrate 100 of the present embodiment is illustrated by taking four first electrode lines E1(1) to E1(4) as an example. Of course, the present invention is not limited thereto. In other embodiments, the active component The array substrate 100 may include a greater number of first electrode lines.

In this embodiment, the Jth first connection line 144a intersects the Kth to Nth first electrode lines, and is connected to the Kth first electrode line E1 via the corresponding contact window H, J, K, N are A positive integer. For example, the first first connection line 144a(1) intersects the first to fourth first electrode lines E1(1) to E1(4), wherein the first first connection line 144a(1) is correspondingly The contact window H is connected to the first first electrode line E1(1), and the first first connection line 144a(1) spans the second first electrode line E1(2) to the fourth first electrode line E1 (4), and is not connected to the second first electrode line E1(2) to the fourth first electrode line E1(4), as shown in FIG.

In this embodiment, the four first connection lines 144a are only connected to the first first electrode line E1(1), and the three first connection lines 144a are only connected to the second first electrode line E1 (2). The two first connection lines 144a are connected only to the third first electrode line E1(3), and the one first connection line 144a is connected only to the fourth first electrode line E1(4). Specifically, the first first electrode line E1(1) is far away from the pad 142, and thus is used to connect the first first electrode line E1(1) and the corresponding pad 142 (the leftmost connection) The first connection line 144a of the pad has a longer length and thus a higher conductive impedance. In contrast, the first connection line 144a for connecting the fourth first electrode line E1 (4) and the corresponding pad 142 (the fourth from the left in FIG. 2) has a shorter length and thus has a shorter Low conduction impedance. Accordingly, a plurality of strips of the first connection line 144a connected to the first first electrode line E1(1) may be disposed to reduce the overall conduction resistance thereof, and sequentially connected to the second to fourth first electrode lines E1. (2) The number of the first connection lines 144a of ~E1(4), so that the first to fourth first electrode lines E1(1) to E1(4) can be lowered. The difference in impedance (preferably maintained within about 10%), thereby improving the accuracy of touch sensing.

It should be noted that the present invention does not limit the number of first electrode lines and the first connection lines connected to the respective first electrode lines. For example, the active device array substrate 100 can have 26 first electrode lines, wherein the first first electrode line can connect 26 first connection lines 144a, and the second first electrode line can connect 25 first connections. Line 144a, and so on, the 26th first electrode line can be connected to one first connection line 144a. Those skilled in the art can adjust the number of first connection lines 144a connected by different first electrode lines according to design requirements.

On the other hand, the display area 102d of the active device array substrate 100 can be divided into a first region R1 and a second region R2. The first connection line 144a located in the first region R1 is connected to the first electrode lines E1(1) to E1(4) through the contact window H. The first connection line 144a located in the second region R2 is not connected to the first electrode lines E1(1) to E1(4). 5A is a cross-sectional view taken along line A-A' of FIG. 4A, and FIG. 5B is a cross-sectional view taken along line B-B' of FIG. 4A. Please also refer to FIG. 2, FIG. 4A, FIG. 5A and FIG. 5B to explain the structure of the first region R1 and the second region R2 in detail. In the first region R1, the first connection line 144a has, for example, a connection portion C1, and the first connection line 144a connected to the same first electrode line E1(1) to E1(4) is connected to the adjacent portion through the connection portion C1. The first connection lines 144a are connected together. Further, the first connection line 144a connected to the same first electrode line E1(1) to E1(4) extends to the peripheral area 102p and is connected to the same pad 142.

In addition, in the embodiment, each of the first connecting lines 144a is made of the first strip. The first electrode line E1(1) extends to the fourth first electrode line E1(4) and intersects all of the first electrode lines E1(1) to E1(4). However, the invention is not limited thereto. In other embodiments, the first connection line 144a connected to the second first electrode line E1(2) may extend only from the second first electrode line E1(2) to the fourth first electrode line E1 ( 4) Therefore, the first connection line 144a connected to the second first electrode line E1(2) does not intersect the first first electrode line E1(1).

In the first region R1, the connection portion C1 is connected to the common electrode 160 through the contact window H. In addition, the first region R1 of the active device array substrate 100 is further provided with a common electrode pattern 160a, and the first connection line 144a is connected to the common electrode pattern 160a through the contact window H. The common electrode 160 is divided into a display cycle and a touch cycle in timing control. During the display period, the first connection line 144a provides a common voltage signal to the common electrode 160 (all of the first electrode lines E1(1) to E1(4)). During the touch cycle, the first connection line 144a sequentially supplies the touch scan signal to the first electrode line E1(1)~E1(4). At this time, the first electrode line E1(1)~E1(4) can be It is a touch sensing electrode. In detail, the common electrode 160 and the common electrode pattern 160a can be used as a touch sensing electrode for projected capacitive sensing.

The first connection line 144a in the second region R2 is not connected to the common electrode 160, and thus the common electrode pattern 160a is not provided in the second region R2. In the second region R2, a conductive pattern C2 may be disposed between the adjacent first connection lines 144a. The conductive pattern C2 and the first connection line 144a are separated from each other. The conductive pattern C2 is connected to the common electrode 160 through the contact window H. In other words, since the conductive pattern C2 is a conductive material, the conduction of the common electrode 160 can be further reduced by connecting the conductive pattern C2 to the common electrode 160. impedance.

In other embodiments, the first connecting line 144a connected to the same first electrode line E1(1)~E1(4) may not have a connecting portion C1, wherein the same first electrode line E1 (1) The first connection lines 144a connected to ~E1(4) are separated from each other in the display area 102d, and are connected to the same pad 142 in the peripheral area 102p. A contact window is disposed at a position where the first connection line 144a overlaps the first electrode lines E1(1) to E1(4), and the first connection line 144a and the first electrode line E1(1) to E1(4) pass through the contact window. connection.

Referring to FIG. 5A and FIG. 5B, the active device array substrate 100 may include a conductor layer 103, an insulating layer 104, a conductor layer 105, and an insulating layer 106, wherein the conductor layer 103 is, for example, a gate G formed in the active device 110 of FIG. Scan line SL. The insulating layer 104 covers the conductor layer 103. The conductor layer 105 is, for example, the source S, the drain D, and the data line DL in the active device 110 of FIG. The insulating layer 104 and the insulating layer 106 may be a single layer or a multi-layer structure, and the material of the insulating layer may be selected from the materials described in the first insulating layer 130 or the second insulating layer 150, and the conductive layer 103 and the conductive layer 105 may be It is a single layer or a multilayer structure, and the material of the above conductor layer may be selected from the materials described in the conductive layer 140.

Specifically, a plurality of second electrode lines E2 are disposed on the surface of the substrate of the counter substrate 200, and the second electrode lines E2 extend in the first direction D1. The first electrode lines E1(1) to E1(4) formed by the common electrode 160 are, for example, first sensing electrodes, and the second electrode lines E2 on the opposite substrate 200 are, for example, second sensing electrodes, wherein The first electrode lines E1(1) to E1(4) and the second electrode line E2 may constitute the sensing array E. The first electrode lines E1(1) to E1(4) are, for example, transmission electrodes that are projected capacitive sensing, The second electrode line E2 is, for example, a receiver as a projected capacitive sensing. When a touch event occurs, the sensing array E can pass the signal to the backend processor to calculate the location where the touch occurs, thereby achieving the function of touch sensing. Referring to FIG. 1A, the second electrode line E2 of the present embodiment is disposed, for example, on the outer surface 202a of the substrate 202, however, the present invention is not limited thereto. In other embodiments, the second electrode line E2 may also be disposed on the inner surface 202b of the substrate 202, as shown in FIG. 1B. The second electrode line E2 and the first electrode line E1 are not connected together.

Specifically, since the first connection line 144a for transmitting the signals of the first electrode lines E1(1) to E1(4) is disposed in the display area 102d, the required area of the peripheral area 102 can be reduced, thereby satisfying the touch. The narrow bezel design requirements of the display panel. As shown in FIG. 3, since the first connection line 144a is disposed, for example, overlapping with the scanning line SL, the arrangement of the first connection line 144a does not have much influence on the aperture ratio of the sub-pixel unit P. Further, the first connection line 144a does not contact the scan line SL and it is also electrically insulated from the scan line SL. Moreover, the connection line 144a also does not contact the data line DL and is also electrically insulated from the data line DL.

Referring to FIG. 2 again, the conductive layer 140 further includes a plurality of second connecting lines 144b. The second connection lines 144b extend in the first direction D1, respectively, and are located in the display area 102D. The first connection line 144a and the second connection line 144b are symmetrically disposed with each other, wherein the Jth second connection line 144b intersects with the Kth to Nth first electrode lines E1(1) to E1(4), and via corresponding contacts The window H is connected to the Kth first electrode line E1(1) to E1(4). In other words, the second connection line 144b has a similar connection relationship with the first connection line 144a, so the connection relationship between the second connection line 144b and the first electrode line E1(1)~E1(4) can be referred to. The first connection line 144a is tested. In this embodiment, the first electrode lines E1(1) to E1(4) may pass through the first connection line 144a and the second connection line 144b connected to the same first electrode line E1(1) to E1(4). To drive. Specifically, the display period and the touch period are alternately replaced, wherein the touch period is shorter. At this time, the arrangement of the second connection line 144b can reduce the conduction resistance of the first connection line 144a, thereby reducing the charge and discharge time of the first electrode lines E1(1) to E1(4). For the relationship between the second connection line 144b and the scan line SL and the data line DL, please refer to the relationship between the first connection line 144a and the scan line SL and the data line DL, and details are not described herein.

Further, the active device array substrate 100 further has a third region R3. FIG. 6 is a partially enlarged schematic view of the third region R3. Referring to FIG. 2 and FIG. 6 , specifically, the conductive layer 140 may further include a plurality of third connecting lines 144 c . Each of the third connecting lines 144c extends in the first direction D1. In the third region R3, the third connection line 144c has a connection portion C3 to connect the adjacent third connection line 144c, and the connection portion C3 of the third connection line 144c is connected to the common electrode 160 through the contact window H. As shown in FIGS. 2 and 6, each of the third connection lines 144c is connected to a plurality of common electrodes 160 in the same common electrode serial array 160S via respective contact windows H. It is worth mentioning that the third connection lines 144c connected to the same first electrode line E1(1)~E1(4) may all be connected together. Since the third connection line 144c is made of a conductive material, the conduction impedance of the common electrode 160 can be further reduced by the third connection line 144c and the common electrode 160. In addition, the third connection line 144c and the first connection line 144a and the second connection line 144b are separated from each other and are not connected to each other, and are connected to the third connection line 144c of the different first electrode lines E1(1) to E1(4). They are separated from each other and are not connected to each other. Also in the third zone The common electrode pattern 160a is also provided in R3, and the common electrode pattern 160a and the third connection line 144c are connected through the contact window H. For the relationship between the third connection line 144c and the scan line SL and the data line DL, please refer to the relationship between the first connection line 144a and the scan line SL and the data line DL, and details are not described herein.

As can be seen from FIG. 5A and FIG. 5B, in the present embodiment, the pixel electrode 120 is first formed and then the common electrode 160 is formed. Therefore, the common electrode 160 covers the upper surface of the pixel electrode 120 to form a common electrode top. However, the invention is not limited thereto. In the embodiment illustrated in FIG. 7A and FIG. 7B, the common electrode 160 may be fabricated first to reproduce the pixel electrode 120 to form a structure in which the pixel electrode 120 covers the upper surface of the common electrode 160, that is, the top is a pixel electrode (pixel). The structure of the electrode top). The common electrode 160 may be a single layer or a multi-layer structure, and the material thereof may preferably be selected from the materials described in the pixel electrode 120, or other suitable conductive materials.

The top view of the active device array substrate 100 shown in FIGS. 7A and 7B is similar to FIG. 2 and FIG. 4A, and FIG. 2 and FIG. 4A may be referred to together. Referring to FIG. 7A and FIG. 7B, in the active device array substrate 100a of the present embodiment, after the common electrode 160 is formed on the insulating layer 106, the pixel electrode 120 is formed on the second insulating layer 150, wherein the common electrode is formed. The pattern of the 160 and the pixel electrode 120 is the same as that of the common electrode 160 and the pixel electrode 120 of the first embodiment. In detail, the first insulating layer 130 covers the common electrode 160 and has a plurality of contact windows H in the first insulating layer 130. The first connection line 144a of the conductive layer 140 and the connection portion C1 are connected to the common electrode 160 through the contact window H. The second insulating layer 150 covers the conductive layer 140 and the first insulating layer 130. The pixel electrode 120 is located on the second insulating layer 150. In addition, in the embodiment of FIG. 7C, an unpatterned first insulating material layer (not labeled) may be formed to cover the common electrode 160. Then, the conductive layer 140 is further formed on the unpatterned first insulating material layer (not labeled) and the unpatterned second insulating material layer (not labeled) covers the conductive layer 140 and the unpatterned first On the layer of insulating material (not shown). Then, the contact window H1 and the contact window H2 having different depths are formed through the same patterning process, and the first insulating material layer (not labeled) can be made into the first insulating layer 130 and the second insulating material layer can be formed (not labeled) A second insulating layer 150 is formed. The contact window H1 is located in the second insulating layer 150, and the contact window H2 is located in the first insulating layer 130 and the second insulating layer 150. Thereafter, the conductive pattern 120c is formed again. The conductive pattern 120c fills the contact window H1 and the contact window H2 to connect the common electrode 160 with the conductive layer 140. The conductive pattern 120c may be fabricated in the same process as the pixel electrode 120, but the conductive pattern 120c and the pixel electrode 120 are separated from each other and are not connected to each other.

In addition, in the structure in which the top is a pixel electrode top, the conductive layer 140, the common electrode 160, and the pixel electrode 120 may have other different layouts, which will be described below by other embodiments.

8A to 8C are top plan views of a first region, a second region, and a third region of an active device array substrate according to another embodiment of the present invention. 9A to 9B are schematic cross-sectional views taken along line C-C' and line D-D' of Fig. 8A, respectively. In addition, FIG. 8D further illustrates the common electrode 160, the common electrode pattern 160a, the scan line SL, and the common wiring COM of FIGS. 8A to 8C to clearly illustrate the layout of the common electrode 160. Moreover, in order to clearly illustrate the arrangement relationship of the respective members, FIGS. 8A to 8C omits the partial members.

In the embodiment of FIG. 4B, each of the common electrodes 160 has, for example, a plurality of slits. Referring to FIGS. 8A, 8D, 9A, and 9B, the common electrode 160 is, for example, a continuous pattern having no slits. The active device array substrate 100b includes a plurality of common wirings COM. Each of the common wirings COM extends in the second direction D2, and the common wiring COM connects the plurality of common electrodes 160 to form one of the common electrode serials 160s.

In more detail, the common electrodes 160 in the plurality of sub-pixel units P in the second direction D2 are connected together to form a common electrode group. Here, the common electrode 160 in the three sub-pixel units P is connected together to form a common electrode group as an example. Of course, the invention is not limited thereto. In other embodiments, the common electrodes 160 in two or more sub-pixel units P may be connected together to form a common electrode group. In this embodiment, any two sets of common electrode groups are separated from each other, and a plurality of sets of common electrode groups arranged in the second direction D2 are electrically connected together through a common wiring COM, as shown in FIG. 8D.

Specifically, the common wiring COM is formed, for example, in the same process as the scanning line SL, and the common wiring COM extends in the second direction D2. The common wiring COM and the scanning line SL are separated from each other and electrically insulated. One of the common electrodes 160 of the common electrode group is connected to the common wiring COM via the contact window H2. Thus, each of the common wirings COM can electrically connect the plurality of sets of the common electrode groups to form one of the common electrodes extending in the second direction D2. Tandem 160s. Furthermore, each of the two or more common electrode serials 160s is connected to each other to form one of the first electrode lines E1. In addition, between the two sets of the common electrode groups 160, the common electrode 160 is further disposed. The common electrode patterns 160a are separated from each other.

Referring to FIGS. 9A and 9B, in the present embodiment, the first insulating layer 130 as shown in FIGS. 7A to 7C is not disposed on the active device array substrate 100b, and thus the conductive layer 140 is directly disposed on the common electrode 160. In detail, the conductive layer 140 includes a plurality of pads 142 (as shown in FIG. 2 ), a plurality of first connection lines 144 a , and a plurality of conductive wires 146 . The first connection line 144a is mainly disposed on the common electrode pattern 160a. When the first connection line 144a is electrically connected to the predetermined first electrode line E1, the first connection line 144a can be electrically connected to the common electrode 160 via the connection portion C4. . The conductive wiring 146 is directly disposed on the common electrode 160. Since the conductive wiring 146 is made of a conductive material, the conductivity of the common electrode 160 can be increased and the conduction resistance of the common electrode 160 can be lowered. Further, the first connection line 144a extends in the first direction D1 to be electrically connected between the first electrode line E1 and the pad 142, so the first connection line 144 spans the plurality of first electrode lines E1 to form a continuous wire. In contrast, the conductive wirings 146 disposed on the different first electrode lines E1 are not connected to each other.

The pixel electrode 120 is disposed on the second insulating layer 150, and the pixel electrode 120 is electrically connected to the lower drain D (shown in FIG. 2) through the contact window H1. In the embodiment, the pixel electrode 120 has a plurality of slits. When the pixel electrode 120 and the common electrode 160 are driven, an electric field can be formed between the pixel electrode 120 and the common electrode 160 to drive the active device array substrate. Display media above 100b.

Referring to FIG. 8B and FIG. 8D, in the second region R2, the first connection line 144a is not electrically connected to the first electrode line E1. In detail, a connection portion as shown in FIG. 8A is not provided between the first connection line 144a and the common electrode 160 in the second region R2. C4, therefore, the first connection line 144a is only electrically connected across the plurality of first electrode lines E1 and not to the first electrode line E1.

Referring to FIG. 8C and FIG. 8D, in the third region R3, the conductive layer 140 includes a plurality of third connection lines 144c. Each of the third connecting lines 144c extends in the first direction D1. The third connection line 144c is electrically connected to the common electrode 160 via the connection portion C5. Further, since the third connection line 144c is made of a conductive material, the third connection line 144c can further reduce the conduction resistance of the common electrode 160. The third connection line 144c and the first connection line 144a are separated from each other and are not connected to each other, and the third connection lines 144c connected to the different first electrode lines E1 are separated from each other and are not connected to each other. Further, a common electrode pattern 160a is also provided in the third region R3, and the common electrode pattern 160a is directly connected to the third connection line 144c.

Referring to FIG. 2 again, the first connecting line 144a located at the innermost side of the display area 102d and the second connecting line 144b located at the innermost side of the display area 102d have a first spacing d1 between any two adjacent first connecting lines 144a. There is a second spacing d2, and any two adjacent second connecting lines 144b have a third spacing d3, wherein the first spacing d1 is substantially greater than the second spacing d2 and the third spacing d3. Preferably, the first connection line 144a is disposed adjacent to the edge of the display area 102d, and the second connection line 144b is disposed adjacent to the other edge of the display area 102d. In other words, the first connection line 144a and the second connection line 144b are collectively disposed on both sides within the display area 102d. Moreover, in this embodiment, preferably, the third connection line 144c is located between the first connection line 144a and the second connection line 144b.

However, the invention is not limited thereto. In the embodiment of FIG. 10, the first connection line 144a located at the innermost side of the display area 102d of the active device array substrate 100a is in position There is a first spacing d1 between the second connecting lines 144b on the innermost side of the display area 102d, a second spacing d2 between any two adjacent first connecting lines 144a, and a spacing between any two adjacent second connecting lines 144b. The three pitches d3, and the first pitch d1, the second pitch d2 and the third pitch d3 are substantially equal, as shown in FIG. In other words, the first connection line 144a and the second connection line 144b are uniformly dispersed in the display area 102d. Moreover, a third connection line 144c may be disposed between the two adjacent first connection lines 144a, between the two adjacent second connection lines 144b, and between the adjacent first connection lines 144a and the second connection lines 144b. Further, the third connection line 144c and the first connection line 144a and the second connection line 144b are separated from each other and are not connected to each other. Furthermore, the third connection lines 144c connected to the different first electrode lines E1(1) to E1(4) are separated from each other and are not connected to each other. For the connection relationship between the first connection line 144a and the second connection line 144b, please refer to the related description of FIG. 2, and no further description is made here. It should be noted that the layout of the pixel electrode 120 and the common electrode 160 is not limited in the layout shown in the embodiment of FIG. In other words, in the embodiment shown in FIG. 10, the pixel electrode 120 and the common electrode 160 may be sequentially formed, or the common electrode 160 and the pixel electrode 120 may be sequentially formed.

Further, in the embodiment shown in FIG. 11, the active device array substrate 100b further includes a plurality of auxiliary connection lines 170. Each of the auxiliary connecting wires 170 extends in the first direction D1. The auxiliary connection line 170 is located in the peripheral area 102p. Each of the auxiliary connecting lines 170 is connected in parallel with the corresponding first connecting line 144a and connected between the corresponding first electrode lines E1(1) to E1(4) and the pad 142. The setting of the auxiliary connecting line 170 can further reduce the corresponding Conduction impedance of the first electrode lines E1(1) to E1(4). The auxiliary connecting lines 170 are separated from each other and are not connected to each other. In addition, the first connection line of this embodiment The connection relationship between the 144a and the second connection line 144b is shown in FIG. 2, but is not limited thereto. In other embodiments, a plurality of auxiliary connecting lines 170 can also be used in FIG. It should be noted that the layout of the pixel electrode 120 and the common electrode 160 is not limited in the layout shown in the embodiment of FIG. In other words, in the embodiment shown in FIG. 11, the pixel electrode 120 and the common electrode 160 may be sequentially formed, or the common electrode 160 and the pixel electrode 120 may be sequentially formed.

In summary, the present invention provides a first connection line for transmitting a signal of the first electrode line to the pad in the display area of the active device array substrate, thereby reducing the required area of the peripheral area, thereby satisfying the touch display panel. Narrow bezel design needs.

100‧‧‧Active component array substrate

102d‧‧‧ display area

102p‧‧‧ surrounding area

140‧‧‧ Conductive layer

142‧‧‧ pads

144a, 144a (1) ‧ ‧ first cable

144b‧‧‧second cable

144c‧‧‧ third cable

160s‧‧‧Common electrode series

D1‧‧‧ first direction

D2‧‧‧ second direction

D1‧‧‧first spacing

D2‧‧‧second spacing

D3‧‧‧ third spacing

E1 (1), E1 (2), E1 (3), E1 (4) ‧ ‧ first electrode line

H‧‧‧Contact window

P‧‧‧ sub-pixel unit

R1‧‧‧ first district

R2‧‧‧Second District

R3‧‧‧ Third District

Claims (18)

An in-cell touch display panel includes: an active device array substrate having a display area, the active device array substrate comprising: a plurality of active components arranged in the display area; a plurality of pixel electrodes located at the a display area, and respectively coupled to the corresponding active elements; a first insulating layer covering the active elements and the pixel electrodes; a conductive layer disposed on the first insulating layer, the conductive layer The device includes: a plurality of pads adjacent to one side of the active device array substrate; and a plurality of first connecting wires respectively extending along a first direction and located in the display region, wherein the first connecting wires are respectively connected to the corresponding ones The second insulating layer is disposed on the conductive layer and has a plurality of contact windows; and a plurality of common electrodes disposed on the second insulating layer and respectively corresponding to the pixel electrodes The common electrodes are arranged in a plurality of common electrode series extending in a second direction, wherein each of the two or more common electrode series is connected to form a first electrode line, so that the active All the common electrodes of the array substrate form N first electrode lines arranged in the first direction, and the Jth first connection lines intersect the Kth to Nth first electrode lines, and via the corresponding contact windows Connected to the Kth first electrode line, J, K, N are positive integers, and K≦N; a pair of substrates corresponding to the active device array substrate, one of the opposite substrates The surface has a plurality of second electrode lines extending along the first direction, and the first electrode lines and the second electrode lines together form a sensing array; and a display medium layer And being sandwiched between the active device array substrate and the opposite substrate. The in-cell touch display panel of claim 1, wherein each of the first connecting lines extends from the first first electrode line to the Nth first electrode line, and all of the first electrodes Lines intersect. The in-cell touch display panel of claim 1, wherein the first connecting lines are adjacent to an edge of the display area. The in-cell touch display panel of claim 1, wherein the conductive layer further comprises a plurality of second connecting lines extending in the first direction and located in the display area, the first The connecting line and the second connecting lines are symmetrically disposed with each other, wherein the Jth second connecting line intersects the Kth to Nth first electrode lines, and is connected to the Kth first electrode line via the corresponding contact window. The in-cell touch display panel of claim 4, wherein a first spacing between the first connecting line and the second connecting line located at an innermost side of the display area, any two adjacent A connecting line has a second spacing between each of the two adjacent second connecting lines, and the first spacing is greater than the second spacing and the third spacing. The in-cell touch display panel of claim 4, wherein the first connecting line located at the innermost side of the display area and the second connecting line have a a first spacing, a second spacing between any two adjacent first connecting lines, a second spacing between any two adjacent second connecting lines, and the first spacing, the second spacing, and the third spacing The spacing is equal. The in-cell touch display panel of claim 1, further comprising a plurality of third connecting lines extending along the first direction, wherein each of the third connecting lines is connected via the corresponding contact windows To several common electrodes in the same common electrode string. The in-cell touch display panel of claim 1, further comprising a plurality of auxiliary connecting lines extending along the first direction and located outside the display area, each of the auxiliary connecting lines and the corresponding one The first connecting lines are connected in parallel and connected between the corresponding first electrode lines and the pads. An in-cell touch display panel includes: an active device array substrate having a display area, the active device array substrate includes: a plurality of active components, the array is arranged in the display area; and a plurality of common electrodes are located in the display In the region, and corresponding to the active component arrangements, the common electrodes are arranged in a plurality of common electrode series extending in a second direction, wherein each of the two or more common electrode serials are connected to each other to form a first electrode line, wherein all common electrodes of the active device array substrate form N first electrode lines arranged in a first direction, N is a positive integer; a conductive layer is disposed at least on the common electrodes The conductive layer includes: a plurality of pads adjacent to one side of the active device array substrate; a plurality of first connecting lines extending along the first direction and located in the display area, wherein the first connecting lines are respectively connected to the corresponding pads, wherein the Jth first connecting line and the Kth to the Nth The first electrode lines intersect and are connected to the Kth first electrode line, J, K are positive integers, and K≦N; a first insulating layer disposed on the conductive layer; and a plurality of pixel electrodes, Disposed on the first insulating layer and located in the display area, the pixel electrodes are respectively coupled to the corresponding active components; a pair of substrates corresponding to the active device array substrate, the opposite substrate a plurality of second electrode lines on a surface, the second electrode lines respectively extending along the second direction, and the first electrode lines and the second electrode lines together form a sensing array; and a display medium The layer is sandwiched between the active device array substrate and the opposite substrate. The in-cell touch display panel of claim 9, wherein each of the first connecting lines extends from the first first electrode line to the Nth first electrode line, and all the first electrodes Lines intersect. The in-cell touch display panel of claim 9, wherein the first connecting lines are adjacent to an edge of the display area. The in-cell touch display panel of claim 9, wherein the conductive layer further comprises a plurality of second connecting lines extending in the second direction and located in the display area, the first The connecting line and the second connecting lines are symmetrically disposed, wherein the Jth second connecting line intersects the Kth to Nth first electrode lines, and Connect to the Kth first electrode line. The in-cell touch display panel of claim 12, wherein the first connecting line located at the innermost side of the display area and the second connecting line have a first spacing, and any two adjacent A connecting line has a second spacing between each of the two adjacent second connecting lines, and the first spacing is greater than the second spacing and the third spacing. The in-cell touch display panel of claim 12, wherein the first connecting line located at the innermost side of the display area and the second connecting line have a first spacing, and any two adjacent A connecting line has a second spacing therebetween, and any two adjacent second connecting lines have a third spacing therebetween, and the first spacing, the second spacing is equal to the third spacing. The in-cell touch display panel of claim 9, further comprising a plurality of third connecting lines extending along the first direction, wherein each of the third connecting lines is connected to the same common electrode string Several common electrodes. The in-cell touch display panel of claim 9, further comprising a plurality of auxiliary connecting lines extending along the second direction and located outside the display area, each of the auxiliary connecting lines and the corresponding one The first connecting lines are connected in parallel and connected between the corresponding first electrode lines and the pads. The in-cell touch display panel of claim 9, further comprising a second insulating layer covering the active components and the common electrode layers, and the conductive layer is disposed on the second insulating layer Upper, wherein the second insulating layer has a plurality of contact windows, and the Jth first connecting line is connected to the Kth via the corresponding contact window First electrode line. The in-cell touch display panel of claim 9, further comprising a plurality of common wires, located in the display area, each of the common wires extending along the second direction and each of the common wires connecting is shared The electrodes form one of the common electrode trains.