TWI479636B - Semiconductor structure and method for manufacturing the same - Google Patents

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor device having an electrostatic discharge protection device and a method of fabricating the same.

Semiconductor structures are used in many products, such as MP3 players, digital cameras, computers, and the like. As applications increase, the demand for semiconductor structures also tends to be smaller, larger circuit densities. However, in semiconductor structures, devices of different functions are often manufactured separately in separate processes, so the process is complicated and costly.

Electrostatic discharge (ESD) is a phenomenon of electrostatic charge transfer between different objects and electrostatic charge accumulation. The time of ESD is very short, only within a few nanoseconds. Very high currents are generated in ESD events, and current values are typically a few amps. Therefore, once the current generated by the ESD flows through the semiconductor structure, the semiconductor structure is usually damaged by the high energy density. Therefore, when an electrostatic charge is generated in a semiconductor structure by a mechanical, human body or charging device, the ESD guard must provide a discharge path to avoid damage to the semiconductor structure. However, in high-voltage electric fields, current ESD protection devices are still unable to effectively provide high-voltage ESD protection performance, such as less than 2KV, so it is difficult to apply to protect various high-voltage devices.

The disclosure relates to semiconductor structures and methods of making the same. The semiconductor structure has excellent operation efficiency, and the manufacturing method is simple and low in cost.

A semiconductor structure is provided. The semiconductor structure includes a first doped region, a second doped region, a first conductive structure and a second conductive structure. The first doped region includes a first contact region. The first doped region and the first contact region have a first conductivity type. The second doped region includes a second contact region. The second doped region and the second contact region have a second conductivity type opposite to the first conductivity type.

A method of fabricating a semiconductor structure is provided. The method includes the following steps. A first doped region is formed in the substrate. The first doped region includes a first contact region. The first doped region and the first contact region have a first conductivity type. A second doped region is formed in the substrate. The second doped region includes a second contact region. The second doped region and the second contact region have a second conductivity type opposite to the first conductivity type. The first doped region is adjacent to the second doped region.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

1 is a top view of a semiconductor structure in an embodiment. 2 and 3 illustrate cross-sectional views of a semiconductor structure in an embodiment. The second figure is drawn along the line AB in Fig. 1. Figure 3 is drawn along the CD line in Figure 1.

Referring to FIG. 1, the semiconductor structure includes a first element region 2, a second element region 4, and a third device region 6.

Referring to FIG. 2, the semiconductor structure in the first device region 2 includes a first doping region 8 and a second doping region 10. The first doped region 8 may include a first contact region 12, a first body doped portion 14 and a side doped portion 16. For example, the doping concentration of the side doping portion 16 is greater than the doping concentration of the first body doping portion 14. The first contact region 12 is formed on the first body doped portion 14 in. The first contact region 12, the first body doped portion 14 and the side doped portion 16 have a first conductivity type such as an N conductivity type. The second doped region 10 may include a second contact region 18 and a second body doped portion 20. The second contact region 18 is formed in the second body doped portion 20. The second contact region 18 and the second body doped portion 20 have a second conductivity type opposite to the first conductivity type. The second conductivity type is, for example, a P conductivity type. The side doped portion 16 of the first doped region 8 is adjacent between the first body doped portion 14 and the second body doped portion 20 of the second doped region 10. In an embodiment, the first contact region 12 and the second contact region 18 are respectively heavily doped regions.

Referring to FIG. 2, the dielectric structure 22 is formed on the first doping region 8. In an embodiment, the first contact region 12 of the first doped region 8 is defined by the dielectric structure 22. In more detail, for example, the dielectric structure 22 includes a first dielectric portion 24 and a second dielectric portion 26 that are separated from each other, wherein the first contact region 12 is interposed between the first dielectric portion 24 and the second portion. Between the dielectric portions 26.

A top doped layer 28 may be formed in the first body doped portion 14 between the first contact region 12 and the second contact region 18. In one embodiment, the top doped layer 28 has a second conductivity type, such as a P conductivity type.

The gate structure 30 may be formed on the side doping portion 16 of the first doping region 8 or the second body doping portion 20 of the second doping region 10 between the first contact region 12 and the second contact region 18. . The gate structure 30 can include a gate dielectric layer at the bottom and a gate electrode layer on the gate dielectric layer. The gate dielectric layer can include an oxide or a nitride such as hafnium oxide or tantalum nitride. The gate electrode layer may include a metal or polysilicon.

The third contact region 32 may form a second body doping in the second doping region 10 Part 20 of it. The third contact region 32 may have a first conductivity type such as an N conductivity type. In one embodiment, the third contact region 32 is a heavily doped region.

The first conductive structure 34 is electrically connected to the first contact region 12 of the first doping region 8 . The second conductive structure 36 is electrically connected to the second contact region 18 of the second doping region 10 . The first conductive structure 34 and the second conductive structure 36 respectively include the conductive plug 74 and the conductive plug 40 in the inter-metal dielectric layer (IMD) 44 at different levels, and the interlayer dielectric layer (ILD) 98. Conductive layer 38 and conductive layer 42. The conductive plug 74, the conductive layer 38, the conductive plug 40 and the conductive layer 42 are electrically connected to each other. Conductive plug 74, conductive layer 38, conductive plug 40, and conductive layer 42 may each comprise a metal such as tungsten, copper, or the like.

The first doped buried region 46 formed in the substrate 48 is located under the second doped region 10. The first doped buried region 46 has a first conductivity type such as an N conductivity type. The second doped buried region 50 formed in the substrate 48 is located under the first doped region 8. The second doped buried region 50 has a first conductivity type such as an N conductivity type. Substrate 48 can have a second conductivity type, such as a P conductivity type.

Referring to FIG. 2, in the embodiment, the semiconductor structure in the first element region 2 is used as an electrostatic discharge protection device, such as a diode electrostatic discharge protection device. For example, the first conductive structure 34 is used to direct the current generated by the user touching the semiconductor structure to the first contact region 12, and then the current flows through the first body doped portion 14, the side doped portion 16 and The second body is doped to the portion 20 and to the second contact region 18 and the third contact region 32. The second conductive structure 36 is used to conduct current away from the first contact region 12. This can be used as an electrostatic discharge protection to avoid grain burnout. In an embodiment, the second conductive structure 36 is electrically connected to the ground. Therefore, the semiconductor structure located in the first element region 2 can be used to protect other component regions such as the second element shown in FIG. The semiconductor structure in the device region 4 and the third device region 6.

Referring to FIGS. 1 and 2, the electrostatic discharge protection effect of the semiconductor structure (electrostatic discharge protection device) located in the first element region 2 can be improved by the following components. For example, the first contact region 12 defined by the dielectric structure 22 can be used to collect an electrostatic discharge current to stabilize the opening device. The use of side doped portions 16 provides more donors to enhance the ability of electrostatic discharge. The first doped buried region 46 and the second doped buried region 50 can provide more donor bodies to enhance the ability of electrostatic discharge.

The difference between the semiconductor structure in the second element region 4 shown in FIG. 3 and the semiconductor structure in the first device region 2 shown in FIG. 2 is that the side doping portion shown in FIG. 2 is omitted. 16. That is, the first body doping portion 14 of the first doping region 8 and the second body doping portion 20 of the second doping region 10 are adjacent to each other. Furthermore, the second doped buried region 50 shown in Fig. 2 is omitted. Referring to FIGS. 1 and 3, in the second element region 4, the second body doping portion 20 of the second doping region 10 surrounds the first body doping portion 14 of the first doping region 8. . The second body doped portion 20 can provide self-isolation of the semiconductor structure in the second device region 4.

Referring to FIGS. 1 and 3, in the embodiment, the semiconductor structure in the second element region 4 is a metal oxide semiconductor (MOS) device, such as a high voltage NMOS or an ultra high voltage NMOS. For example, the first contact zone 12 is used as a drain. The third contact region 32 serves as a source. The second contact zone 18 serves as a base.

Referring to FIGS. 1 and 3, in the embodiment, the third component region 6 is a high voltage region in which suitable devices such as a low voltage MOS, a BJT, a capacitor, a resistor, etc., may be disposed. Please refer to Figure 3, for example, A doped buried layer 52 is formed in the substrate 48. A well region 54 is formed on the doped buried layer 52. Well zone 56 and well zone 58 are formed in well zone 54. The heavily doped region 60 is formed in the well region 56. The heavily doped region 62 and the heavily doped region 64 are formed in the well region 58. In one embodiment, the doped buried layer 52, the well region 54, the well region 56, the heavily doped region 60, and the heavily doped region 64 have a first conductivity type, such as an N conductivity type. The well region 58 and the heavily doped region 62 have a second conductivity type such as a P conductivity type. Dielectric 66 is between the heavily doped region 60 and the heavily doped region 62.

The semiconductor structure shown in FIG. 3 also includes a well region 68 on the substrate 48. The heavily doped region 70 is formed in the well region 68. In one embodiment, well region 68 and heavily doped region 70 have a second conductivity type, such as a P conductivity type.

Referring to FIG. 3, in the embodiment, the junction depth of the first body doped portion 14 is sufficient to maintain a high voltage operation. The top doped layer 28 is based on the concept of reducing the surface field (RESURF). The doped buried layer 52 can avoid the occurrence of punch through from the third element region 6 (high voltage region) to the semiconductor structure (ground portion). The first doped buried region 46 can provide isolation between the third contact region 32 (source) and the semiconductor structure.

FIG. 1 only shows the second doped region 10 of the semiconductor structure in the first element region 2, the first contact region 12 and the third contact region 32, and the second doped region of the semiconductor structure in the second device region 4. 10. First contact zone 12 and third contact zone 32.

4 to 8 illustrate a manufacturing flow of the semiconductor structure in the first element region 2 as shown in FIG. 2. Referring to FIG. 4, a first doped buried region 46 and a second doped buried region 50 are formed in the substrate 48. The first doped buried region 46 and the second doped buried region 50 may utilize a patterned mask layer (not Shown, the portion of the substrate 48 that is not covered is doped. After the doping step, the patterned mask layer is removed. After the doping step, an annealing step may also be performed to diffuse the first doped buried region 46 and the second doped buried region 50. Epitaxial layer 72 can be formed on substrate 48. In one embodiment, the epitaxial layer 72 has a second conductivity type, such as a P conductivity type. In another embodiment, the epitaxial layer 72 has a first conductivity type, such as an N conductivity type. The use of an epitaxial layer 72 having an N conductivity type can help increase the substrate pressure of the semiconductor structure.

Referring to FIG. 5, the unmasked portions of the substrate 48 and the epitaxial layer 72 may be doped using a patterned mask layer (not shown) to form the first body doped portion 14. After the doping step, the patterned mask layer is removed. After the doping step, an annealing step may also be performed to diffuse the first body doped portion 14. The unmasked portions of the substrate 48 and the epitaxial layer 72 may be doped using a patterned mask layer (not shown) to form the second body doped portion 20. After the doping step, the patterned mask layer is removed. After the doping step, an annealing step may also be performed to diffuse the second body doped portion 20.

Referring to FIG. 6, the unmasked portion of the first body doped portion 14 may be doped to form the side doped portion 16 by using a patterned mask layer (not shown). After the doping step, the patterned mask layer is removed. After the doping step, an annealing step may also be performed to diffuse the side doped portion 16.

Referring to FIG. 7, a portion of the first body doped portion 14 that is not covered may be doped using a patterned mask layer (not shown) to form a top doped layer 28. After the doping step, the patterned mask layer is removed.

Please refer to Figure 8, which can be patterned using a mask layer (not shown). A dielectric structure 22 is formed on the uncovered portion of the first body doped portion 14 and the epitaxial layer 72. In this embodiment, the dielectric structure 22 is a field oxide (FOX). The patterned mask layer is then removed. A gate structure 30 is formed on the side doped portion 16 and the second body doped portion 20. The method for forming the gate structure 30 may include forming a gate dielectric layer on the side doped portion 16 and the second body doped portion 20, forming a gate electrode layer on the gate dielectric layer, and then patterning the gate dielectric layer. Formed with a gate electrode layer.

Referring to FIG. 8, a patterned mask layer (not shown) may be used to dope the uncovered portions of the first body doped portion 14 and the second body doped portion 20, respectively. The first contact region 12 and the third contact region 32. After the doping step, the patterned mask layer is removed.

Referring to FIG. 8, a portion of the second body doped portion 20 that is not covered may be doped using a patterned mask layer (not shown) to form a second contact region 18. After the doping step, the patterned mask layer is removed.

Referring to FIG. 2, the first conductive structure 34 and the second conductive structure 36 are formed. The forming method of the conductive plug 74 and the conductive plug 40 of the first conductive structure 34 and the second conductive structure 36 includes forming a through hole in the inter-metal dielectric layer (IMD) 44, and then filling the through hole with a conductive material. form. The method for forming the conductive layer 38 and the conductive layer 42 of the first conductive structure 34 and the second conductive structure 36 includes forming a conductive film on the inter-metal dielectric layer 44 and then patterning the conductive film. An interlayer dielectric (ILD) 98 fills the openings in the conductive layer 38.

In an embodiment, the process of the semiconductor structure in the first device region 2 can be integrated with the process of the semiconductor structure in the other device regions, thereby forming a semiconductor structure in the first device region 2 (eg, an electrostatic discharge protection device) It does not require the use of an additional reticle, which simplifies the process and reduces manufacturing costs. In the embodiment, the first element region 2, the second element region 4 and the similar portion of the semiconductor structure in the third element region 6 are simultaneously formed. For example, the first body doped portions 14 shown in FIGS. 2 and 3 are formed simultaneously. The second body doped portion 20 shown in Fig. 2 and Fig. 3 is formed simultaneously. The first contact region 12 and the third contact region 32 are simultaneously formed. Embodiments can also be applied to mix-mode or analog circuit designs such as light-emitting diodes, energy-saving lamps, ballasts, motor drives, and the like.

FIG. 9 is a cross-sectional view showing the semiconductor structure in the first element region 102 in an embodiment. The difference between the semiconductor structure shown in FIG. 9 and the semiconductor structure shown in FIG. 2 is that the side doped portion 116 includes a first sub-portion portion 176 and a second sub-side portion 178. The second side portion 178 is formed in the first side portion 176 by a doping step. In the embodiment, the first side portion 176 and the second side portion 178 have a first conductivity type such as an N conductivity type.

FIG. 10 is a cross-sectional view showing the semiconductor structure in the first element region 202 in an embodiment. The difference between the semiconductor structure illustrated in FIG. 10 and the semiconductor structure illustrated in FIG. 2 is that the top doped layer 228 includes a plurality of doped layer portions 280, 282, wherein the doped layer portion 280 and the doped layer Portions 282 are arranged longitudinally.

11 is a cross-sectional view showing the semiconductor structure in the first device region 302 in an embodiment. The difference between the semiconductor structure illustrated in FIG. 11 and the semiconductor structure illustrated in FIG. 2 is that the top doped layer 328 includes a plurality of doped layer portions 384, 386, 388, 390, 392, 394, 396. Doped layer portion 384, doped layer portion 386, doped layer portion 388, doped layer portion 390, the doped layer portion 392, the doped layer portion 394 and the doped layer portion 396 are arranged laterally and separated from each other.

Figure 12 is a cross-sectional view showing the semiconductor structure in the first device region 402 in an embodiment. The difference between the semiconductor structure shown in FIG. 12 and the semiconductor structure shown in FIG. 2 is that the dielectric structure 422 is shallow trench isolation (STI).

Figure 13 is a cross-sectional view showing the semiconductor structure in the first device region 502 in an embodiment. The difference between the semiconductor structure shown in FIG. 13 and the semiconductor structure shown in FIG. 2 is that the dielectric structure 22 shown in FIG. 2 is omitted. This embodiment can reduce manufacturing costs.

Figure 14 is a cross-sectional view showing the semiconductor structure in the first element region 602 in an embodiment. Compared to the semiconductor structure illustrated in FIG. 2, the semiconductor structure illustrated in FIG. 14 has a first conductive structure 634 and a second conductive structure 636 having a small number (eg, one layer). This embodiment can reduce manufacturing costs.

Figure 15 is a cross-sectional view showing the semiconductor structure in the first element region 702 in an embodiment. The difference between the semiconductor structure shown in FIG. 15 and the semiconductor structure shown in FIG. 2 is that the first doped buried region 46 and the second doped buried region 50 shown in FIG. 2 are omitted. Furthermore, the second body doped portion 720 shown in Fig. 15 has a shallower depth than the second conductive structure 36 shown in Fig. 2.

Figure 16 is a cross-sectional view showing the semiconductor structure in the first element region 802 in an embodiment. The difference between the semiconductor structure shown in FIG. 16 and the semiconductor structure shown in FIG. 2 is that an epitaxial layer 872 having a first conductivity type such as an N conductivity type is used, and thus the first embodiment shown in FIG. 2 can be omitted. The doped portion 14 is integrally formed.

Figure 17 is a cross-sectional view showing the semiconductor structure in the first device region 902 in an embodiment. The difference between the semiconductor structure illustrated in FIG. 17 and the semiconductor structure illustrated in FIG. 16 is that the side doped portion 916 includes a first side portion 976 and a second side portion 978. The second side portion 978 is formed in the first side portion 976 by a doping step. In the embodiment, the first side portion 976 and the second side portion 978 have a first conductivity type such as an N conductivity type.

Figure 18 is a cross-sectional view showing the semiconductor structure in the first device region 1002 in an embodiment. The difference between the semiconductor structure shown in FIG. 18 and the semiconductor structure shown in FIG. 16 is that the first doped buried region 846 and the second doped buried region 850 shown in FIG. 16 are omitted.

In an embodiment, the semiconductor structure (electrostatic discharge protection device) formed in the first component region can provide electrostatic discharge protection substantially greater than 3 kV. The breakdown voltage of the semiconductor structure (electrostatic discharge protection device) in the first element region is greater than 650V. A semiconductor structure (eg, an ultra-high voltage NMOS) formed in the second element region may have a breakdown voltage greater than 650V. For example, it can be seen from the results of the electrostatic discharge protection test shown in Fig. 19 that the electrostatic discharge protection device of the embodiment can protect the MOS device from operating voltage after electrostatic action substantially greater than 2 kV. In contrast, when the electrostatic discharge protection device of the comparative example is electrostatically activated by substantially more than 2 kV, the operational efficiency of the MOS device has been destroyed.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

2, 102, 202, 302, 402, 502, 602, 702, 802, 902, 1002‧‧‧First component area

4‧‧‧Second component area

6‧‧‧ third component area

8‧‧‧First doped area

10‧‧‧Second doped area

12‧‧‧First contact area

14‧‧‧First body doping

16, 116, 916‧‧‧ side doping

18‧‧‧Second contact area

20, 720‧‧‧ second body doping

22, 422‧‧‧ dielectric structure

24‧‧‧First dielectric part

26‧‧‧Second dielectric part

28, 228, 328‧‧‧ top doped layer

30‧‧ ‧ gate structure

32‧‧‧ Third contact area

34,634‧‧‧First conductive structure

36, 636‧‧‧Second conductive structure

38, 42‧‧‧ conductive layer

40, 74‧‧‧ conductive plug

44‧‧‧Metal interlayer dielectric layer

46, 846‧‧‧ first doped burial area

48‧‧‧Base

50, 850‧‧‧Second-doped burial area

52‧‧‧Doped burial layer

54, 56, 58, 68‧‧ ‧ well area

60, 62, 64, 70‧‧‧ heavily doped areas

66‧‧‧Dielectric

72, 872‧‧‧ epitaxial layer

98‧‧‧Interlayer dielectric layer

176, 976‧‧‧ first side part

178, 978‧‧‧ second side part

280, 282, 384, 386, 388, 390, 392, 394, 396‧‧‧ doped layer parts

1 is a top view of a semiconductor structure in an embodiment.

2 is a cross-sectional view showing a semiconductor structure in an embodiment.

3 is a cross-sectional view showing a semiconductor structure in an embodiment.

4 to 8 illustrate a manufacturing process of a semiconductor structure in an embodiment.

Figure 5 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 6 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 7 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 8 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 9 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 10 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 11 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 12 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 13 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 14 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 15 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 16 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 17 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 18 is a cross-sectional view showing a semiconductor structure in an embodiment.

Fig. 19 shows the results of the electrostatic discharge protection test of the examples and comparative examples.

2‧‧‧First component area

8‧‧‧First doped area

10‧‧‧Second doped area

12‧‧‧First contact area

14‧‧‧First body doping

16‧‧‧ side doping

18‧‧‧Second contact area

20‧‧‧Second body doped part

22‧‧‧Dielectric structure

24‧‧‧First dielectric part

26‧‧‧Second dielectric part

28‧‧‧ top doped layer

30‧‧ ‧ gate structure

32‧‧‧ Third contact area

34‧‧‧First conductive structure

36‧‧‧Second conductive structure

38, 42‧‧‧ conductive layer

40, 74‧‧‧ conductive plug

44‧‧‧Metal interlayer dielectric layer

46‧‧‧First doped burial area

48‧‧‧Base

50‧‧‧Second-doped burial area

52‧‧‧Doped burial layer

54, 56, 58, 68‧‧ ‧ well area

60, 62, 64, 70‧‧‧ heavily doped areas

66‧‧‧Dielectric

72‧‧‧Elevation layer

98‧‧‧Interlayer dielectric layer

Claims (9)

A semiconductor structure comprising: a first doped region comprising: a first contact region; a first body doped portion; and a side doped portion, wherein the first doped region, the first contact region, The first body doped portion and the side doped portion have a first conductivity type; and a second doped region includes a second contact region, wherein the second doped region and the second contact region have opposite In a second conductivity type of the first conductivity type, the first doping region is adjacent to the second doping region, and the side doping portion is adjacent to the first body doping portion and the second doping region between. The semiconductor structure of claim 1, wherein the semiconductor structure is an electrostatic discharge protection device. The semiconductor structure of claim 1, further comprising a first conductive structure electrically connected to the first contact region, wherein the first conductive structure is used to direct a current to the first contact region . The semiconductor structure of claim 1, further comprising a second conductive structure electrically connected to the second contact region, wherein the second conductive structure is used to conduct a current away from the second contact Area. The semiconductor structure of claim 1, further comprising a dielectric structure formed on the first doped region, wherein the first contact region is defined by the dielectric structure. The semiconductor structure of claim 1, further comprising a dielectric structure formed on the first doped region, wherein the dielectric structure package A first dielectric portion and a second dielectric portion are disposed between the first dielectric portion and the second dielectric portion. The semiconductor structure of claim 1, wherein the side doped portion comprises a first sub-portion portion and a second sub-portion portion, wherein the first sub-portion portion and the second sub-portion portion The side portion has the first conductivity type, and the second sub-side portion is formed in the first sub-side portion. The semiconductor structure of claim 1, further comprising a first doped buried region under the second doped region, wherein the first doped buried region has the first conductivity type. A method of fabricating a semiconductor structure, comprising: forming a first doped region in a substrate, wherein the first doped region comprises: a first contact region; a first body doped portion; and a side doping a portion, wherein the first doped region, the first contact region, the first body doped portion and the side doped portion have a first conductivity type; and a second doped region is formed in the substrate The second doped region includes a second contact region, and the second doped region and the second contact region have a second conductivity type opposite to the first conductivity type, the first doped region is adjacent to The second doped region is adjacent between the first body doped portion and the second doped region.