TWI478389B - Light-emitting diode and manufacturing method thereof - Google Patents

Description

Light-emitting diode and manufacturing method thereof

The present invention relates to a light emitting diode and a method of manufacturing the same.

The present application claims priority based on the Japanese Patent Application No. 2011-055833, filed on Jan. 14, 2011, and the Japanese Patent Application No. 2011-203449, filed on Sep.

A point source type light-emitting diode in which light generated by a light-emitting layer is taken out from a part of an element is known. It is also known that the light-emitting diode of this type has a current narrowing structure for restricting a part of the light-emitting layer in the light-emitting layer to the inside thereof (for example, Patent Document 1). In a light-emitting diode having a current narrow structure, the light-emitting region is limited, and light is emitted from a light exit hole provided directly above the region thereof, thereby obtaining a high light output and enabling the emitted light to be efficiently taken. Into optical parts, etc.

Among the light source type light-emitting diodes, in particular, a Resonant-Cavity Light Emitting Diode (RCLED) is a belly that is constructed to form a standing wave generated in a resonator including two mirrors. The light-emitting layer disposed in the resonator is disposed, and the reflectance of the mirror on the light-emitting side is set to be lower than the reflectivity of the mirror on the substrate side, thereby being patterned by the LED without laser oscillation. A highly efficient light-emitting element that operates (Patent Documents 2, 3). Compared with the conventional light-emitting diode, the resonator-type light-emitting diode has a narrow spectral line width, a high directivity of the emitted light, and a short carrier life due to natural emission depending on the effect of the resonator structure. It is suitable for sensors and the like because of its high speed response and the like.

It is known that a resonator-type light-emitting diode includes a light-removing region in which a direction parallel to a substrate is narrowed, and an upper mirror layer, an active layer, and the like are formed into a pillar structure, and light extraction is performed on a top surface of the pillar structure. The surface of the layer having the opening for light emission (for example, Patent Document 4).

18 is a view showing a resonator-type light-emitting diode in which a lower mirror layer 132, an active layer 133, an upper mirror layer 134, and a contact layer 135 are sequentially provided on a substrate 131, and a resonator-type light-emitting diode is formed. The active layer 133, the upper mirror layer 134, and the contact layer 135 are formed as pillar structures 137, and the protective film 138 is coated with the pillar structure 137 and its surroundings, and an electrode film 139 is formed on the protective film 138. The electrode film 139 in the top surface 137a (light extraction surface) forms an opening 139a for light emission. Reference numeral 140 is a back electrode.

The current narrowing structure of the pillar structure shown in Fig. 18 can also be applied to a non-resonator type point source type light emitting diode.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] JP-A-2005-31842

[Patent Document 2] JP-A-2002-76433

[Patent Document 3] JP-A-2007-299949

[Patent Document 4] Japanese Patent Publication No. 9-283862

When the pillar structure is formed, since the portion other than the pillar structure is removed by anisotropic dry etching after the active layer or the like is formed, the side surface 137b of the pillar structure 137 is phased as shown in FIG. A vertical or sharp tilt is formed for the substrate 131. The side surface of the pillar structure is usually formed by a vapor deposition method or a sputtering method, and then an electrode metal (for example, Au) film is formed by vapor deposition, but the surface is protected on the vertical or steeply inclined side. It is not easy to form the film thickness of the film or the electrode with a metal film, and there is a problem that a film which is discontinuous is easily formed. In the case where the protective film is a discontinuous film (reference numeral A in Fig. 18), in the discontinuous portion, the metal film for the electrode enters the contact active layer or the like to cause leakage. Moreover, when the metal film for electrodes is a discontinuous film (reference numeral B in FIG. 18), it is a cause of a malfunction.

Further, when a portion other than the pillar structure is removed by dry etching, an expensive device is required, and there is a problem that the etching time becomes long.

The present invention has been made in view of the above circumstances, and an object of the invention is to provide a protective film and an electrode film formed thereon having a uniform thickness of a light-emitting diode, and to reduce leakage or power failure to improve yield, and A method of manufacturing a light-emitting diode that can be manufactured at a lower cost than ever before.

The present invention provides the following means.

(1) A light-emitting diode comprising a reflective layer and a compound semiconductor layer containing an active layer on a substrate, wherein the upper portion has a flat portion and has an inclined side surface and a top surface. In the mesa structure portion, at least a part of each of the flat portion and the mesa structure portion is covered with a protective film and an electrode film in sequence, and the mesa structure portion includes at least a part of the active layer, and the inclined side surface is a wet type Etching is formed, and the cross-sectional area in the horizontal direction is formed toward the aforementioned top surface Continuously decreasing, the protective film covering at least a part of the flat portion, the inclined side surface of the mesa structure portion, and a peripheral region of the top surface of the mesa structure portion, and having a top view visible in the periphery The inner side of the region exposes a portion of the surface of the compound semiconductor layer, and the electrode film is in direct contact with the surface of the compound semiconductor layer exposed from the current supply window, and covers at least the protective film formed on the flat portion. In part, a continuous film formed by a light-emitting hole is formed on the top surface of the mesa structure portion.

In the present invention, the term "flat portion" refers to a method in which a compound semiconductor layer is wet-etched to form a mesa-type structure portion, and "flat" is performed by wet etching.

(2) The light-emitting diode according to (1), wherein the reflective layer is a DBR reflective layer.

(3) The light-emitting diode according to (2), wherein the upper DBR reflective layer is provided on a side opposite to the substrate facing the active layer.

(4) The light-emitting diode according to (1), wherein the reflective layer contains a metal.

(5) The light-emitting diode according to any one of (1) to (4) wherein the compound semiconductor layer has a contact layer in contact with the electrode film.

(6) The light-emitting diode according to any one of (1) to (5), wherein the mesa structure portion includes all of the active layer and a part or all of the reflective layer.

The light-emitting diode according to any one of (1) to (6), wherein the mesa-type structural portion has a rectangular shape in plan view.

(8) The light-emitting diode according to (7), wherein each of the inclined side faces of the mesa-type structural portion is formed to be offset with respect to an orientation surface of the substrate.

The light-emitting diode according to any one of the above aspects, wherein the height of the mesa structure portion is 3 to 7 μm, and the width of the inclined side surface in a plan view is 0.5 to 7 μm.

The light-emitting diode according to any one of (1) to (9), wherein the light-emitting apertures are circular or elliptical in plan view.

(11) The light-emitting diode according to (10), wherein the light-emitting aperture has a pore diameter of 50 to 150 μm.

The light-emitting diode according to any one of (1) to (11), wherein the portion on the flat portion of the electrode film has a bonding wire.

The light-emitting diode according to any one of (1) to (12), wherein the light-emitting layer contained in the active layer contains a multiple quantum well.

The light-emitting diode according to any one of (1) to (13), wherein the light-emitting layer contained in the active layer contains ((Al _X1 Ga _1-X1 ) _Y1 In _1-Y1 P ( 0≦X1≦1,0<Y1≦1), (Al _X2 Ga _1-X2 )As(0≦X2≦1), (In _X3 Ga _1-X3 )As(0≦X3≦1)) .

(15) A method of producing a light-emitting diode, comprising: forming a reflective layer and a compound semiconductor layer containing an active layer on a substrate; and wet etching the compound semiconductor layer to form a horizontal cross section a step of forming a mesa-type structural portion that is continuously reduced toward the top surface and a flat portion that is disposed around the mesa-type structural portion; and having a portion of the surface of the mesa-type structural portion that exposes the surface of the compound semiconductor layer a method of forming a protective film on the mesa-type structure portion and the flat portion in the manner of energizing the window; The step of forming the electrode film of the continuous film in such a manner that the surface of the exposed compound semiconductor layer is in direct contact with at least one portion of the protective film formed on the flat portion, and the top surface of the mesa structure portion has a light exit hole .

(16) The method for producing a light-emitting diode according to the above aspect, wherein the wet etching is performed by using a mixed solution of phosphoric acid/hydrogen peroxide water, a mixture of ammonia/hydrogen peroxide water, and a mixture of bromine and methanol. At least one of the group of potassium iodide/ammonia is carried out.

According to the light-emitting diode of the present invention, the upper portion has a flat portion and a mesa structure portion having an inclined side surface and a top surface, and at least a part of each of the flat portion and the mesa structure portion is sequentially covered by the protective film and the electrode film. The mesa structure portion includes at least a part of the active layer, and the protective film covers at least a part of the flat portion, the inclined side surface of the mesa structure portion, and the peripheral portion of the top surface of the mesa structure portion, and has a plan view. An energization window exposing a portion of a surface of the compound semiconductor layer on the inner side of the peripheral region, the electrode film being in direct contact with a surface of the compound semiconductor layer exposed from the self-energizing window, and covering at least a protective film formed on the flat portion A part of the continuous film formed by the light-emitting hole on the top surface of the mesa structure portion. According to the above configuration, it is possible to obtain a high light output and efficiently extract the emitted light into an optical component or the like.

Further, the inclined side surface of the mesa structure portion is formed by wet etching and the cross-sectional area in the horizontal direction is continuously reduced toward the top surface. Since the above configuration is adopted, it is easy to be on the side as compared with the case of the vertical side. The protective film and the electrode film thereon are formed to form a continuous film having a uniform film thickness, so that no leakage or electrification failure due to the discontinuous film is caused, and stable and high-luminance light emission can be ensured. Such an effect is achieved by the effect achieved by the mesa structure portion having the inclined side surface formed by the wet etching, and which is not obtained by the laminated structure inside the light emitting diode or the configuration of the substrate.

According to the light-emitting diode of the present invention, by adopting a configuration in which the reflective layer is made of a metal, light emitted in the light-emitting layer can be reflected at a high reflectance to obtain a high light output.

According to the light-emitting diode of the present invention, by using a configuration in which the reflective layer is a DBR reflective layer, light having a narrow visible line width can be performed. Further, by adopting a configuration in which the upper DBR reflection layer is provided on the opposite side of the active layer opposite to the substrate, the visible spectral line width becomes narrow, and the directivity of the emitted light is high, and the high-speed response can be achieved.

According to the light-emitting diode of the present invention, the compound semiconductor layer is configured to have a contact layer in contact with the electrode film, whereby the contact resistance of the ohmic electrode is lowered to drive at a low voltage.

According to the light-emitting diode of the present invention, the entire structure including the active layer and a part or all of the reflective layer are formed by the use of the mesa structure, so that the light emission is generated in the mesa structure portion, and the light extraction efficiency is improved.

According to the light-emitting diode of the present invention, the mesa-type structure portion is formed in a rectangular shape in plan view, and the influence of the anisotropy of the wet etching at the time of manufacture causes the shape of the mesa to be changed depending on the etching depth. High-precision dimensional shape due to easy access to the console floor area shape.

According to the light-emitting diode of the present invention, the inclined side surfaces of the mesa-type structure portion are formed to be offset with respect to the orientation surface of the substrate, and the anisotropy due to the orientation of the substrate is used to form the rectangular mesa structure portion. The influence of the four sides is alleviated, so that an equal platform shape and a gradient can be obtained.

According to the light-emitting diode of the present invention, the height of the mesa-type structure portion is 3 to 7 μm, and the width of the inclined side surface in the plan view is 0.5 to 7 μm, which is easier to the side than the case of the vertical side surface. The protective film and the electrode film thereon are formed, and a continuous film having a uniform film thickness is formed. Therefore, no leakage or electrification failure due to the discontinuous film is caused, and stable and high-luminance light emission can be ensured.

According to the light-emitting diode of the present invention, the light-emitting aperture is formed in a circular or elliptical shape in plan view, so that a uniform contact area can be easily formed than a structure having a rectangular equiangular portion, and the occurrence of the corner portion can be suppressed. Current concentration and other situations. Further, it is suitable for coupling with an optical fiber or the like on the light receiving side.

According to the light-emitting diode of the present invention, the light-emitting aperture has a hole diameter of 50 to 150 μm, so as to avoid the so-called less than 50 μm, and the current density in the mesa structure portion becomes high, resulting in low current output saturation, and more than 150 μm. At this time, since it is difficult for the current to diffuse toward the entire structure of the mesa structure, the problem of saturation is still output.

According to the light-emitting diode of the present invention, since the portion on the flat portion of the electrode film has a bonding wire, since the wire is bonded at a portion where a flat portion of a sufficient load (and ultrasonic wave) can be applied, A wire bonding with strong joint strength can be achieved.

The method for producing a light-emitting diode according to the present invention includes a mesa-type structural portion formed by wet etching the compound semiconductor layer to form a horizontal cross-sectional area, which is formed to be continuously reduced toward the top surface, and a mesa-type structure disposed on the mesa-type structure. a step of forming a protective film on the mesa structure portion and the flat portion so as to expose a portion of the surface of the compound semiconductor layer on the top surface of the mesa structure portion; The surface of the compound semiconductor layer exposed from the energization window is in direct contact with at least one portion of the protective film formed on the flat portion, and the electrode of the continuous film is formed on the top surface of the mesa structure portion with light exit holes The step of the membrane. By adopting the above configuration, it is possible to obtain a high light output and efficiently take the emitted light into the optical component or the like, and it is easy to form the protective film on the inclined side surface and the upper side as compared with the case of the vertical side surface. Since the electrode film is formed into a continuous film having a uniform film thickness, there is no leakage or electrification caused by the discontinuous film, and a light-emitting diode which can stably emit light with high luminance can be secured. When the pillar structure is formed by the conventional anisotropic dry etching, a vertical side surface is formed, and the mesa-type structure portion is formed by wet etching, and the side surface can be formed to be gently inclined. Further, by forming the mesa structure portion by wet etching, it is possible to shorten the formation time even when the pillar structure is formed by dry etching.

[Formation of the Invention]

Hereinafter, the configuration of the light-emitting diode and the method of manufacturing the same according to the present invention will be described using the drawings. In addition, the following uses the diagram used. In the case where the feature is displayed in an enlarged manner in order to make it easy to understand the feature, the size ratio of each component or the like is not necessarily the same as the actual one. In addition, the materials, the dimensions, and the like described in the following description are merely examples, and the present invention is not limited thereto, and can be appropriately modified and implemented without departing from the scope of the invention.

Further, a layer not described below may be provided in a range that does not impair the effects of the present invention.

[Light Emitting Diode (First Embodiment)]

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a resonator-type light-emitting diode of a light-emitting diode of the present invention. 2 is a perspective view of a light-emitting diode formed on a wafer including the light-emitting diode shown in FIG. 1.

Hereinafter, a light-emitting diode according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

The light-emitting diode 100 shown in FIG. 1 is a light-emitting diode having a reflective layer 2 and a compound semiconductor layer containing the active layer 3 on a substrate 1, and has an upper portion having a flat portion 6 and an inclined side surface as an outer surface. At least a part of each of the flat portion 6 and the mesa structure portion 7 of the mesa structure portion 7 of the top surface 7b and the top surface portion 7b is covered with the protective film 8 and the electrode film 9, and the mesa structure portion 7 contains at least the active layer 3. In part, the inclined side surface 7a is formed by wet etching and the cross-sectional area formation in the horizontal direction is continuously reduced toward the top surface 7b, and the protective film 8 covers at least a part of the flat portion 6, and the inclined side surface 7a of the mesa-type structure portion 7. And a peripheral edge region 7ba of the top surface 7b of the mesa structure portion 7, and having an energization window 8b exposing a part of the surface of the compound semiconductor layer on the inner side of the peripheral region 7ba in plan view, the electrode film 9 is connected to the self-energizing window 8b The surface of the exposed compound semiconductor layer is directly connected Touching, and covering at least one portion of the protective film 8 formed on the flat portion 6, a continuous film formed by the light-emitting holes 9b on the top surface 7b of the mesa-type structure portion 7, and the reflective layer 2 being a DBR reflective layer (Lower DBR Reflective Layer) The upper DBR reflective layer 4 is provided on the opposite side of the active layer 3 opposed to the substrate 1, and the compound semiconductor layer has the contact layer 5 in contact with the electrode film 9.

The mesa-type structure portion 7 of the resonator-type light-emitting diode of the present embodiment has a rectangular shape in plan view, and the light-emitting hole 9b of the electrode film 9 has a circular shape in plan view. The mesa structure portion 7 is not limited to being rectangular in plan view, and the light exit hole 9b is also not limited to being circular in plan view.

The electrode film of the mesa structure portion 7 is provided with a light leakage preventing film 16 for preventing light leakage from the side surface.

Moreover, the back surface electrode 10 is provided in the lower surface side of the board|substrate 1.

In the light-emitting diode of the present invention, as shown in FIG. 2, after a plurality of light-emitting diodes 100 are formed on a wafer-shaped substrate, each light-emitting diode is placed along a dicing street (cut line) 21 ( The broken line 22 is cut by the center line in the longitudinal direction of the cutting path 21 and manufactured. That is, a portion where the laser beam or the blade or the like is touched along the scribe line 21 along the broken line 22 can be cut into the respective light-emitting diodes.

The mesa structure portion 7 has a structure that protrudes upward with respect to the flat portion 6, and has an inclined side surface 7a and a top surface 7b as outer surfaces. In the case of the example shown in FIG. 1, the inclined side surface 7a is an entire layer including the active layer 3, and an electrode film (outer surface electrode film) formed by a protective film on an inclined cross section of the upper DBR layer 4 and the contact layer 5. The surface of the top surface 7b includes a surface for covering the surface of the portion 8d of the central portion of the protective film 8, and a surface of the electrode film 9 (portions of numerals 9ba, 9bb, and 9d).

Further, the inside of the mesa structure portion 7 of the present invention includes at least a part of the contact layer 5, the upper DBR layer 4, and the active layer 3.

In the case of the example shown in FIG. 1, the inside of the mesa structure portion 7 includes the entire layer of the contact layer 5, the upper DBR layer 4, and the active layer 3. The inside of the mesa structure portion 7 may include only a part of the active layer 3, but it is preferable that the entire layer of the active layer 3 is included in the interior of the mesa structure portion 7. The reason is that all of the light that is emitted by the active layer 3 is generated in the mesa-type structure portion, and the light extraction efficiency is improved. Further, a part of the lower DBR layer 2 may be contained inside the mesa structure portion 7.

Further, the inclined side surface 7a of the mesa structure portion 7 is formed by wet etching, and the cross-sectional area in the horizontal direction is continuously reduced from the substrate 1 side toward the top surface. The inclined side surface 7a is formed by wet etching, so that it is convex downward. The height h of the mesa structure portion 7 is 3 to 7 μm, and the width w of the inclined side surface 7a in plan view is preferably 0.5 to 7 μm. The reason is that the side surface of the mesa structure portion 7 is not inclined vertically or obliquely but is gently inclined. Therefore, the protective film or the electrode metal film is likely to have the same film thickness, and there is no need to worry about becoming a discontinuous film. There is no leakage or poor energization caused by the discontinuous film, which ensures stable and high-intensity illumination.

Further, when wet etching having a height of more than 7 μm is performed, the inclined side surface tends to have an overhang shape (reversely tapered shape), which is not preferable. In the overhang shape (reverse taper), it is more difficult to form the protective film or the electrode film with a uniform film thickness and no discontinuous portion than the vertical side surface.

Further, in the present specification, the height h means the surface of the electrode film 9 (portion of the numeral 9c) formed by the protective film on the flat portion 6 up to the surface. The distance in the vertical direction from the surface of the electrode film 9 (portion of the numeral 9ba) of the portion of the protective film 8 of the reference numeral 8ba (see Fig. 1). Further, the width w refers to the lowermost portion of the electrode film 9 (portion of numeral 9a) from the edge of the electrode film 9 (portion of numeral 9ba) covering the portion of the protective film 8 to 8ba to the inclined side surface to which the edge is attached. The horizontal distance of the edge (see Figure 1).

Fig. 3 is an electron micrograph of a cross section in the vicinity of the mesa structure portion 7.

The layer configuration of the example shown in Fig. 3 is the same as that of the later-described embodiment except that the contact layer contains Al _0.3 Ga _0.7 As and the layer thickness is 3 μm.

Since the mesa-type structure portion of the present invention is formed by wet etching, the horizontal cross-sectional area (or width or diameter) of the mesa-type structure portion is formed as it goes toward the substrate side from the top surface side (the direction is downward). The increase rate of the ) becomes larger. According to this shape, it can be determined that the mesa structure portion is formed by wet etching without dry etching.

In the example shown in Fig. 3, the height h is 7 μm and the width w is 3.5 to 4.5 μm.

The mesa structure portion 7 is preferably rectangular in plan view. The reason is that the influence of the anisotropy of the wet etching at the time of manufacture suppresses the shape of the mesa depending on the etching depth, and since the area of each surface of the console structure portion can be easily obtained, a high-precision size can be obtained. shape.

As shown in FIGS. 1 and 2, the position of the mesa structure portion 7 in the light-emitting diode is preferably biased to the side in the long axis direction of the light-emitting diode for the miniaturization of the element. The reason is that since the flat portion 6 is required to be attached Since the width of the line (not shown) is narrowed, the width of the land type structure portion 7 is biased to the other side, and the range of the flat portion 6 can be minimized, and the size of the element can be reduced.

The flat portion 6 is disposed at a portion around the mesa structure portion 7. In the present invention, since the wire bonding is performed at a portion where the flat portion of the electrode film to which a sufficient load (and ultrasonic wave) can be applied, wire bonding with high bonding strength can be realized.

A protective film 8 and an electrode film (outer surface electrode film) 9 are sequentially formed on the flat portion 6, and a bonding wire (not shown) is mounted on the electrode film 9. The material disposed directly under the protective film 8 of the flat portion 6 is determined by the internal structure of the mesa structure portion 7. In the case of the example shown in Fig. 1, the inside of the mesa structure portion 7 includes the contact layer 5, the upper DBR layer 4, and the entire layer of the active layer 3, and the lower layer of the active layer 3, that is, the uppermost portion of the lower DBR layer Since it is disposed directly under the protective film 8 of the flat portion 6, the material immediately below the protective film 8 of the flat portion 6 is placed on the uppermost material of the lower DBR layer.

The protective film 8 includes a portion 8a that covers the inclined side surface 7a of the mesa structure portion 7, and a portion 8c that covers at least a portion of the flat portion 6 (including a flat portion that covers the opposite side with the mesa structure portion 7 interposed therebetween) a portion 8cc); a portion 8ba covering a peripheral portion 7ba of the top surface 7b of the mesa-type structure portion 7; and a portion 8d covering the central portion of the top surface 7b and having a contact layer 5 exposed on the inner side of the peripheral portion 7ba in plan view A portion of the surface of the energization window 8b.

The energization window 8b of the present embodiment is a portion 8ba located below the peripheral region 7ba in the surface of the contact layer 5 of the top surface 7b of the mesa structure portion 7, and a portion 8d positioned below the central portion. Between parts An area between two concentric circles of different diameters is exposed.

The first function of the protective film 8 is provided in the lower surface of the outer surface electrode film 9 for narrowing the region where the light is emitted and the range for extracting light to restrict the flow current between the outer surface electrode film 9 and the back surface electrode 10. The area. That is, after the protective film 8 is formed, the outer surface electrode film is formed over the entire surface including the protective film 8, and then the outer surface electrode film is patterned to form a portion of the protective film 8 even if the outer surface electrode film is not removed, the outer surface No current flows between the electrode film and the back electrode 10. The energization window 8b of the protective film 8 is formed at a current between the back electrode 10 and the back electrode 10 to be formed.

Therefore, the electric current window 8b may be formed in a part of the top surface 7b of the mesa structure portion 7 so that the first function can be provided, and the shape or position of the electric current window 8b is not limited to the shape or position as shown in FIG. .

The second function of the protective film 8 is not a necessary function with respect to the first function which is a necessary function. In the case of the protective film 8 shown in Fig. 1, the second function is equipped in a plan view. On the surface of the contact layer 5 in the light-emitting hole 9a of the outer surface electrode film 9, light can be taken out through the protective film 8, and the surface of the contact layer 5 from which light is taken out is protected.

Further, in the second embodiment to be described later, there is no configuration in which a protective film is formed under the light exit hole, and light is directly taken out from the light exit hole 9b without passing through the protective film, and the second function is not provided.

As the material of the protective film 8, a well-known insulating layer can be used, but since it is easy to form a stable insulating film, a ruthenium oxide film is preferable.

Further, in the present embodiment, since the light is taken out through the protective film 8 (8d), the protective film 8 needs to have light transmissivity.

Further, the film thickness of the protective film 8 is preferably 0.3 to 1 μm. The reason is that When the thickness is 0.3 μm, the insulation is insufficient, and when it exceeds 1 μm, the formation of the film takes too much time.

The electrode film (outer surface electrode film) 9 includes a portion 9a covering a portion 8a of the protective film 8 for covering the inclined side surface 7a, and a portion 9c covering at least the protective film 8 for covering the flat portion 6. a portion 8c; a portion 9ba covering a portion of the protective film 8 covering the peripheral portion 7ba of the top surface 7b of the mesa structure portion 7; a portion 9bb (hereinafter referred to as "contact portion" as appropriate) The power-on window 8b of the buried protective film 8 and the portion 9d cover the outer peripheral portion of the portion 8d of the protective film 8 of the top surface 7b of the mesa-type structure portion 7 for covering the central portion of the top surface 7b.

The first function of the electrode film (outer surface electrode film) 9 is to flow a current between the back electrode 10 and the second function is to limit the range of light emitted by the emission. In the case of the example shown in Fig. 1, the first function is performed by the contact portion 9bb, and the second function is held by the portion 9d of the outer peripheral portion of the portion 8d covering the central portion.

It is also possible to make the protective film a second function by using a non-translucent protective film.

The electrode film 9 may cover the entire protective film 8 of the flat portion 6, or may cover a part thereof, and it is preferable to cover the wide range as much as possible in order to properly mount the bonding wires. From the viewpoint of cost reduction, as shown in FIG. 2, it is preferable that the dicing street 21 at the time of cutting into the respective light-emitting diodes does not cover the electrode film.

Since the electrode film 9 is in contact with the contact layer 5 only by the contact portion 9bb in the top surface 7b of the mesa structure portion 7, the electrode film 9 and the back surface electrode 10 can only flow a current between the contact portion 9bb and the back surface electrode 10. For this purpose, in the light-emitting layer The current concentrate in 13 is in a range overlapping with the light exit hole 9b in a plan view, and since the light is concentrated in the range thereof, the light can be efficiently extracted.

As the material of the electrode film 9, a well-known electrode material can be used, but it is preferable to use AuBe/Au in order to obtain a good ohmic contact.

Further, the film thickness of the electrode film 9 is preferably 0.5 to 2.0 μm. The reason is that not more than 0.5 μm is difficult to obtain uniform and good ohmic contact, and the strength and thickness at the time of bonding are insufficient, and when it exceeds 2.0 μm, the cost is excessively high.

As shown in FIG. 1, a light leakage preventing film 16 may be provided to prevent light emitted from the active layer from leaking from the side surface of the mesa structure portion 7 toward the outside of the element.

As the material of the light leakage preventing film 16, a well-known reflective material can be used. It may be the same AuBe/Au as the electrode film 9.

In the present embodiment, the protective film 8d (8) is formed under the light-emitting hole 9b, and the top surface of the mesa-type structure portion 7 is configured to take out light from the light-emitting hole 9b via the protective film 8d (8).

The shape of the light exit hole 9b is preferably circular or elliptical in plan view. The reason is that it is possible to form a uniform contact region more easily than a structure having a rectangular equiangular portion, and it is possible to suppress the occurrence of current concentration at the corner portion. Further, it is suitable for coupling with an optical fiber or the like on the light receiving side.

The diameter of the light exit hole 9b is preferably 50 to 150 μm. The reason is that when the temperature is less than 50 μm, the current density at the emitting portion is increased, resulting in a low current and saturation of the output. On the other hand, if it exceeds 150 μ, it is difficult for the current to diffuse toward the entire emitting portion, so that the luminous efficiency with respect to the injection current is lowered.

As the substrate 1, for example, a GaAs substrate can be used.

In the case of using a GaAs substrate, it can be produced by a well-known method. A single crystal substrate of a commercial product. The surface of the GaAs substrate for epitaxial growth is preferably smooth. Regarding the surface orientation of the surface of the GaAs substrate, the substrate which is easy to grow by epitaxy, mass-produced (100) plane, and (100) biased within ±20° is the best in terms of quality stability. Further, the plane orientation of the GaAs substrate is preferably in the range of 15° ± 5° from the (100) direction toward the (0-1-1) direction.

For the good crystallinity of the lower DBR layer 2, the active layer 3, and the upper DBR layer 4, the difference in the discharge density of the GaAs substrate is preferably as low as possible. Specifically, for example, it is preferably 10,000 cm ^-2 or less, more preferably 1,000 cm ^-2 or less.

The GaAs substrate can be either n-type or p-type. The carrier concentration of the GaAs substrate can be appropriately selected from the desired electrical conductivity and element configuration. For example, in the case where the GaAs substrate is an n-type doped with Si, a range of a carrier concentration of 1 × 10 ¹⁷ to 5 × 10 ¹⁸ cm ^-3 is preferable. On the other hand, in the case where the GaAs substrate is a p-type doped with Zn, a carrier concentration of 2 × 10 ¹⁸ to 5 × 10 ¹⁹ cm ^-3 is preferable.

The thickness of the GaAs substrate is dependent on the size of the substrate. When the thickness of the GaAs substrate is thinner than the appropriate range, the GaAs substrate may be broken during the production process of the compound semiconductor layer. On the other hand, when the thickness of the GaAs substrate is thicker than the appropriate range, the material cost increases. For this reason, in the case where the substrate size of the GaAs substrate is large, for example, in the case of a diameter of 75 mm, in order to prevent cracking during transportation, the thickness is preferably 250 to 500 μm. Similarly, in the case of a diameter of 50 mm, the thickness of 200 to 400 μm is the best, and in the case of a diameter of 100 mm, the thickness of 350 to 600 μm is the best.

Thus, by increasing the thickness of the substrate in accordance with the substrate size of the GaAs substrate, the compound semiconductor layer caused by the active layer 3 can be reduced. Warping. Thereby, since the temperature distribution in the epitaxial growth becomes uniform, the wavelength distribution in the plane of the active layer 3 can be made small. Further, the shape of the GaAs substrate is not particularly limited to a circular shape, and there is no problem even if it is a rectangle or the like.

Regarding the structure of the reflective layer (lower DBR layer 2) and the compound semiconductor layer (active layer 3, upper DBR layer 4, and contact layer 5), a well-known functional layer can be added as appropriate. For example, a current diffusion layer for diffusing the element drive current to the entire light-emitting portion in a planar manner, and a well-known layer such as a current blocking layer or a current confinement layer for restricting a flow region of the element drive current may be provided. structure.

The reflective layer (lower DBR layer) and the compound semiconductor layer formed on the substrate 1 are formed by sequentially laminating the lower DBR layer 2, the active layer 3, and the upper DBR layer 4.

The DBR (Distributed Bragg Reflector) layer is a layer containing two layers of alternating thickness λ/(4n) (λ: wavelength of light to be reflected in vacuum, n: refractive index of layer material) and different refractive indices. Multi-layer film. In terms of reflectance, when the difference in refractive index between the two types is large, high reflectance can be obtained with a multilayer film of a small number of layers. The feature is that the reflection film is not reflected by a certain surface as usual, but the entirety of the multilayer film causes reflection based on the interference phenomenon of light.

The material of the DBR layer is preferably transparent with respect to the emission wavelength, and is preferably a combination in which the refractive index difference between the two types of materials constituting the DBR layer is increased.

The lower DBR layer 2 is preferably formed by alternately laminating 10 to 50 pairs of layers having two different refractive indices. The reason is that in the case of 10 pairs or less, since the reflectance is too low, it does not help to increase the output, and even 50 pairs or more The value of the reflectance further increases is small.

The two types of layers constituting the lower refractive index of the lower DBR layer 2 are selected from two types of compositions (Al _Xh Ga _1-Xh ) _Y3 In _1-Y3 P (0<Xh≦1, Y3=0.5), (Al _X1 Ga _1-X1 ) _Y3 In _1-Y3 P; 0≦X1<1, Y3=0.5), and the composition difference of ΔX=xh-xl of the two is greater than or equal to 0.5, Or a combination of GaInP and AlInP, or a pair of two different types of Al _x1 Ga _1-x1 As (0.1≦x1≦1), Al _xh Ga _1-xh As (0.1≦xh≦1), and both The composition difference ΔX=xh-xl is any combination of 0.5 or more, and it is preferable to obtain high reflectance because of good efficiency.

Since the composition of AlGaInP having different compositions does not contain As which is prone to crystal defects, it is preferable that GaInP and AlInP are those in which the maximum refractive index difference can be obtained, so that the number of reflective layers can be reduced, and the composition conversion is simple, so good. Further, AlGaAs has an advantage that it is easy to obtain a large refractive index difference.

The upper DBR layer 4 may have the same layer structure as the lower DBR layer 2. However, since the light is transmitted through the upper DBR layer 4 and is emitted, the ruthenium has a lower reflectance than the lower DBR layer 2. Specifically, in the case where the same material as the lower DBR layer 2 is included, it is preferable to alternately laminate the layers 3 to 10 with two layers having different refractive indices in such a manner that the number of layers is smaller than that of the lower DBR layer 2. The reason is that in the case of 2 pairs or less, since the reflectance is too low, the output is not helped, and when it is 11 pairs or more, the amount of light penetrating the upper DBR layer 4 is greatly reduced.

The light-emitting diode of the present invention is characterized in that the active layer 3 is coated with a low-reflectivity upper DBR layer 4 and a high-reflectivity lower DBR layer 2 such that the active layer 3 emits light in the upper DBR layer 4 and the lower DBR. Resonance between layers 2 On the other hand, the abdomen of the standing wave is formed in the light-emitting layer, so that the light-emitting diode having higher directivity than the conventional light-emitting diode is formed without causing the laser to oscillate.

As shown in FIG. 4, the active layer 3 is formed by sequentially laminating the lower cladding layer 11, the lower guiding layer 12, the light-emitting layer 13, the upper guiding layer 14, and the upper cladding layer 15. In other words, the active layer 3 is formed to include a lower portion and a lower side opposite to the lower side and the upper side of the light-emitting layer 13 for the carrier (carrier) and the light-emitting "light-in" light-emitting layer 13 that will cause radiation recombination. The so-called double heterogeneous (DH) structure of the cladding layer 11, the lower guiding layer 12, the upper guiding layer 14, and the upper cladding layer 15 is preferable in obtaining high-intensity light emission.

As shown in FIG. 4, the light-emitting layer 13 controls the light-emitting wavelength of the light-emitting diode (LED), and a quantum well structure can be constructed. That is, the light-emitting layer 13 can be formed in a multilayer structure (layered structure) having the well layer 17 and the barrier layer 18 of the barrier layer (also referred to as a barrier layer) 18 at both ends.

The layer thickness of the light-emitting layer 13 is preferably in the range of 0.02 to 2 μm. The conductivity type of the light-emitting layer 13 is not particularly limited, and undoped, p-type, and n-type may be selected. In order to improve the luminous efficiency, the carrier concentration of undoped or less than 3 × 10 ¹⁷ cm ^-3 which is excellent in crystallinity is the best.

As the material of the well layer 17, a well-known well layer material can be used. For example, AlGaAs, InGaAs, or AlGaInP can be used.

The layer thickness of the well layer 17 is preferably in the range of 3 to 30 nm. More preferably, it is in the range of 3 to 10 nm.

As the material of the barrier layer 18, a material for selecting a material suitable for the well layer 17 is preferable. In order to prevent absorption in the barrier layer 18 to improve luminous efficiency It is preferable to set the band gap to be larger than the well layer 17.

For example, in the case where AlGaAs or InGaAs is used as the material of the well layer 17, as the material of the barrier layer 18, AlGaAs or AlGaInP is preferable. When AlGaInP is used as the material of the barrier layer 18, since As does not easily cause defects, the crystallinity is high and contributes to high output.

In the case where (Al _X1 Ga _1-X1 ) _Y1 In _1-Y1 P (0≦X1≦1, 0<Y1≦1) is used as the material of the well layer 17, as the material of the barrier layer 18, Al may be used. High (Al _X4 Ga _1-X4 ) _Y1 In _1-Y1 P (0≦X4≦1,0<Y1≦1, X1<X4) or band gap energy ratio well layer (Al _X1 Ga _1-X1 ) _Y1 In _1-Y1 P (0≦X1≦1, 0<Y1≦1) Large AlGaAs.

The layer thickness of the barrier layer 18 is preferably equal to or greater than the layer thickness of the well layer 17. By increasing the thickness of the layer thickness in the channel effect, the expansion between the well layers due to the channel effect is suppressed, the effect of the carrier being locked in is increased, and the probability of recombination of electrons and holes is increased. Seeking an increase in luminous output.

In the multilayer structure of the well layer 17 and the barrier layer 18, the number of pairs of the well layer 17 and the barrier layer 18 which are alternately laminated is not particularly limited, but is preferably 2 pairs or more and 40 pairs or less. That is, the active layer 11 is preferably a well layer 17 containing 2 to 40 layers. Here, the luminous efficiency of the active layer 11 is a suitable range, and it is preferable that the well layer 17 is five or more layers. On the other hand, since the well layer 17 and the barrier layer 18 have a low carrier concentration, a plurality of pairs are caused to cause an increase in the forward voltage (V _F ). For this reason, it is preferably 40 or less, and more preferably 20 or less.

The lower guiding layer 12 and the upper guiding layer 14 are provided on the lower surface and the upper surface of the light-emitting layer 13 as shown in FIG. 4, respectively. Specifically, a lower guiding layer 12 is disposed under the luminescent layer 13, and an upper guiding layer is disposed on the upper surface of the luminescent layer 13. 14.

As the material of the lower guiding layer 12 and the upper guiding layer 14, a well-known compound semiconductor material can be used, and a material suitable for selecting a material suitable for the light-emitting layer 13 is preferable. For example, AlGaAs or AlGaInP can be used.

For example, in the case where the material of the well layer 17 is AlGaAs or InGaAs, and the material of the barrier layer 18 is AlGaAs or AlGaInP, the material of the lower guiding layer 12 and the upper guiding layer 14 is preferably AlGaAs or AlGaInP. The material of the lower guiding layer 12 and the upper guiding layer 14 is a case where AlGaInP is used, and since As is likely to cause defects, the crystallinity is high and contributes to high output.

In the case where (Al _X1 Ga _1-X1 ) _Y1 In _1-Y1 P (0≦X1≦1, 0<Y1≦1) is used as the material of the well layer 17, higher Al may be used as the material of the guiding layer 14. Composition (Al _X4 Ga _1-X4 ) _Y1 In _1-Y1 P(0≦X4≦1,0<Y1≦1, X1<X4) or band gap energy ratio well layer (Al _X1 Ga _1-X1 ) _Y1 In _1-Y1 P (0≦X1≦1, 0<Y1≦1) is also large AlGaAs.

The lower guiding layer 12 and the upper guiding layer 14 are provided to reduce the transmission of the lower cladding layer 11 and the upper cladding layer 15 and the active layer 11 and the defects, respectively. For this reason, the layer thickness of the lower guiding layer 12 and the upper guiding layer 14 is preferably 10 nm or more, more preferably 20 nm to 100 nm.

The conduction type of the lower guiding layer 12 and the upper guiding layer 14 is not particularly limited, and undoped, p-type, and n-type may be selected. In order to improve the luminous efficiency, the carrier concentration of undoped or less than 3 × 10 ¹⁷ cm ^-3 which is excellent in crystallinity is the best.

As shown in FIG. 4, the lower cladding layer 11 and the upper cladding layer 15 are provided on the lower surface of the lower guiding layer 12 and the upper surface of the upper guiding layer 14, respectively.

Regarding the materials of the lower cladding layer 11 and the upper cladding layer 15, it can be used. A well-known compound semiconductor material is preferable in order to select a material suitable for the material of the light-emitting layer 13. For example, AlGaAs or AlGaInP can be used.

For example, in the case where the material of the well layer 17 is AlGaAs or InGaAs, and the material of the barrier layer 18 is AlGaAs or AlGaInP, the material of the lower cladding layer 11 and the upper cladding layer 15 is preferably AlGaAs or AlGaInP. . The material of the lower cladding layer 11 and the upper cladding layer 15 is a case where AlGaInP is used, and since As is likely to cause defects, the crystallinity is high and contributes to high output.

In the case where (Al _X1 Ga _1-X1 ) _Y1 In _1-Y1 P (0≦X1≦1, 0<Y1≦1) is used as the material of the well layer 17, as the material of the cladding layer 15, Al may be used. Higher (Al _X4 Ga _1-X4 ) _Y1 In _1-Y1 P (0≦X4≦1,0<Y1≦1, X1<X4) or band gap energy ratio well layer (Al _X1 Ga _1-X1 ) _Y1 In _1-Y1 P (0≦X1≦1, 0<Y1≦1) is also large AlGaAs.

The lower cladding layer 11 and the upper cladding layer 15 have different polarities.

Further, the carrier concentration and thickness of the lower cladding layer 11 and the upper cladding layer 15 can be appropriately determined, and the conditions can be optimized so that the luminous efficiency of the active layer 11 can be improved. In addition, the lower and upper cladding layers may not be provided.

Further, by controlling the composition of the lower cladding layer 11 and the upper cladding layer 15, the warpage of the compound semiconductor layer 20 can be lowered.

The contact layer 5 is provided to reduce the contact resistance with the electrodes. The material of the contact layer 5 is preferably a material having a band gap larger than that of the light-emitting layer 13. Further, in order to lower the contact resistance with the electrode, the lower limit of the carrier concentration of the contact layer 5 is preferably 5 × 10 ¹⁷ cm ^-3 or more, more preferably 1 × 10 ¹⁸ cm ^-3 or more. The upper limit of the carrier concentration is preferably 2 × 10 ¹⁹ cm ^-3 or less which is liable to cause a decrease in crystallinity. The thickness of the contact layer 5 is preferably 0.05 μm or more. The upper limit of the thickness of the contact layer 5 is not particularly limited, but it is preferably 10 μm or less in order to set the cost of epitaxial growth to an appropriate range.

The light-emitting diode of the present invention can be incorporated in a lamp, a backlight, a mobile phone, a display, various panels, an electronic device such as a computer, a game machine, or an illumination, or a mechanical device such as an automobile in which the electronic device is assembled.

[Light Emitting Diode (Second Embodiment)]

Fig. 5 is a schematic cross-sectional view showing another example of a resonator-type light-emitting diode to which a light-emitting diode of the present invention is applied.

In the first embodiment, a protective film is formed under the light-emitting hole, and the top surface of the mesa-type structure portion is configured to take out light from the light-emitting hole through the protective film. In the second embodiment, the light is emitted. There is no protective film under the hole, and the light is directly taken out from the light exit hole 9b without passing through the protective film.

In other words, the resonator-type light-emitting diode 200 of the second embodiment is characterized in that the protective film 28 covers at least a portion 28c of the flat portion 6, the inclined side surface 7a of the floor-type structure portion 7, and the floor-type structure portion 7. The peripheral edge region 7ba of the top surface 7b has an energization window 28b which exposes the surface of the contact layer 5 on the inner side of the peripheral edge region 7ba. The electrode film 29 covers at least a portion of the flat portion 6 via the protective film 28, and is separated by a protective film. The inclined side surface 7a covering the mesa structure portion 7 and the peripheral edge portion 7ba of the top surface 7b of the mesa structure portion 7 are covered with the protective film 28, and the upper surface of the mesa structure portion 7 is covered from the energization window. A portion of the surface of the exposed contact layer 5 of 28b exposes the light exit hole 29b of the other portion 5a of the surface of the contact layer 5.

As shown in Fig. 5, the protective film 28 of the second embodiment includes a portion 28a that covers the inclined side surface 7a of the mesa structure portion 7, and a portion 28c (which also includes a flat surface that covers the opposite side with the mesa structure portion 7 interposed therebetween. a portion of the portion 28cc) covering at least a portion of the flat portion 6; and a portion 28ba covering the peripheral edge portion 7ba of the top surface 7b of the mesa-type structure portion 7; and having a contact layer 5 exposed on the inner side of the peripheral portion 7ba in plan view The power-on window 28b of the surface. That is, the energization window 28b is exposed on the top surface 7b of the mesa-type structure portion 7 except for a portion of the surface of the contact layer 5 that is below the peripheral region 7ba. Although the electrode film (outer surface electrode film) 9 is formed on the protective film 8, a portion where no current flows between the electrode film 9 and the back surface electrode 10 forms the protective film 8.

Further, as shown in Fig. 5, the electrode film (outer surface electrode film) 29 of the second embodiment includes a portion 29a covering a portion 28a of the protective film 28 for covering the inclined side surface 7a, and a portion 29c covering a portion 28c of the protective film 28 for covering at least a portion of the flat portion 6; a portion 29ba covering a portion of the protective film 28 covering the peripheral portion 7ba of the top surface 7b of the mesa-type structure portion 7; And a portion 29bb that covers the contact layer 5 so as to form an opening of the light-emitting hole 29b over the portion of the protective film 28 of the top surface 7b of the mesa-type structure portion 7 by the reference numeral 28ba.

In the electrode film (outer surface electrode film) 29 of the second embodiment, the portion 29bb serves both the first function and the second function described above.

[Light Emitting Diode (3rd Embodiment)]

The light-emitting diode according to the third embodiment of the present invention is different from the light-emitting diode of the first embodiment in that the upper DBR reflective layer is replaced with a current diffusion layer instead.

Fig. 6 is a schematic cross-sectional view showing an example of the light-emitting diode 300 according to the third embodiment.

As shown in FIG. 6, the light-emitting diode 300 is configured to include a current diffusion layer 40 on the active layer 3.

In the present embodiment, as the material of the current diffusion layer 40, for example, AlGaAs or the like can be used.

The thickness of the current diffusion layer 40 is preferably 0.1 μm or more and 10 μm or less. The reason is that the current spreading effect is insufficient at less than 0.1 μm, and when it exceeds 10 μm, the cost associated with epitaxial growth is too large in terms of effect.

[Light Emitting Diode (Fourth Embodiment)]

The light-emitting diode according to the fourth embodiment of the present invention is provided with a reflective layer containing a metal instead of the lower DBR reflective layer as compared with the light-emitting diode of the first embodiment. The difference is different between a metal substrate as a substrate or a conductive substrate including a substrate such as tantalum or niobium.

Further, in the present embodiment, it is also possible to construct the upper cladding layer and also have the current spreading function of the current diffusion layer 40 in the third embodiment.

Fig. 7 is a schematic cross-sectional view showing an example of the light-emitting diode 400 of the fourth embodiment.

As shown in FIG. 7, the light-emitting diode 400 is provided with a light-emitting diode including a metal reflective layer 52, a GaP layer 53, an active layer 54, and a contact layer 5 on the conductive substrate 51.

Moreover, the back surface electrode 56 is provided in the lower surface side of the electrically-conductive board|substrate 51.

Regarding the reflective layer 52 containing a metal, having a wavelength relative to the light emission A metal having a reflectance of 90% or more is preferable, for example, composed of gold (Au), silver (Ag), copper (Cu), aluminum (Al), or an alloy thereof or an AgPdCu alloy (APC).

The active layer 54 includes the upper cladding layer 63a, the light-emitting layer 64, and the lower cladding layer 63b. However, the upper cladding layer has the current spreading function of the current diffusion layer 40 in the third embodiment. The thickness of the upper cladding layer 63a is preferably 0.1 μm or more and 10 μm or less. The reason is that the current spreading effect is insufficient at less than 0.1 μm, and when it exceeds 10 μm, the cost associated with epitaxial growth is too large in terms of effect.

The GaP layer 53 can electrically connect both the reflective layer 52 containing a metal and the active layer 54 containing a compound semiconductor with a low contact resistance. As long as it has such a function, it is not limited to GaP, and (Al _x Ga _(1-x) ) _(1-y) In _y P, (Al _x Ga _(1-x) ) _{(1-y) can be used.} In _y As and so on.

The thickness of the GaP layer 53 is preferably 1 μm or more and 5 μm or less. The reason is that, in the case of less than 1 μm, the light-emitting output is lowered by the stress at the joint interface, and when it exceeds 5 μm, the cost associated with epitaxial growth is too large in terms of effect.

As the material of the conductive substrate 51, a metal, Si, Ge, GaP, GaInP, SiC, or the like can be used. The Si substrate and the Ge substrate have an advantage that they are inexpensive and excellent in moisture resistance. GaP, GaInP, and SiC substrates have an advantage that the thermal expansion coefficient is close to the light-emitting portion, and the moisture resistance is excellent and the thermal conductivity is good. From the viewpoints of cost surface, mechanical strength, and heat dissipation, the metal substrate is excellent, and as described later, a structure in which a plurality of metal layers (metal plates) are laminated is provided, and the entire metal substrate can be adjusted in thermal expansion coefficient. The advantages.

In the case where the conductive substrate 51 is a metal substrate, a structure in which a plurality of metal layers (metal plates) are laminated may be used.

In the case of forming a structure in which a plurality of metal layers (metal plates) are laminated, it is preferable to alternately laminate two types of metal layers, in particular, metal layers of the two types (for example, these are referred to as first metals). The number of layers of the layer and the second metal layer is preferably an odd number in total.

For example, in the case of forming a metal substrate in which the second metal layer is formed of the first metal layer, the second metal layer is made of a thermal expansion coefficient higher than that of the compound semiconductor layer from the viewpoint of warpage or cracking of the metal substrate. In the case of a small material, the first metal layer is preferably a material having a larger thermal expansion coefficient than the compound semiconductor layer 3. The reason is that since the thermal expansion coefficient of the entire metal substrate is close to the thermal expansion coefficient of the compound semiconductor layer, warpage or cracking of the metal substrate can be suppressed when the compound semiconductor layer and the metal substrate are bonded, and the manufacturing yield of the light-emitting diode can be improved. Upgrade. Similarly, when the second metal layer is made of a material having a thermal expansion coefficient larger than that of the compound semiconductor layer 2, it is preferable that the first metal layer contains a material having a thermal expansion coefficient smaller than that of the compound semiconductor layer 2. The reason is that since the thermal expansion coefficient of the entire metal substrate is close to the thermal expansion coefficient of the compound semiconductor layer, warpage or cracking of the metal substrate can be suppressed when the compound semiconductor layer and the metal substrate are bonded, and the manufacturing yield of the light-emitting diode can be improved.

From the above viewpoints, the two types of metal layers may be the first metal layer or the second metal layer.

For the two types of metal layers, for example, silver (thermal expansion coefficient = 18.9 ppm/K), copper (thermal expansion coefficient = 16.5 ppm/K), and gold (hot expansion) can be used. Expansion coefficient = 14.2 ppm/K), aluminum (coefficient of thermal expansion = 23.1 ppm/K), nickel (coefficient of thermal expansion = 13.4 ppm/K), and metal layers of any of these alloys, and containing molybdenum (coefficient of thermal expansion = 5.1 ppm / K), tungsten (coefficient of thermal expansion = 4.3 ppm/K), chromium (coefficient of thermal expansion = 4.9 ppm/K), and combinations of metal layers of any of these alloys.

A suitable example of a metal substrate including Cu/Mo/Cu is described. From the above point of view, the same effect can be obtained even with a three-layer metal substrate containing Mo/Cu/Mo, but since the three-layer metal substrate including Cu/Mo/Cu is made of a Cu-clamp mechanical strength which is easy to process Since the high Mo is formed, it has an advantage that processing such as cutting is easier than a metal substrate including three layers of Mo/Cu/Mo.

The thermal expansion coefficient of the entire metal substrate is, for example, a metal substrate of three layers including Cu (30 μm) / Mo (25 μm) / Cu (30 μm) is 6.1 ppm / K, and contains Mo (25 μm) / Cu (70 μm) / Mo ( The metal substrate of the three layers of 25 μm) was 5.7 ppm/K.

Further, from the viewpoint of heat release, it is preferable that the metal layer constituting the metal substrate contains a material having a high thermal conductivity. The reason is that the heat dissipation property of the metal substrate can be improved, the light-emitting diode can emit light with high luminance, and the life of the light-emitting diode can be prolonged.

For example, use of silver (thermal conductivity = 420 W/m. K), copper (thermal conductivity = 398 W/m. K), gold (thermal conductivity = 320 W/m. K), aluminum (thermal conductivity = 236 W/m. K) ), molybdenum (thermal conductivity = 138 W/m. K), tungsten (thermal conductivity = 174 W/m. K), and the like are preferable.

More preferably, the coefficient of thermal expansion of the metal layer including the same is substantially the same as the coefficient of thermal expansion of the compound semiconductor layer. Especially, The material of the metal layer is preferably a material having a thermal expansion coefficient within ±1.5 ppm/K which is a thermal expansion coefficient of the compound semiconductor layer. Thereby, stress caused by heat toward the light-emitting portion when the metal substrate and the compound semiconductor layer are bonded can be reduced, and cracking of the metal substrate due to heat when the metal substrate and the compound semiconductor layer are connected can be suppressed, and the light-emitting diode can be made The manufacturing yield of the body is improved.

The thermal conductivity of the entire metal substrate is, for example, a three-layer metal substrate containing Cu (30 μm) / Mo (25 μm) / Cu (30 μm) is 250 W / m. K, and the 3-layer metal substrate containing Mo (25 μm) / Cu (70 μm) / Mo (25 μm) is 220 W / m. K.

Further, it is preferable that the upper surface and the lower surface of the metal substrate are covered with a metal protective film. Furthermore, the side surface is also preferably covered with a metal protective film.

The material of the metal protective film is preferably a metal containing at least one of chromium, nickel, chemically stable platinum, or gold which is excellent in adhesion.

The metal protective film is most preferably a layer comprising a combination of nickel having excellent adhesion and excellent gold resistance.

The thickness of the metal protective film is not particularly limited, and from the viewpoint of resistance to the etching liquid and cost balance, 0.2 to 5 μm, preferably 0.5 to 3 μm is a suitable range. In the case of high-value gold, the thickness is preferably 2 μm or less.

[Manufacturing Method of Light Emitting Diode (First Embodiment)]

Next, an embodiment of a method for producing a light-emitting diode of the present invention will be described with a method of manufacturing a light-emitting diode (resonator type light-emitting diode) according to the first embodiment.

Fig. 8 is a schematic cross-sectional view showing a step of a method of manufacturing a light-emitting diode. Further, Fig. 9 is a cross-sectional schematic view showing a step subsequent to Fig. 8.

(Step of forming a compound semiconductor layer)

First, the compound semiconductor layer 20 shown in Fig. 8 is produced.

The compound semiconductor layer 20 is formed by sequentially laminating the lower DBR layer 2, the active layer 3, the upper DBR layer 4, and the contact layer 5 on the substrate 1.

A buffer may also be provided between the substrate 1 and the lower DBR layer 2. The buffer layer is provided to reduce the transfer of defects of the constituent layers of the substrate 1 and the active layer 3. For this reason, if the quality of the substrate or the epitaxial growth conditions are selected, the buffer layer is not necessarily required. Further, the material of the buffer layer is preferably the same as that of the substrate for epitaxial growth.

In order to reduce the transmission of defects, the buffer layer may also use a multilayer film composed of different materials of the substrate. The thickness of the buffer layer is preferably 0.1 μm or more, more preferably 0.2 μm or more.

In the present embodiment, a well-known growth method such as molecular beam epitaxy (MBE) or reduced-pressure organic metal chemical vapor deposition (MOCVD) can be applied. Among them, the MOCVD method excellent in mass productivity is most preferable. Specifically, the substrate 1 for epitaxial growth of the compound semiconductor layer is preferably subjected to a pretreatment such as a cleaning step or a heat treatment before growth to remove surface contamination or a natural oxide film. Each of the layers constituting the compound semiconductor layer is formed by mounting a substrate 1 having a diameter of 50 to 150 mm in an MOCVD apparatus and epitaxial growth. Further, as for the MOCVD apparatus, a commercially available large-scale device such as a self-conversion or a high-speed rotary type can be applied.

When the respective layers of the compound semiconductor layer 20 are epitaxially grown, for the raw material of the group III constituent element, for example, trimethylaluminum ((CH ₃ ) ₃ Al) or trimethylgallium ((CH ₃ ) ₃ ) can be used. Ga) and trimethylindium ((CH ₃ ) ₃ In). Further, as the doping raw material of Mg, for example, dicyclopentadienyl magnesium (bis-(C ₅ H ₅ ) ₂ Mg) or the like can be used. Further, as the doping raw material of Si, for example, dioxane (Si ₂ H ₆ ) or the like can be used. Further, as a raw material of the group V constituent element, phosphine (PH ₃ ), arsine (AsH ₃ ), or the like can be used.

Further, the carrier concentration, layer thickness, and temperature conditions of each layer can be appropriately selected.

The compound semiconductor layer thus produced can obtain a good surface state with few crystal defects despite the active layer 3. Further, the compound semiconductor layer 20 may be subjected to surface processing such as polishing in accordance with the element structure.

(Step of forming the back electrode)

Next, as shown in FIG. 8, the back surface electrode 10 is formed on the back surface of the substrate 1.

Specifically, for example, when the substrate is an n-type substrate, the back surface electrode 10 of the n-type ohmic electrode is formed by, for example, sequentially depositing Au or AuGe by a vapor deposition method.

(Formation steps of the mesa structure part)

Next, in order to form the mesa structure portion (excluding the protective film and the electrode film), the compound semiconductor layer of the portion other than the mesa structure portion, that is, at least a part of the contact layer and the upper DBR layer and the active layer, or the contact layer and the upper portion At least a portion of the DBR layer and the active layer and the lower DBR layer are wet etched.

Specifically, first, as shown in FIG. 9, a photoresist is deposited on the uppermost layer of the compound semiconductor layer, that is, on the contact layer, and the photolithography is performed on the mesa type. A photoresist pattern 23 having an opening 23a is formed outside the structural portion.

It is preferable that the mesa structure portion in the resist pattern is formed to have a predetermined portion size, and is formed to be slightly larger than the top surface of the "floor type structure portion" by 10 μm.

Next, for example, using a phosphoric acid/hydrogen peroxide water mixture, etching and removing portions of the contact layer and the upper DBR layer and the active layer other than the mesa-type structure portion, or the contact layer and the upper DBR layer and the active layer and the lower portion At least a portion of the DBR layer.

For the phosphoric acid/hydrogen peroxide water mixture, for example, a phosphoric acid/hydrogen peroxide water mixture of H ₂ PO ₄ :H ₂ O ₂ :H ₂ O=1~3:4-6:8-10 can be used. The above etching removal is performed by a wet etching time of 30 to 120 seconds.

After that, the photoresist is removed.

The shape of the mesa structure portion in plan view is determined by the shape of the opening 23a of the photoresist pattern 23. The photoresist pattern 23 is formed with an opening 23a having a shape corresponding to a desired plan view shape.

Further, the depth of etching, that is, which layer of the compound semiconductor layer is etched to remove it, is determined by the type of etching liquid and the etching time.

Figure 10 shows an etchant using H ₂ PO ₄ :H ₂ O ₂ :H ₂ O=2:5:9 (100:250:450), 56% (H ₂ O), liquid temperature 30 ° C ~ 34 ° C, The relationship between the depth and the width of the compound semiconductor layer shown in Example 1 to be described later in the case of wet etching with respect to the etching time. Table 1 shows the conditions and results by numerical values.

As can be seen from FIG. 10 and Table 1, the etching depth (corresponding to "h" in FIG. 1) is approximately proportional to the etching time (sec), and the etching rate increases as the etching time increases. That is, as shown in FIG. 3, the deeper the formation (the more downward in the drawing), the larger the increase rate of the horizontal cross-sectional area (or width or diameter) of the mesa-type structural portion. This etched shape is different from the etched shape formed by dry etching. Therefore, from the shape of the inclined slope of the mesa structure portion, it can be determined that the mesa structure portion is formed by dry etching or formed by wet etching.

(Step of forming a protective film)

Next, the material of the protective film 8 is formed in a comprehensive manner. Specifically, for example, SiO _{2 is} formed into a film by sputtering.

(Step of removing the protective film from the portion of the scribe line and the contact layer)

Next, the photoresist is entirely deposited, and a portion corresponding to the energization window 8b on the contact layer and a portion corresponding to the dicing street are formed by photolithography as an open photoresist pattern.

Next, for example, the protective film 8 is formed by buffering hydrofluoric acid and removing the material corresponding to the energization window 8b of the top surface of the mesa structure portion and the portion of the protective film 8 corresponding to the dicing street by wet etching. .

Fig. 11 shows a plan view of the vicinity of the energization window 8b of the protective film 8.

After that, the photoresist is removed.

(Step of forming the outer surface electrode film)

Next, the outer surface electrode film 9 is formed. That is, the surface electrode film 9 having the light exit hole 9b is formed on the protective film 8 and the contact layer 5 exposed from the current supply window 8b of the protective film 8.

Specifically, the photoresist is entirely deposited, and a non-electrode is formed by photolithography to include a portion corresponding to the light exit hole 9b and a cut portion (cutting path) between the plurality of light emitting diodes on the wafer substrate. A portion other than the portion of the film serves as an open photoresist pattern. Next, the electrode film material is evaporated. In the case where the electrode film material cannot be sufficiently vapor-deposited on the inclined side surface of the mesa structure portion by the vapor deposition, in order to further vapor-deposit the electrode film material on the inclined side surface of the mesa structure portion, a planetary type in which the vapor deposition metal is easily wound is used. The vapor deposition device performs vapor deposition.

After that, the photoresist is removed.

The shape of the light exit hole 9b is determined by the shape of the opening of the photoresist pattern (not shown). A photoresist pattern having an opening shape corresponding to the shape of the desired light exit hole 9b is formed.

(single step)

Next, the light-emitting diodes on the wafer substrate are individually formed.

Specifically, for example, the dicing portion is cut by a dicing saw or a laser and sliced by the illuminating diode on the wafer substrate.

[Manufacturing Method of Light Emitting Diode (Second Embodiment)]

The light-emitting diode of the present invention (second embodiment) and the light-emitting diode (first embodiment) differ only in the arrangement of the protective film and the electrode, and the manufacturing method thereof and the light-emitting diode (first embodiment) The manufacturing method is performed in the same manner.

[Method of Manufacturing Light Emitting Diode (3rd Embodiment)]

The manufacturing method of the light-emitting diode of the present invention (the third embodiment) differs from the method of manufacturing the light-emitting diode (first embodiment) in that a lower layer is laminated on the substrate 1 in the step of forming the compound semiconductor layer. After the DBR layer 2 and the active layer 3, the current diffusion layer 40 is laminated on the active layer 3, and the rest can be carried out in the same manner as in the case of the light-emitting diode (first embodiment).

[Manufacturing Method of Light Emitting Diode (Fourth Embodiment)]

Next, a method of manufacturing the light-emitting diode of the present invention (fourth embodiment) will be described.

The case of the substrate 51 is described with respect to the case of using a metal substrate.

<Manufacturing procedure of metal substrate>

12(a) to 12(c) are schematic cross-sectional views showing a part of a metal substrate for explaining a manufacturing process of a metal substrate.

The metal substrate 51 is a first metal layer (first metal plate) 51b having a thermal expansion coefficient larger than that of the active layer, and a second metal layer having a thermal expansion coefficient smaller than that of the active layer (second The metal plate 51a is formed by hot pressing.

Specifically, first, two substantially flat first metal layers 51b and one substantially flat second metal layer 51a are prepared. For example, Cu having a thickness of 10 μm is used as the first metal layer 51b and Mo having a thickness of 75 μm as the second metal layer 51a.

Next, as shown in FIG. 12(a), the second metal layer 51a is inserted between the two first metal layers 51b, and these are placed one on top of the other.

Secondly, the overlapping metal layers are placed in a prescribed pressurized package. The first metal layer 51b and the second metal layer 51a are applied with a load in the direction of the arrow at a high temperature. Thereby, as shown in FIG. 12(b), the first metal layer 51b is Cu, and the second metal layer 51a is Mo, and a three-layer metal substrate containing Cu (10 μm) / Mo (75 μm) / Cu (10 μm) is formed. 1.

The metal substrate 51 has, for example, a thermal expansion coefficient of 5.7 ppm/K and a thermal conductivity of 220 W/m. K.

Next, as shown in FIG. 12(c), a metal protective film 51c covering the entire surface, that is, the upper surface, the lower surface, and the side surface of the metal substrate 1, is formed. At this time, since the metal substrate has not been cut into individual light-emitting diodes, the side surface covered by the metal protective film refers to the outer peripheral side surface of the metal substrate (sheet). Therefore, in the case where the side surface of the metal substrate 51 of each of the light-emitting diodes to be covered is covered with the metal protective film 51c, the step of covering the side surface with the metal protective film is additionally performed.

Fig. 12 (c) shows a part of a portion on the outer peripheral end side of the non-metal substrate (sheet), and the metal protective film on the outer peripheral side is not shown in the drawing.

Although a known film formation method can be employed for the metal protective film, the plating method capable of forming a film on the entire surface including the side surface is optimal.

For example, in the electroless plating method, after plating nickel, gold is plated to cover the metal substrate 51 covering the upper surface, the side surface, and the lower surface of the metal substrate with a nickel film and a gold film (metal protective film).

The plating material is not particularly limited, and a known material such as copper, silver, nickel, chromium, platinum, or gold can be used. However, it is preferable to use a combination of nickel having excellent adhesion and excellent gold resistance.

The plating method can use well-known techniques and medicines. The electroless plating method which does not require an electrode is preferable because it is simple.

<Step of Forming Compound Semiconductor Layer>

First, as shown in FIG. 13, a plurality of epitaxial layers are grown on one surface 61a of a semiconductor substrate (growth substrate) 61 to form an epitaxial layered body 80 including the active layer 54.

The semiconductor substrate 61 is a substrate for forming an epitaxial layered body 80, and is, for example, an Si-doped n-type GaAs single crystal substrate in which one surface 61a is a surface inclined by 15° from the (100) plane. In the case where the epitaxial layered body 80 is an AlGaInP layer or an AlGaAs layer, a gallium arsenide (GaAs) single crystal substrate can be used as the substrate on which the epitaxial layered body 80 is formed.

Regarding the method of forming the active layer 54, a Metal Organic Chemical Vapor Deposition (MOCVD) method, a Molecular Beam Epitaxic (MBE) method, or a Liquid Phase Epitaxicy (LPE) method can be used. ) Law and so on.

In the present embodiment, trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga), and trimethylindium ((CH ₃ ) ₃ In) are used as the III group. The decompression MOCVD method of the raw materials of the elements causes the layers to be epitaxially grown.

Further, a doping raw material of Mg is made of dicyclopentadienyl magnesium ((C ₅ H ₅ ) ₂ Mg). Further, dioxane (Si ₂ H ₆ ) is used as a doping material for Si. Further, as a raw material of the group V constituent element, phosphine (PH ₃ ) or arsine (AsH ₃ ) is used.

Further, the p-type GaP layer 53 is grown at, for example, 750 ° C, and the other epitaxial growth layer is grown at, for example, 730 ° C.

Specifically, first, a buffer layer 62a containing n-type GaAs doped with Si is formed on one surface 61a of the growth substrate 61. As the buffer layer 62a, for example, n-type GaAs doped with Si is used, the carrier concentration is 2 × 10 ¹⁸ cm ^{-3 ,} and the layer thickness is set to 0.2 μm.

Next, in the present embodiment, the etching stop layer 62b is formed on the buffer layer 62a.

The etch stop layer 62b is a layer for preventing etching to the cladding layer and the light-emitting layer when the semiconductor substrate is removed by etching, for example, (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P containing Si doping, and the layer thickness is set. It is 0.5 μm.

Next, a contact layer 5 containing, for example, Si-doped n-type Al _x Ga _1-x As (0.1 ≦ X ≦ 0.3) is formed on the etch stop layer 62b.

Next, an upper cladding layer 63a containing, for example, an n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P doped with Si is formed on the contact layer 5.

Next, for example, three pairs of the well layers including Al _0.17 Ga _0.83 As/Al _0.3 Ga _0.7 As/the light-emitting layer 64 having a laminated structure including a barrier layer are formed on the upper cladding layer 63a.

Next, a lower cladding layer 63b containing, for example, Mg-doped p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is formed on the light-emitting layer 64.

Next, a Mg-doped p-type GaP layer 53 is formed on the lower cladding layer 63b.

Before attaching to a substrate such as a metal substrate to be described later, the surface to be trimmed (that is, mirror-finished. For example, the surface roughness is 0.2 nm or less), for example, it is preferably about 1 μm.

Further, a guiding layer may be provided between the cladding layer and the light-emitting layer.

<Step of forming a reflective layer>

Next, as shown in FIG. 13, a reflective layer 52 containing, for example, Au is formed on the p-type GaP layer 53.

<Joining step of metal substrate>

Before the metal substrate 51 is bonded to the reflective layer 52, the reflective layer can also be used. A barrier layer (not shown) and/or a bonding layer (not shown) are formed on 52.

The barrier layer can suppress the diffusion of the metal contained in the metal substrate and react with the reflective layer 52.

As the material of the barrier layer, nickel, titanium, platinum, chromium, ruthenium, tungsten, molybdenum or the like can be used. The barrier layer enhances the barrier properties by a combination of two or more types of metals, such as a combination of platinum and titanium.

Further, even if the barrier layer is not provided, the bonding layer can have the same function as the barrier layer by adding a material such as the bonding layer.

The bonding layer is used to bond the compound semiconductor layer 10 including the active layer 54 to the layer of the metal substrate 1 with good adhesion.

As the material of the bonding layer, an Au-based eutectic metal having a chemical stability and a low melting point is used. Examples of the Au-based eutectic metal include a eutectic composition of an alloy such as AuGe, AuSn, AuSi, or AuIn.

Next, as shown in FIG. 14, the semiconductor substrate 61 on which the epitaxial laminate 80 or the reflective layer 52 is formed, and the metal substrate 51 formed in the manufacturing process of the metal substrate are carried into the decompression device, and the bonding surface of the bonding layer The joint surface 51A of the metal substrate 51 is disposed to overlap each other.

Next, after the exhaust gas in the decompression device reaches 3 × 10 ^-5 Pa, a load of 500 kg is applied to bond the bonding surface of the bonding layer and the metal in a state where the superposed semiconductor substrate 61 and the metal substrate 51 are heated to 400 ° C. The joint structure 90 is formed on the joint surface 51A of the substrate 51.

<Semiconductor substrate and buffer layer removal step>

Next, as shown in FIG. 15, the semiconductor substrate 61 and the buffer layer 62a are selectively removed from the bonded structure 90 by an ammonia-based etching liquid.

At this time, the metal substrate of the present invention is covered with a metal protective film, The resistance to the etching liquid is high, thereby preventing deterioration of the quality of the metal substrate.

<etch stop layer removal step>

Next, as shown in FIG. 15, the etching stop layer 62b is selectively removed by a hydrochloric acid-based etching liquid.

The metal substrate of the present invention is covered with a metal protective film, and the resistance to the etching liquid is high, thereby preventing deterioration of the quality of the metal substrate.

(Step of forming the back electrode)

Next, as shown in FIG. 15, the back surface electrode 56 is formed on the back surface of the metal substrate 51.

(Formation steps of the mesa structure part)

In the same manner as the manufacturing method of the light-emitting diode (first embodiment), in order to form the mesa-type structure portion (excluding the protective film and the electrode film), the compound semiconductor layer other than the mesa-type structure portion, that is, the current At least a portion of the diffusion layer and the active layer, or all of the current diffusion layer and the active layer are wet etched.

Specifically, first, a photoresist pattern is formed in the same manner as the method of manufacturing the light-emitting diode (first embodiment).

Next, the compound semiconductor layer of the portion other than the mesa structure portion is subjected to wet etching.

The etching liquid used for the wet etching is not limited, and an As-based compound semiconductor material such as AlGaAs is preferably an ammonia-based etching liquid (for example, an ammonia/hydrogen peroxide water mixed solution), and a P system such as AlGaInP. The compound semiconductor material is suitable for an iodine-based etching solution (for example, potassium iodide/ammonia), the phosphoric acid/hydrogen peroxide water mixture is suitable for the AlGaAs system, and the bromine-methanol mixture is suitable for the P system.

In addition, a structure in which only the As system is formed can be used, and a structure in which the As/P system is mixed can be used. The As-structured portion can use an ammonia mixed liquid, and the P-based structural portion can use an iodine mixed liquid.

In the case of the compound semiconductor layer described above, that is, the contact layer 5 containing AlGaAs in the uppermost layer, the cladding layer 63a containing AlGaInP, the light-emitting layer 64 containing AlGaAs, the cladding layer 63b containing AlGaInP, and the GaP layer 53 In the case where the contact layer 5 and the light-emitting layer 64 of the As-based layer and the other P-based layers are used, it is preferable to use different etching liquids having high etching rates.

For example, it is preferable to use an iodine-based etching solution for the etching of the layer of the P-based layer, and to use the ammonia-based etching solution for the etching of the contact layer 5 and the light-emitting layer 64 of the As-based layer.

As the iodine-based etching liquid, for example, an etching liquid obtained by mixing iodine (I), potassium iodide (KI), pure water (H ₂ O), and ammonia water (NH ₄ OH) can be used.

Further, as the ammonia-based etching liquid, for example, an ammonia/hydrogen peroxide water mixed liquid (NH ₄ OH:H ₂ O ₂ :H ₂ O) can be used.

When the portion other than the mesa structure portion is removed by using the preferred etching liquid, first, the contact layer 5 containing AlGaAs in a portion other than the mesa structure portion is removed by etching using an ammonia-based etching solution.

When this etching is performed, since the next layer, that is, the cladding layer 55 containing AlGaInP functions as an etch stop layer, it is not necessary to strictly manage the etching time, for example, when the thickness of the contact layer 5 is set to about 0.05 μm, etching is performed. It takes about 10 seconds.

Next, the cladding layer 55 containing AlGaInP other than the mesa structure portion is etched and removed using an iodine-based etching solution.

When an etching liquid in which iodine (I) 500 cc, potassium iodide (KI) 100 g, pure water (H ₂ O) 2000 cc, and ammonia water (NH ₄ OH) 90 cc were mixed, the etching rate was 0.72 μm/min.

When this etching is performed, since the next layer, that is, the light-emitting layer 64 containing AlGaAs functions as an etch stop layer, it is not necessary to strictly manage the etching time, but for the case of the etching liquid, the thickness of the cladding layer 55 is set. When it is about 4 μm, etching can be performed for about 6 minutes.

Next, the light-emitting layer 64 containing AlGaAs in a portion other than the mesa structure portion is removed by etching using an ammonia-based etching solution.

When this etching is performed, since the next layer, that is, the cladding layer 63b containing AlGaInP functions as an etch stop layer, it is not necessary to strictly manage the etching time, but when the thickness of the light-emitting layer 64 is set to about 0.25 μm, etching is performed. It takes about 40 seconds to complete.

Next, the cladding layer 63b containing AlGaInP in a portion other than the mesa structure portion is removed by etching using an iodine-based etching solution.

There is a GaP layer 53 under the cladding layer 63b, but when the metal-containing reflective layer 52 under the GaP layer 53 is exposed, it is not ideal in electrical characteristics, so it is necessary to stop before reaching the GaP layer 53. Etching.

For example, when a GaP layer of 3.5 μm is formed and then the thickness of the GaP layer is 2.5 μm after the polishing is performed for 1 μm, and the thickness of the cladding layer 63b is 0.5 μm, it is necessary to set the etching time when the iodine-based etching solution is used. Into 4 minutes or less.

The step of removing the protective film, the step of removing the protective film in the portion of the dicing street and the contact layer, and the step of forming the outer surface electrode film can be carried out in the same manner as in the method of manufacturing the light-emitting diode (first embodiment). get on.

(single step)

Next, the light-emitting diodes on the wafer substrate are sequentially etched and laser-cut to be sliced.

Specifically, after the photoresist pattern having an opening is formed in the dicing street portion, the compound semiconductor layer and the reflective layer on the dicing street are etched away, and then the metal substrate is cut by laser cutting to complete singulation. The layer to be etched only after etching the compound semiconductor layer or the metal protective layer in addition to the compound semiconductor layer and the reflective layer, and the layer to be etched is not limited to the above.

(Metal protective film forming step on the side of the metal substrate)

The metal protective film can be formed on the side surface of the cut metal substrate of the formed light-emitting diode, under the same conditions as those of the upper and lower metal protective films.

[Examples]

Hereinafter, the light-emitting diode of the present invention and the method of manufacturing the same will be further described by way of examples, but the present invention is not limited to the embodiment. In the present embodiment, in order to perform characteristic evaluation, a light-emitting diode lamp in which a light-emitting diode chip is packaged on a substrate is produced.

(Example 1)

Example of the light-emitting diode of the first embodiment of the light-emitting diode system of the first embodiment.

In the light-emitting diode of the first embodiment, first, a compound semiconductor layer is sequentially laminated on a GaAs substrate including an n-type GaAs single crystal doped with Si to form an epitaxial wafer. The GaAs substrate has a (100) plane as a growth surface and a carrier concentration of 2 × 10 ¹⁸ cm ^-3 . Further, the layer thickness of the GaAs substrate was set to be about 250 μm. The compound semiconductor layer refers to an n-type lower DBR reflective layer comprising an n-type buffer layer of Si-doped GaAs, Si-doped Al _0.9 Ga _0.1 As and Al _0.1 Ga _0.9 As, including doped Si N-type lower cladding layer of Al _0.4 Ga _0.6 As, lower guiding layer containing Al _0.25 Ga _0.75 As, three pairs of well layers/barrier layers containing GaAs/Al _0.15 Ga _0.85 As, including Al _0.25 Ga _0.75 As P-type upper DBR reflection of the upper guide layer, p-type upper cladding layer containing Al-doped Al _0.4 Ga _0.6 As, C-doped Al _0.9 Ga _0.1 As and Al _0.1 Ga _0.9 As A layer comprising a contact layer of p-doped P-type Al _0.1 Ga _0.9 As.

In the present embodiment, a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 50 mm and a thickness of 250 μm using a reduced pressure organometallic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer. When the epitaxial growth layer is grown, as a raw material of the group III constituent element, trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga), and trimethylindium ( (CH ₃ ) ₃ In). Further, as a doping material for C, tetrabromomethane (CBr ₄ ) was used. Further, as a doping material for Si, dioxane (Si ₂ H ₆ ) is used. Further, as a raw material of the group V constituent element, phosphine (PH ₃ ) or arsine (AsH ₃ ) is used.

Further, the growth temperature of each layer was grown at 700 °C.

The buffer layer containing GaAs has a carrier concentration of about 2 × 10 ¹⁸ cm ^-3 and a layer thickness of about 0.5 μm. The lower DBR reflective layer is Al _0.9 Ga _0.1 As having a carrier concentration of about 1×10 ¹⁸ cm ⁻³ , a layer thickness of about 54 nm, and a carrier concentration of about 1×10 ¹⁸ cm ⁻³ . Al _0.1 Ga _0.9 As, which was formed to have a layer thickness of about 51 nm, alternately laminated 40 pairs. The lower cladding layer had a carrier concentration of about 1 × 10 ¹⁸ cm ^-3 and a layer thickness of about 54 nm. The lower guiding layer was made undoped and the layer thickness formed to be about 50 nm. The well layer was formed as GaAs which was undoped and had a layer thickness of about 7 nm, and the barrier layer was made of Al _0.15 Ga _0.85 As which was undoped and had a layer thickness of about 7 nm. Further, the well layer and the barrier layer are alternately laminated in three pairs. The upper guiding layer was made undoped and the layer thickness formed to be about 50 nm. The upper cladding layer had a carrier concentration of about 1 × 10 ¹⁸ cm ^-3 and a layer thickness of 54 nm. Further, the upper DBR reflective layer has Al ₉ Ga _0.1 As having a carrier concentration of about 1 × 10 ¹⁸ cm ^{-3 , a} layer thickness of about 54 nm, and a carrier concentration of about 1 × 10 ¹⁸ cm ^{-3 .} Al _0.1 Ga _0.9 As, which was formed to have a layer thickness of about 51 nm, alternately laminated 5 pairs.

The contact layer containing Al _0.1 Ga _0.9 As had a carrier concentration of about 3 × 10 ¹⁸ cm ^-3 and a layer thickness of about 250 nm.

Next, on the back surface of the substrate as the back surface electrode, an Au-type ohmic electrode was formed by vacuum vapor deposition so that the thickness of AuGe and Ni alloy was 0.5 μm, Pt was 0.2 μm, and Au was 1 μm.

Next, in order to form a mesa structure, a patterned photoresist (AZ5200NJ (manufactured by Clariant)) and a phosphoric acid of H ₂ PO ₄ :H ₂ O ₂ :H ₂ O=2:5:9 were used. The hydrogen peroxide water mixed solution was subjected to wet etching for 60 seconds to form a mesa structure portion and a flat portion. By this wet etching, the entire layer of the contact layer, the upper DBR reflective layer, and the active layer is removed, and a mesa-type structure portion having a top surface size of 190 μm × 190 μm, a height h of 7 μm, and a width w of 5 μm in a plan view is formed. Except for protective film and electrode film).

Next, since a protective film is to be formed, a protective film containing SiO ₂ of about 0.5 μm is formed.

Thereafter, after patterning by a photoresist (AZ5200NJ (manufactured by Clariant)), buffered hydrofluoric acid was used to form an opening having a concentric circular shape (outer diameter d _out : 166 μm, inner diameter d _in : 154 μm) _in plan view ( Refer to Figure 11) and the opening of the scribe line.

Next, in order to form an external surface electrode (film), after patterning by photoresist (AZ5200NJ (manufactured by Clariant)), 1.2 μm of Au and 0.15 μm of AuBe were sequentially deposited, and then formed by a lift-off process. In plan view, it is an outer surface electrode (p-type ohmic electrode) having a long side of 350 μm and a short side of 250 μm of a light-emitting hole 9b having a circular shape (diameter: 150 μm).

Thereafter, the film was alloyed by heat treatment at 450 ° C for 10 minutes to form low-resistance p-type and n-type ohmic electrodes.

Then, in order to form the light-shielding preventing film 16 on the side surface of the mesa-type structure portion, the pattern is formed by photoresist (AZ5200NJ (manufactured by Clariant)), and then 0.5 μm of Ti and 0.17 μm of Au are sequentially deposited. The light leakage preventing film 16 is formed by the separation process.

Next, the dicing saw is cut from the side of the compound semiconductor layer by cutting at the scribe line portion. Broken layer and dirt caused by cutting with sulfuric acid. The hydrogen peroxide mixed solution was removed by etching to prepare a light-emitting diode of the example.

A plurality of light-emitting diode lamps in which the light-emitting diode chips of the embodiment fabricated as described above were packaged on a carrier substrate were combined. The light-emitting diode lamp is supported (fixed) by a die bonder, and is bonded to a p-type ohmic electrode and a p-electrode terminal by a gold wire, and then sealed with a general epoxy resin.

In the light-emitting diode (light-emitting diode lamp), when a current flows between the n-type and p-type ohmic electrodes, infrared light having a peak wavelength of 850 nm is emitted. The forward voltage (V _F ) at a current of 20 milliamperes (mA) in the forward direction was 1.6V. The luminous output when the forward current was set to 20 mA was 1.5 mW. Further, the response speed (rise time: Tr) was 12.1 nsec.

Any of the 100 light-emitting diode lamps produced can obtain the same degree of characteristics, and is not considered to be leakage (short circuit) in the case where the protective film becomes a discontinuous film or the metal film for the electrode becomes a discontinuous film. The situation is caused by a poor power supply.

Fig. 16 is a graph showing the measurement results of the spectrum directly above the light-emitting diode (refer to the pattern diagram on the right side of the graph). The vertical axis represents the intensity of light, and the horizontal axis represents the wavelength.

As shown in Fig. 16, in the light-emitting diode of the example, the line width of the visible spectrum was narrow (high monochromaticity), and the half value width (HWHM) was 6.3 nm.

Fig. 17 is a graph showing the measurement results of the directivity of light emitted (refer to the pattern diagram on the right side of the graph). The horizontal axis of the graph in which the horizontal axis is connected from "-1" to "1" indicates that the light intensity (Int.) is 13,000. Therefore, for example, when the light intensity in a certain direction is 6,500, an image is formed on the circumference of the horizontal axis of "-0.5" connected to "0.5" in the direction. Further, for example, in the light-emitting diode of the embodiment, the light-emitting diode of the embodiment has a pattern from a circumference of approximately "-0.9" to a circumference (not shown) of "0.9" (not shown). Like, it is known that the light intensity in its range is about 90% of 13,000.

As shown in FIG. 17, the light-emitting diode of the embodiment has high strength (about 70% or more of 13,000) in a range of about ±15° from the light exit hole, and exhibits high directivity.

(Example 2)

Example of the light-emitting diode of the fourth embodiment of the second embodiment (in the case of using a metal substrate).

First, a Mo layer (foil, plate) having a thickness of 75 μm was coated with two Cu layers (foil, plate) having a thickness of 10 μm, and pressed by heating to form a metal having a thickness of 95 μm. Plate (before cutting and cutting). After the upper surface and the lower surface of the metal sheet were ground to form a glossy surface thereon, the surface was washed with an organic solvent to remove dirt. Next, on the entire surface of the metal sheet, a 2 μm Ni layer and a 1 μm Au layer as a metal protective film were sequentially formed by electroless plating to form a metal substrate (the metal substrate before the sheet cutting) ) 51.

Next, on the GaAs substrate including the Si-doped n-type GaAs single crystal, the compound semiconductor layer was sequentially laminated to fabricate an epitaxial wafer having an emission wavelength of 730 nm.

The GaAs substrate was a growth surface having a surface inclined by 15° from the (100) plane toward the (0-1-1) direction, and the carrier concentration was set to 2 × 10 ¹⁸ cm ^-3 . Further, the layer thickness of the GaAs substrate was set to be about 0.5 μm. The compound semiconductor layer is an n-type buffer layer 62a containing Si-doped GaAs, an etch stop layer 62b containing Si-doped (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P, and n-type Al _0.3 GaAs containing doped Si. Contact layer 5, an n-type upper cladding layer 63a containing Si-doped (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P, an upper guiding layer containing Al _0.4 Ga _0.6 As, and including Al _0.17 Ga _0.83 As/Al _0.3 Ga a well layer/barrier layer of _0.7 As, a lower guiding layer containing Al _0.4 Ga _0.6 As, a p-type lower cladding layer 63b containing Mg-doped (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P, including (Al An intermediate layer of a film of _0.5 Ga _0.5 ) _0.5 In _0.5 P and a p-type GaP layer 53 doped with Mg.

In the present embodiment, a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 50 mm and a thickness of 250 μm using a reduced pressure organometallic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer. When the epitaxial growth layer is grown, as a raw material of the group III constituent element, trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga), and trimethylindium ( (CH ₃ ) ₃ In). Further, as a doping raw material for Mg, dicyclopentadienyl magnesium (bis-(C ₅ H ₅ ) ₂ Mg) was used. Further, as a doping material for Si, dioxane (Si ₂ H ₆ ) is used. Further, as a raw material of the group V constituent element, phosphine (PH ₃ ) or arsine (AsH ₃ ) is used.

Further, the p-type GaP layer was grown at 750 ° C with respect to the growth temperature of each layer. The other layers are grown at 700 °C.

The buffer layer containing GaAs has a carrier concentration of about 2 × 10 ¹⁸ cm ^-3 and a layer thickness of about 0.5 μm. The etching stop layer was set to have a carrier concentration of 2 × 10 ¹⁸ cm ^-3 and a layer thickness of about 0.5 μm. The contact layer was set to have a carrier concentration of about 2 × 10 ¹⁸ cm ^-3 and a layer thickness of about 0.05 μm. The upper cladding layer had a carrier concentration of about 1 × 10 ¹⁸ cm ^-3 and a layer thickness of about 3.0 μm. The well layer was made of Al _0.17 Ga _0.83 As which was undoped and had a layer thickness of about 7 nm, and the barrier layer was made of Al _0.3 Ga _0.7 As which was undoped and had a layer thickness of about 19 nm. Further, the well layer and the barrier layer are alternately laminated in three pairs. The lower guiding layer is undoped and the layer thickness is formed to be about 50 nm. The lower cladding layer has a carrier concentration of about 8 × 10 ¹⁷ cm ^-3 and a layer thickness of about 0.5 μm. The intermediate layer had a carrier concentration of about 8 × 10 ¹⁷ cm ^-3 and a layer thickness of about 0.05 μm. The GaP layer had a carrier concentration of about 3 × 10 ¹⁸ cm ^-3 and a layer thickness of about 3.5 μm.

Next, the GaP layer was mirror-finished from the surface polished to a depth of about 1 μm. According to this mirror processing, the roughness of the surface of the current diffusion layer was formed to 0.18 nm.

Next, a reflective layer containing Au having a thickness of 0.7 μm was formed on the GaP layer. Then, a Ti layer as a barrier layer having a thickness of 0.5 μm was formed on the reflective layer, and an AuGe layer as a bonding layer having a thickness of 1.0 μm was formed on the barrier layer.

Next, a compound semiconductor layer and a reflection are formed on the GaAs substrate. The structure in which the layer or the like is placed and the metal substrate are placed in the opposite direction and placed in the decompression device, and are joined to form a bonded structure by a load of 500 kg by heating at 400 ° C.

Then, the GaAs substrate and the buffer layer of the growth substrate of the compound semiconductor layer are selectively removed by the ammonia-based etching liquid from the bonded structure, and then the etching stop layer is selectively removed by the hydrochloric acid-based etching liquid.

(Step of forming the back electrode)

Next, 1.2 μm of Au and 0.15 μm of AuBe were sequentially deposited on the back surface of the metal substrate 51 by vacuum deposition to form a back surface electrode 56.

Next, in order to form the mesa structure portion, after the photoresist pattern is formed, wet etching is performed for 10 seconds using an ammonia/hydrogen peroxide water mixture (NH ₄ OH:H ₂ O ₂ :H ₂ O) to remove the mesa. A current diffusion layer 55 of a portion other than the type structure portion.

Next, an iodine-based etching solution prepared by mixing iodine (I) 500 cc, potassium iodide (KI) 100 g, pure water (H ₂ O) 2000 cc, and ammonia water (NH ₄ OH) 90 cc was used for 45 seconds of wet etching. The upper cladding layer 55 is removed from the portion other than the mesa structure.

Next, wet etching is performed for 40 seconds using the ammonia/hydrogen peroxide water mixture (NH ₄ OH:H ₂ O ₂ :H ₂ O), and the upper portion of the guide layer and the light-emitting layer 64 other than the mesa structure portion are removed. And the lower guiding layer.

Next, wet etching was performed for 50 seconds using the iodine-based etching liquid, and a portion of the lower cladding layer 63b other than the mesa structure portion was removed. Thereby, a mesa structure portion is formed.

Next, since a protective film is to be formed, a protective film containing SiO ₂ of about 0.5 μm is formed.

Thereafter, after the photoresist pattern was formed, an opening (see FIG. 11) having a concentric circular shape (outer diameter d _out : 166 μm, inner diameter d _in : 154 μm) and an opening of the scribe line portion were formed using buffered hydrofluoric acid.

Next, in order to form the outer surface electrode (film), after forming the photoresist pattern, AuGe, Ni alloy is formed into a thickness of 0.5 μm by vacuum evaporation, Pt is formed into 0.2 μm, Au is formed by 1 μm, and then formed by a lift-off process. An outer surface electrode (n-type ohmic electrode) having a long side of 350 μm and a short side of 250 μm in a circular (diameter: 150 μm) light-receiving hole 9b.

Thereafter, heat treatment was performed at 450 ° C for 10 minutes to alloy it to form a low-resistance n-type ohmic electrode.

Next, in order to form the light leakage preventing film 16 on the side surface of the mesa structure portion, after the photoresist pattern is formed, 0.5 μm of Ti and 0.17 μm of Au are sequentially deposited, and the light leakage preventing film 16 is formed by a lift-off process.

Next, wet etching and laser cutting were sequentially performed to form a light-emitting diode of the example.

A plurality of light-emitting diode lamps in which the light-emitting diode chips of the embodiment fabricated as described above were packaged on a carrier substrate were combined. The light-emitting diode lamp is supported (fixed) by a die bonder, and is bonded to a p-type ohmic electrode and a p-electrode terminal by a gold wire, and then sealed with a general epoxy resin.

In the light-emitting diode (light-emitting diode lamp), when a current flows between the n-type and p-type electrodes, infrared light having a peak wavelength of 730 nm is emitted. The forward voltage (V _F ) at a current of 20 milliamperes (mA) in the forward direction was 1.6V. The luminous output when the forward current was set to 20 mA was 3.2 mW. Further, the response speed (rise time: Tr) was 12.6 nsec.

Any of the 100 light-emitting diode lamps produced can obtain the same degree of characteristics, and is not considered to be a leakage (short circuit) in the case where the protective film becomes a discontinuous film or the metal film for the electrode becomes a discontinuous film. The situation is caused by a poor power supply.

(Comparative example)

An example of a light-emitting diode having a wavelength of 850 nm in which a thick film is grown by liquid phase epitaxy and the structure of the substrate is removed is shown.

The AlGaAs layer was grown on the GaAs substrate using a sliding boat type growth device.

A p-type GaAs substrate is provided in the substrate storage groove of the sliding boat type growth device, and Ga metal, GaAs polycrystal, metal Al, and dopant are placed in a crucible for growth of each layer.

The layer to be grown is a four-layer structure of a transparent thick film layer (first p-type layer), a lower cladding layer (p-type cladding layer), an active layer, and an upper cladding layer (n-type cladding layer), and This sequence is layered.

The sliding boat type growth device equipped with the raw materials is installed in a quartz reaction tube, and is heated to 950 ° C in a hydrogen stream. After the raw material is melted, the ambient temperature is lowered to 910 ° C, and the slider is pushed to the right. After the pressure is brought into contact with the molten raw material (melted material), the temperature is lowered at a rate of 0.5 ° C / minute, and after reaching a predetermined temperature, the slider is repeatedly pressed and sequentially contacted with each molten raw material to cause a high temperature operation, and finally, After the melt is contacted, the ambient temperature is lowered to 703 ° C to grow the n-cladding layer, and then the slider is pushed to separate the molten material from the wafer and the epitaxial growth is completed.

The structure of the epitaxial layer obtained is such that the first p-type layer has an Al composition of X1=0.3-0.4, a layer thickness of 64 μm, a carrier concentration of 3×10 ¹⁷ cm ⁻³ , and a p-type cladding layer of Al composition X2=0.4~ 0.5, layer thickness 79 μm, carrier concentration 5 × 10 ¹⁷ cm ^-3 , p-type active layer is a composition having an emission wavelength of 850 nm, a layer thickness of 1 μm, a carrier concentration of 1 × 10 ¹⁸ cm ^-3 , and an n-type cladding layer of Al The composition was X4 = 0.4 to 0.5, the layer thickness was 25 μm, and the carrier concentration was 5 × 10 ¹⁷ cm ^-3 .

After the epitaxial growth is completed, the epitaxial substrate is taken out, the surface of the n-type GaAlAs cladding layer is protected, and the p-type GaAs substrate is selectively removed by an ammonia-hydrogen peroxide-based etching solution. Thereafter, a gold electrode was formed on both surfaces of the epitaxial wafer, and an electrode having a long side of 350 μm was used to form a surface electrode in which a wire bonding pad having a diameter of 100 μm was placed at the center. An ohmic electrode having a diameter of 20 μm was formed on the back electrode at intervals of 80 μm. Thereafter, by cutting and etching, a 350 μm square light-emitting diode formed by forming an n-type AlGaAs layer on the surface side was produced.

When a current flows between the n-type and p-type ohmic electrodes of the light-emitting diode of the comparative example, infrared light having a peak wavelength of 850 nm is emitted. The forward voltage (V _F ) at a current of 20 milliamperes (mA) in the forward direction was 1.9V. The luminous output when the forward current was set to 20 mA was 5.0 mW. Further, the response speed (Tr) is 15.6 nsec, which is slower than the embodiment of the present invention.

As shown in FIG. 16, in the light-emitting diode of the comparative example, the line width of the visible spectrum was wide, and the half value width (HWHM) was 42 nm.

As shown in FIG. 17, in the light-emitting diode of the comparative example, about 20% of the hemispherical shape of 13,000 is emitted as the center of the light-emitting diode, which is much lower in directivity than the embodiment. .

[Industrial availability]

The present invention is applicable to a light-emitting diode and a method of manufacturing the same.

1‧‧‧Substrate

2‧‧‧Lower DBR layer

3‧‧‧Active layer

4‧‧‧Upper DBR layer

5‧‧‧Contact layer

6‧‧‧flat

7‧‧‧ Platform type structure department

7a‧‧‧Slanted side

7b‧‧‧ top surface

7ba‧‧‧ Peripheral area

8‧‧‧Protective film

8b‧‧‧Power window

9‧‧‧Electrode film

9b‧‧‧Light shot hole

11‧‧‧Lower coating

12‧‧‧Lower guide layer

13‧‧‧Lighting layer

14‧‧‧ upper guide layer

15‧‧‧Upper cladding

16‧‧‧Light leakage prevention film

20‧‧‧ compound semiconductor layer

23‧‧‧resist pattern

40‧‧‧current diffusion layer

51‧‧‧Metal substrate (conductive substrate)

51c‧‧‧Metal protective film

52‧‧‧reflective layer

53‧‧‧GaP layer

54‧‧‧Active layer

56‧‧‧Back electrode

61‧‧‧Semiconductor substrate (growth substrate)

63a‧‧‧Upper cladding

63b‧‧‧lower cladding

64‧‧‧Lighting layer

100, 200, 300, 400‧‧‧Lighting diodes

Fig. 1 is a schematic cross-sectional view showing a light-emitting diode according to a first embodiment of the present invention.

Fig. 2 is a perspective view showing a light-emitting diode according to a first embodiment of the present invention.

Fig. 3 is an electron micrograph showing a cross section of an inclined slope of the light-emitting diode of the first embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view showing an active layer of a light-emitting diode according to the first embodiment of the present invention.

Fig. 5 is a cross-sectional schematic view showing a light-emitting diode according to a second embodiment of the present invention.

Fig. 6 is a schematic cross-sectional view showing a light-emitting diode according to a third embodiment of the present invention.

Fig. 7 is a cross-sectional schematic view showing a light-emitting diode according to a fourth embodiment of the present invention.

FIG. 8 is a cross-sectional schematic view for explaining a method of manufacturing the light-emitting diode according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional schematic view for explaining a method of manufacturing the light-emitting diode according to the first embodiment of the present invention.

Figure 10 is a graph showing the relationship between depth and width versus etching time for wet etching.

Fig. 11 is a cross-sectional schematic view showing a method of manufacturing the light-emitting diode according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a step of an example of a manufacturing process of a metal substrate used in the light-emitting diode according to the fourth embodiment of the present invention.

Fig. 13 is a cross-sectional view showing the steps of an example of a method of manufacturing the light-emitting diode according to the fourth embodiment of the present invention.

Fig. 14 is a cross-sectional view showing the steps of an example of a method of manufacturing a light-emitting diode according to a fourth embodiment of the present invention.

Fig. 15 is a cross-sectional view showing the steps of an example of a method of manufacturing a light-emitting diode according to a fourth embodiment of the present invention.

Fig. 16 is a graph showing the measurement results of the spectrum directly above the light-emitting diode.

Fig. 17 is a graph showing the measurement results of the directivity of illuminating light.

Fig. 18 is a cross-sectional view showing a conventional light-emitting diode.

1‧‧‧Substrate

2‧‧‧Lower DBR layer

3‧‧‧Active layer

4‧‧‧Upper DBR layer

5‧‧‧Contact layer

Section 5a‧‧‧

6‧‧‧flat

7‧‧‧ Platform type structure department

7a‧‧‧Slanted side

7b‧‧‧ top surface

7ba‧‧‧ Peripheral area

8‧‧‧Protective film

Section 8a‧‧‧

8b‧‧‧Power window

Section 8ba‧‧‧

Section 8c‧‧‧

8d‧‧‧section

9‧‧‧Electrode film

Section 9a‧‧‧

9b‧‧‧Light shot hole

9bb‧‧‧section

Section 9c‧‧‧

9d‧‧‧section

16‧‧‧Light leakage prevention film

100‧‧‧Lighting diode

Claims (15)

A light-emitting diode is a light-emitting diode having a reflective layer and a compound semiconductor layer containing an active layer on a substrate, and has a flat portion and a mesa structure portion having an inclined side surface and a top surface. At least a part of each of the flat portion and the mesa structure portion is sequentially covered with a protective film and an electrode film, and the mesa structure portion includes at least a part of the active layer, and the inclined side surface is formed by wet etching, and The cross-sectional area in the horizontal direction is continuously reduced toward the top surface, and each of the inclined side surfaces is formed to be offset with respect to the orientation surface of the substrate, and the protective film covers at least a part of the flat portion and the terrace. All of the inclined side faces of the structural portion and the peripheral region of the top surface of the mesa structure portion have an energization window that exposes a part of the surface of the compound semiconductor layer on the inner side of the peripheral region, and the electrode film Directly contacting the surface of the compound semiconductor layer exposed from the energization window, and Covering a portion of the protective film formed on the flat portion and a protective film formed on the inclined side surface of the mesa-type structural portion, and forming a light-emitting hole on a top surface of the mesa-type structural portion Continuous film. The light-emitting diode of claim 1, wherein the reflective layer is a DBR reflective layer. The light-emitting diode of claim 2, wherein the upper DBR reflective layer is provided on the opposite side of the active layer opposite to the substrate. The light-emitting diode of claim 1, wherein the reflective layer comprises a metal. The light-emitting diode according to any one of claims 1 to 4, wherein the compound semiconductor layer has a contact layer in contact with the electrode film. The light-emitting diode according to any one of claims 1 to 4, wherein the mesa-type structure portion includes all of the active layer and a part or all of the reflective layer. The light-emitting diode according to any one of claims 1 to 4, wherein the mesa-type structural portion is rectangular in plan view. The light-emitting diode according to any one of claims 1 to 4, wherein the height of the mesa structure portion is 3 to 10 μm, and the width of the inclined side surface in a plan view is 0.5 to 7 μm. The light-emitting diode according to any one of claims 1 to 4, wherein the light-emitting apertures are circular or elliptical in plan view. The light-emitting diode of claim 9, wherein the light-emitting aperture has a pore diameter of 50 to 150 μm. The light-emitting diode according to any one of claims 1 to 4, wherein the portion on the flat portion of the electrode film has a bonding wire. The light-emitting diode according to any one of claims 1 to 4, wherein the light-emitting layer contained in the active layer comprises a multiple quantum well. The light-emitting diode according to any one of claims 1 to 4, wherein the light-emitting layer contained in the active layer contains ((Al _X1 Ga _1-X1 ) _Y1 In _1-Y1 P (0≦X1≦) 1,0<Y1≦1), (Al _X2 Ga _1-X2 )As(0≦X2≦1), (In _X3 Ga _1-X3 )As(0≦X3≦1)). A method for manufacturing a light-emitting diode, comprising: forming a reflective layer and a compound semiconductor layer containing an active layer on a substrate; and forming a square resist pattern on each of the compound semiconductor layers a step of forming a surface biasing method; performing wet etching on the compound semiconductor layer on which the photoresist pattern is formed, forming a cross-sectional area in the horizontal direction, forming a mesa-type structural portion that continuously decreases toward the top surface, and a step of forming a flat portion around the ground structure portion, and forming a conductive window that exposes a part of a surface of the compound semiconductor layer on a top surface of the mesa structure portion, and is formed on the mesa structure portion and the flat portion a step of protecting the film; and directly contacting the surface of the compound semiconductor layer exposed from the energization window, and covering at least one portion of the protective film formed on the flat portion and the inclined side surface of the mesa structure portion All of the protective film is formed in such a manner that the top surface of the mesa-type structural portion has a light exit hole The electrode film of the step. The method for producing a light-emitting diode according to claim 14, wherein the wet etching is performed by using a phosphoric acid/hydrogen peroxide water mixture, an ammonia/hydrogen peroxide water mixture, a bromine methanol mixture, and a potassium iodide. At least one of the group of / ammonia is carried out.