TWI477030B - System, battery pack and method for balancing voltage between battery packs - Google Patents

Description

System, battery pack and method for balancing voltage between battery packs Related application

The present application is entitled "High-Efficiency Switched-Capacitor Power Conversion" by U.S. Patent Application Serial No. 12/535,974, filed on Jan. 5, 2009. Part of the continuation-in part, and hereby claims priority under 35 USC § 120 (agent number APL-P7723US1).

The disclosed invention is generally related to a battery pack consisting of a plurality of battery packs coupled together in series. More specifically, the disclosed embodiments relate to methods and apparatus for balancing the voltage between battery packs within a battery pack.

Battery performance is critical to the effective operation of portable computing devices Keys, such as laptops. To provide a higher supply voltage, the battery packs on the inside of the portable computing device are typically stacked in series inside the battery pack. This configuration provides power efficiently because conduction losses are lower in this series configuration. (It should be noted that the battery pack may include one or more batteries that are electrically connected in parallel.)

However, if the battery packs constituting the battery pack are not precisely matched in capacity, the battery pack may suffer from an imbalance. Such battery pack imbalances may exist in new battery packs due to manufacturing variations between battery packs, or they may be caused by exceeding battery pack life when battery pack capacity decays at different rates over time. An unbalanced battery pack has a reduced capacity because the battery pack with the highest state of charge will result in the end of the charging process, which means that the battery pack with a lower state of charge can never be fully charged. In addition, when the battery pack is discharged, the battery pack having the least charge may cause the discharge process to stop, even though the charge may remain in the other battery pack.

Many mechanisms are currently used to handle imbalances in the battery pack. The "passive balancer" operates by switching the resistance in parallel with the selected battery pack during the charging process. The effect of these resistors is to transfer current around the selected battery pack during the charging process, which results in a slower charging of the selected battery pack, which assists in equalization of the voltage across the battery pack during the charging process. While the passive balancer can equalize the battery voltage during the charging process, they do not alleviate the imbalance problems that arise during the discharge process.

In contrast to passive balancers, the "active balancer" is based on an inductor and can be operated at any time, for example, when the battery pack is being charged, discharged, or at rest. Active balancer by selectively coupling the inductor to the battery pack Operating with current flow between the battery packs. Unfortunately, such active balancers can create safety issues. For example, if the switching process is not carefully controlled or if there is a fault in the switch, excessive current may be pushed into the battery pack, which may damage the battery pack.

Therefore, what is needed is a method and apparatus for solving the problem of capacity imbalance between battery packs without the disadvantages of existing passive balancers or active balancers.

The disclosed embodiments provide a system for balancing the voltage between battery packs. The system includes a plurality of battery packs including a first set and a second set, and a first capacitor having a first end and a second end. The system also includes a first set of switching devices that selectively couple the first and second ends of the first capacitor to the first and second ends of the first set, and to the second set One and second ends. The system additionally includes a clock generation circuit that generates a clock signal having substantially non-overlapping clock phases, including a first phase and a second phase. Configuring the pulse generation circuit to control the first set of switching devices such that the first and second ends of the first capacitor are coupled to the first group, respectively, during the first phase The first and second ends, and the first and second ends of the first capacitor are coupled to the first and second ends of the second group, respectively, during the second phase.

In some embodiments, each battery pack includes one or more batteries, wherein if the battery pack includes a plurality of batteries, the plurality of batteries are electrically coupled in parallel.

In some embodiments, the plurality of cells are electrically coupled in series to form a battery pack.

In some embodiments, the system further includes a second set of switching devices; and a second capacitor having a first end and a second end. In these embodiments, the clock generation circuit is configured to control the second set of switching devices such that the first and second ends of the second capacitor are coupled to the first phase during the first phase, respectively The first and second ends of the second group, and the first and second ends of the second capacitor are coupled to the first group of the first group respectively during the second phase Second end.

In some embodiments, the first set of switching devices includes: a first switch coupling the first end of the first capacitor to the first end of the first group during a first phase; An exchanger that couples the second end of the first capacitor to the second end of the first group during a first phase; a third switch that is the first capacitor during the second phase a first end coupled to the first end of the second group; and a fourth switch coupling the second end of the first capacitor to the second end of the second group during the second phase .

In some embodiments, the plurality of groups also includes a third group electrically coupled in series with the first group and the second group. The system also includes a third capacitor having a first end and a second end. In such embodiments, the first set of switching devices and the clock generation circuit are configured such that the first and second ends of the third capacitor are coupled to the first phase during the first phase The first and second ends of the second group, and the first and second ends of the third capacitor are respectively coupled to the third group during the second phase The first and second ends of the.

In some embodiments, the clock generation circuit is a resonant LC oscillator circuit including at least one inductor and at least one capacitor.

In some embodiments, the resonant LC oscillator circuit includes: a first phase output; a second phase output; a first inductor coupled between the voltage source and the first phase output; coupled to the voltage source and a second inductor between the second phase outputs; a source having a source coupled to the substrate, a terminal coupled to the first phase output, and a first terminal coupled to the gate of the second phase output And a second transistor having a source coupled to the substrate voltage, a terminal coupled to the second phase output, and a gate coupled to the first phase output.

In some embodiments, the first set of switching devices includes a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

In some embodiments, the first capacitor includes one or more ceramic capacitors of very low equivalent series resistance (ESR) and very low equivalent series inductance (ESL).

In some embodiments, the clock generation circuit is configured to operate intermittently to balance the voltage between the first set and the second set.

In some embodiments, the clock generation circuit is configured to operate continuously to maintain a balanced voltage between the first set and the second set.

102, 104, 302, 304‧‧‧Switch Capacitor Block (SCB)

103‧‧‧Battery pack

106, 306‧‧‧Oscillator block

108, 109, 308‧‧‧ battery pack

110‧‧‧V _LO

111‧‧‧Oscillator supply voltage V _OSC

112‧‧‧V _HI

113‧‧‧Base voltage V _B

201‧‧‧Node A

202, 204, 206, 208‧‧‧ exchange devices

210, 312‧‧ ‧ capacitor

309‧‧‧V _HX

310, 314‧‧‧Optoelectronics

402, 404‧‧‧Inductors

408, 410‧‧‧FET

412‧‧‧ bootstrap capacitor C _B2

414‧‧‧ bootstrap capacitor C _B1

416, 418‧‧ ‧ Zener diode

420, 422‧‧‧cross-coupled FET

φ _1X , φ _2X ‧‧‧ signals

φ _1H , φ _2H , φ _1L , φ _2L ‧‧‧ output

C _L , C _H , P _L , P _H ‧‧‧ two phase clock

C _X , P _X ‧‧‧ input

1 depicts coupling to a battery in accordance with an embodiment of the present invention Package voltage balancer.

2 depicts the structure of a switched capacitor block in accordance with an embodiment of the present invention.

FIG. 3A depicts a voltage balancer for three battery packs in accordance with an embodiment of the present invention.

3B depicts the structure of an associated switched capacitor block in accordance with an embodiment of the present invention.

4 depicts a resonant clock generation circuit in accordance with an embodiment of the present invention.

FIG. 5 presents a flow chart depicting voltage balancing processing in accordance with an embodiment of the present invention.

The following description is presented to enable any person skilled in the art to make and use the disclosed embodiments, and in the <Desc/Clms Page number> The various modifications of the disclosed embodiments are obvious to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the disclosed embodiments. Therefore, the disclosed embodiments are not limited to the embodiments shown, but the broadest scope of the principles and characteristics disclosed herein.

The data structures and codeologies described in this embodiment are typically stored in a non-transitory computer readable storage medium, which may be any device or medium that can store programs and/or materials for use by the computer system. The Non-transitory computer readable storage media include, but are not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as hard disk drives, magnetic tape, CD (CD), DVD (digitally diverse) A disc or digital video disc), or other medium currently known or later developed to store code and/or material.

The methods and processes described in the embodiments can be embodied as code and/or data, which can be stored in a non-transitory computer readable storage medium as described above. When the computer system reads and executes the code and/or data stored in the non-transitory computer readable storage medium, the computer system implements the current data structure and the code and stores the data in a non-transitory computer readable storage medium. Other methods and treatments. Additionally, the methods and processes described below can be included in a hardware module. For example, the hardware modules can include, but are not limited to, application specific integrated circuit (ASIC) chips, field effect programmable gate arrays (FPGAs), and others currently known or later developed. Stylized logic device. When the hardware module is activated, the hardware modules implement methods and processes included in the hardware modules.

Voltage balancer

FIG. 1 depicts a voltage balancer coupled to a battery pack 103 in accordance with an embodiment of the present invention. The battery pack 103 includes electrically coupled together in series two battery packs 108-109, wherein the voltage across the lines V _LO -V _B across the battery 109 and the battery voltage V _HI 108 lines of -V _LO. It should be noted that each of the battery packs 108-109 includes one or more batteries, wherein if the battery pack includes a plurality of batteries, the plurality of batteries are electrically coupled in parallel.

In the embodiment depicted in FIG. 1, oscillator block 106 receives oscillator supply voltage V _OSC 111 from an oscillator voltage source and produces four versions of the two phase clock, ie, C _L , C _H , P _L , and P _H . The two phase clocks control two switched capacitor blocks (SCB) 102 and 104, which selectively exchange capacitors between the battery packs 108-109 during the reverse clock phase. It should be noted that the effect of the process of exchanging capacitors between battery packs 108-109 is to equalize the voltage between battery packs 108-109. More specifically, during the first clock phase, the SCB 102 is coupled to a first capacitor (see capacitor 210 in FIG. 2) that spans the terminal of the battery pack 108, while the SCB 104 is coupled to the terminal across the battery pack 109. Two capacitors (not shown). Second, during the second clock phase, the SCB 102 is coupled to a first capacitor that spans the terminal of the battery pack 109 while the SCB 104 is coupled to a second capacitor that spans the terminal of the battery pack 108. It should be noted that since the current can continuously flow into and out of the battery packs 108 and 109 (except for a small amount of time when the capacitors in the SCBs 102 and 104 are exchanged between the battery packs 108 and 109), the second SCBs 102 and 104 are used instead. A single SCB is intended to eliminate current flow through the system.

Switch capacitor block

2 depicts the structure of an example switched capacitor block 102 in accordance with an embodiment of the present invention. SCB 102 includes a capacitor 210 (also referred to as a "pump capacitor") and a set of switching devices 202, 204, 206, and 208. In the illustrated embodiment, switching devices 202, 204, 206, and 208 are power metal oxide semiconductor field effect transistors (MOSFETs). Pay attention to Figure 2 The directivity of the inscribed diodes of the MOSFETs 202, 204, 206, and 208 is also depicted.

FIG. 2 additionally depicts the connections of MOSFETs 202, 204, 206, and 208. More specifically, MOSFET 202 when the clock input C _H under the control terminal of the first capacitor 210 is coupled to V _LO 110; MOSFET 206 when the clock input C _{L is} the control terminal of the second capacitor 210 is coupled To the substrate voltage V _B 113; the MOSFET 204 couples the first terminal of the capacitor 210 to the V _HI 112 under the control of the clock input P _H ; and the MOSFET 208 places the second capacitor 210 under the control of the clock input P _L The terminal is coupled to V _LO 110.

During the first clock phase, the first terminal of capacitor 210 is coupled to V _LO 110 and the second terminal of capacitor 210 is coupled to V _B . This causes the voltage across capacitor 210 to become V _LO -V _B , which is the voltage across battery pack 109 in FIG. During the second clock phase, the first terminal of capacitor 210 is coupled to V _HI 112 and the second terminal of capacitor 210 is coupled to V _LO 110. This causes the voltage across capacitor 210 to become V _HI -V _LO , which is the voltage across battery pack 108 in FIG. It should be noted that the alternating coupling of capacitors 210 between battery packs 108 and 109 results in voltage equalization of battery packs 108 and 109. More specifically, if the battery pack 108 has a higher voltage than the battery pack 109, when the capacitor 210 is coupled to the battery pack 108, current will move from the battery pack 108 to the SCB 102, and then when the capacitor 210 is coupled When the battery pack 109 is reached, the charge will move from the capacitor 210 to the battery pack 109.

In one embodiment, a capacitor 210 is implemented using a parallel capacitor bank, where each capacitor is a 100 μF ceramic capacitor. The second terminal of the capacitor bank swings between V _B and V _LO . Therefore, the gate drive for the MOSFET 208 that couples the second terminal of the capacitor bank to V _LO must have a voltage swing of at least V _G + V _LO , where the V _G system R _ds (on) reaches its minimum conduction. The gate drive voltage required for the resistor. Similarly, the first terminal of capacitor 210 swings between V _LO and V _HI . Therefore, the MOSFETs 202 and 204 connected to the first terminal of the capacitor bank do not have to sway below V _LO . The gate drive signals can be oscillated between V _LO +V _B +V _G and V _HI +V _B +V _G by an input voltage bias. It should be noted that the energy required to drive each gate is proportional to (V _LO +V _G ) ² .

Voltage balancer for three battery packs

FIG. 3A depicts a voltage balancer for three battery packs in accordance with an embodiment of the present invention. Depicted in FIG. 3A depicts a system similar to the system of FIG. 1 except that the battery pack 103 includes three battery packs serially coupled together 109,108, and 308, wherein the voltage across the battery system 109 V _LO - V _B , the voltage system V _HI -V _LO across the battery pack 108, and the voltage system V _XH -V _HI across the battery pack 308. Again, in comparison with oscillator block 106 of FIG. 1, oscillator block 306 generates two additional signals φ _1X and φ _2X that are fed into additional inputs C _X and P _X in switching capacitor blocks 302-304. .

FIG. 3B depicts the structure of a swap capacitor block 302 in accordance with an embodiment of the present invention. It should be noted that FIG. 3B includes all of the circuits depicted in FIG. 2 and additionally includes two transistors 310 and 314 and additional capacitors. 312, stacked on top of the capacitor 210. It is also noted that the lower terminal of capacitor 312 is attached to node A 201.

During the first clock phase, the first terminal of capacitor 312 is coupled to V _HI 112 and the second terminal of capacitor 312 is coupled to V _LO 110. This causes the voltage across capacitor 312 to become V _HI - V _LO , which is the voltage across battery pack 108 in Figure 3A. During the second clock phase, the first terminal of capacitor 312 is coupled to V _HX 309 and the second terminal of capacitor 312 is coupled to V _HI 112. This results in the voltage across the capacitor 312 becomes V _XH -V _HI, which line the voltage across Fig. 3A of the battery pack 308. It should be noted that the alternating coupling capacitor 312 between the battery packs 108 and 308 equalizes the voltage between the battery packs 108 and 308. At the same time, capacitor 210 is exchanged between positive battery packs 109 and 108, which equalizes the voltage between battery packs 109 and 108.

Resonance clock generation circuit

4 depicts a resonant clock generation circuit that can be used to implement oscillator block 106 of FIG. 1 or oscillator block 306 of FIG. 3A, in accordance with an embodiment of the present invention. Referring to the bottom of Figure 4, the resonant clock generation circuit includes two complementary circuit portions that produce opposite clock phases. The first circuit portion includes an inductor 402 and an FET 410 and produces an output φ _2L . The second complementary circuit portion includes an inductor 404 and an FET 408 and produces an output φ _1L , where φ _1L and φ _2L provide opposite clock phases. It is noted that FETs 408 and 410 are cross-coupled such that the control inputs for each of FETs 408 and 410 are taken from the output of the complementary circuit portion. It is also important to note that the output load capacitance of the opposite clock phase concentrates the gate capacitance of each FET. (Also note that the load capacitance is at the gate capacitance of the SCB.)

During operation of the resonant clock generation circuit, energy oscillates back and forth between the inductive and capacitive circuit components without significant conduction or switching losses. More specifically, in the first circuit portion, energy oscillates between the inductor 402 and the load capacitance for outputting φ _2L , which is concentrated with respect to the gate capacitance of the FET 408. Similarly, in the second circuit portion, energy oscillates between the inductor 404 and the load capacitance for output φ _1L , which is concentrated with respect to the gate capacitance of the FET 410.

The top of Figure 4 depicts a corresponding circuit that produces outputs φ _1H and φ _2H . The voltages on the outputs φ _1H and φ _2H follow the voltages on the outputs φ _1L and φ _2L but are biased to a higher voltage level. This is accomplished by using two bootstrap capacitors C _B1 414 and C _B2 412 and two cross-coupled FETs 422 and 420 that clamp the high clock output to V _LO during a phase, The clock output is then followed by a positive displacement of V _LO during another phase. The high voltage levels on outputs φ _1H and φ _2H can be used to drive MOSFETs 202 and 204 depicted in FIG. As mentioned in the discussion above, these MOSFETs require a gate drive signal that oscillates between V _LO and V _HI +V _G . As depicted in the top of Figure 4, the dotted box A can be stacked again to provide the "very high" (XH) output of Figure 3B.

It should be noted that the Zener diodes 416 and 418 (which may be, for example, 19V Zener diodes) are respectively coupled between the outputs φ _2L and φ _1L and grounded to protect the circuits from being energized during energization. For large transient voltages. It should also be noted that the cross-coupled FETs 420 and 422 may be replaced with a general diode having an anode coupled to V _LO and a cathode coupled to φ _1H or φ _2H .

Voltage balance processing

FIG. 5 presents a flow chart depicting voltage balancing processing in accordance with an embodiment of the present invention. During operation, the system uses a clock generation circuit to generate a clock signal having substantially non-overlapping clock phases, including a first phase and a second phase (step 502). The system applies the clock signals to the first set of switching devices such that the first and second ends of the first capacitor are respectively coupled to the first of the first group during the first phase And the second end, and during the second phase, the first and second ends of the first capacitor are respectively coupled to the first and second ends of the second group (step 504). The system also applies the clock signal to the second set of switching devices such that the first and second ends of the second capacitor are coupled to the second group of the second group during the first phase The first and second ends of the second capacitor are coupled to the first and second ends of the first group, respectively, during the second phase (step 506).

The description of the embodiments has been presented above for the purposes of illustration and description. They are not to be considered as a thorough disclosure or limitation of the invention. Thus, many modifications and variations will be apparent to those skilled in the invention. Further, the above disclosure is not to be construed as limiting the invention. The scope of the invention is defined by the scope of the appended claims.

Claims (17)

A system for balancing voltage between battery packs, comprising: a plurality of battery packs including a first group and a second group; a first capacitor having a first end and a second end; and a second capacitor having a first end and a second a first set of switching devices that selectively couples the first and second ends of the first capacitor to the first and second ends of the first group, and the first a second end; the second set of switching devices selectively coupling the first and second ends of the second capacitor to the first and second ends of the first group, and the second group a first and a second end; a pulse generation circuit that generates a clock signal having a substantially non-overlapping clock phase, including a first phase and a second phase; wherein the clock generation circuit is configured to: control the first group Exchanging means, wherein the first and second ends of the first capacitor are coupled to the first and second ends of the first group, respectively, during the first phase, and during the second phase Coupling the first and second ends of the first capacitor to the first and And controlling the second set of switching devices to couple the first and second ends of the second capacitor to the first and second of the second group, respectively, during the first phase Ending, and during the second phase, coupling the first and second ends of the second capacitor to the first group respectively First and second ends. The system of claim 1, wherein each battery pack comprises one or more batteries, wherein if the battery pack comprises a plurality of batteries, the plurality of batteries are electrically coupled in parallel. The system of claim 1, wherein the plurality of batteries are electrically coupled in series to form a battery pack. The system of claim 1, wherein the first group of switching devices comprises: a first switch coupling the first end of the first capacitor to the first group of the first group during a first phase One end; a second switch coupling the second end of the first capacitor to the second end of the first group during a first phase; a third exchanger that will The first end of the first capacitor is coupled to the first end of the second group; and the fourth switch is coupled to the second group of the second end of the first capacitor during the second phase The second end. The system of claim 1, wherein the plurality of battery packs further includes a third group electrically coupled in series with the first group and the second group; wherein the system additionally includes a first end and a a third capacitor of the second end; and wherein the first set of switching devices and the clock generating circuit are configured to couple the first and second ends of the third capacitor to the first phase, respectively The first and second ends of the second group, and in the second During the phase, the first and second ends of the third capacitor are respectively coupled to the first and second ends of the third group. The system of claim 1, wherein the clock generation circuit is a resonant LC oscillator circuit including at least one inductor and at least one capacitor. The system of claim 6, wherein the resonant LC oscillator circuit comprises: a first phase output; a second phase output; a first inductor coupled between the voltage source and the first phase output; An inductor coupled between the voltage source and the second phase output; a first transistor having a source coupled to the substrate voltage, a terminal coupled to the first phase output, and coupled to the a gate of the second phase output; and a second transistor having a source coupled to the substrate voltage, a terminal coupled to the second phase output, and a gate coupled to the first phase output. The system of claim 1, wherein the first set of switching devices comprises a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A system as claimed in claim 1, wherein the first capacitor comprises one or more ceramic capacitors of very low equivalent series resistance (ESR) and very low equivalent series inductance (ESL). The system of claim 1, wherein the clock generation circuit is configured to operate intermittently to balance the voltage between the first group and the second group. The system of claim 1, wherein the clock generation circuit is configured to operate continuously to maintain a balanced voltage between the first group and the second group. A battery pack for balancing voltage between battery packs, comprising: a plurality of battery packs, including a first group and a second group, wherein the plurality of battery packs are electrically coupled in series, wherein each battery pack includes one or more batteries Wherein the battery pack includes a plurality of batteries, the plurality of batteries are electrically coupled in parallel; the first capacitor has a first end and a second end; and the second capacitor has a first end and a second end; a group switching device selectively coupling the first and second ends of the first capacitor to the first and second ends of the first group, and the first and second ends of the second group; a second set of switching devices selectively coupling the first and second ends of the second capacitor to the first and second ends of the first group, and the first and second portions of the second group a time-phase generating circuit that generates a clock signal having a substantially non-overlapping clock phase, including a first phase and a second phase; wherein the clock generating circuit is configured to: control the first group of switching devices such that The first and second ends of the first capacitor during the first phase Not coupled to the first The first and second ends of the set, and the first and second ends of the first capacitor are respectively coupled to the first and second ends of the second group during the second phase And controlling the second set of switching devices such that the first and second ends of the second capacitor are coupled to the first and second ends of the second group, respectively, during the first phase And during the second phase, the first and second ends of the second capacitor are respectively coupled to the first and second ends of the first group. The battery pack of claim 12, wherein the plurality of battery packs further comprise a third group electrically coupled in series with the first group and the second group; wherein the system additionally includes a first end and a third capacitor of the second end; and wherein the first set of switching devices and the clock generating circuit are configured to couple the first and second ends of the third capacitor respectively during the first phase Up to the first and second ends of the second group, and during the second phase, coupling the first and second ends of the third capacitor to the first of the third group And the second end. The battery pack of claim 12, wherein the clock generating circuit comprises a resonant LC oscillator circuit including at least one inductor and at least one capacitor. A method for balancing voltages between a plurality of battery packs, the battery packs comprising a first group and a second group electrically coupled in series, the method comprising: Using a clock generation circuit to generate a clock signal having substantially non-overlapping clock phases, including a first phase and a second phase; and applying the clock signals to the first group of switching devices such that the first phase And connecting the first and second ends of the first capacitor to the first and second ends of the first group, respectively, and during the second phase, the first capacitor The first and second ends are respectively coupled to the first and second ends of the second group; wherein applying the clock signal comprises applying the clock signal to the second group of switching devices, such that during the first phase The first and second ends of the second capacitor are respectively coupled to the first and second ends of the second group, and during the second phase, the first of the second capacitors And the second ends are respectively coupled to the first and second ends of the first group. The method of claim 15, wherein the plurality of battery packs further comprise a third group electrically coupled in series with the first group and the second group; and wherein the clock signals are applied to the first group A set of switching means includes ensuring that the first and second ends of the third capacitor are coupled to the first and second ends of the second set, respectively, during the first phase, and in the second phase The first and second ends of the third capacitor are coupled to the first and second ends of the third group, respectively. The method of claim 15, wherein the clock generating circuit comprises using a resonant LC oscillator circuit comprising at least one inductor and at least one capacitor.