TWI476616B - Estimation Method and Device of Initial Value for Simulation of DC Working Point - Google Patents

Description

Initial value guessing method and device for circuit DC operating point simulation

The present invention relates to a method and apparatus for solving a DC operating point of a circuit, and more particularly to an initial value guessing method and apparatus for simulating a DC operating point of a circuit.

Before the simulation of any form, such as transient or small signal analysis, the simulation program with Integrated Circuit Emphasis (HSPICE) first needs DC analysis to establish the DC bias point of the circuit. In order to establish a DC analysis point for a circuit, HSPICE must solve a set of nonlinear equations that describe the behavior of the circuit, which can be achieved by iterative generation using the Newton-Raphson Algorithm (N-R algorithm). The step of the N-R algorithm is to first give an appropriate initial value and then substitute it into the equation for iteration until the absolute value of the difference between the two successive solution vectors is less than a certain allowable error.

The N-R algorithm may have a problem of non-convergence under certain conditions, such as when the nonlinear equation is discontinuous, or the initial value is not close enough to the real solution. When the initial value is not close enough to the real solution, HSPICE will increase the number of iteration operations or re-calculate after reducing the step size. These steps increase the simulation time and the node voltage after these steps. Or the current may still not converge to cause the analog to be interrupted.

The simulation of the DC operating point of the circuit usually uses methods to solve nonlinear equations, such as Newton's method, the same wheel method, and so on. Convergence is the biggest problem encountered by these methods. If the initial guess value is far from the real working point, the number of iterations is large, the simulation time is long, and even the solution does not converge and fails. Conversely, if the initial guess is closer to the real working point, the number of iterations is less and the time taken for convergence is also shorter. Therefore, the choice of initial values is an important part of the process of solving nonlinear equations.

At present, there are two main methods for initial value guessing. One is that HSPICE's original working principle based on each active device is derived from the usual working state of the analog circuit. The initial value guess causes each active component to operate in the initial turn-on mode, assuming that the active components in the analog circuit operate in the initial turn-on mode, ie, the active components operate in a saturation region. This method is more suitable for the work of analog circuits. Because the DC operating point of the analog circuit generally allows each active device to operate in an open state (such as the MOS device operating in the saturation region). However, it is not suitable for digital circuits because active components in digital circuits generally operate in switching mode, that is, in the triode region. The DC operating point of many components is off. Therefore, by default, the initial guess that each active component works in the initial turn-on mode will be far from the true value, so the guessing method is not suitable for the initial value guess of the digital circuit.

Another initial guess is used in HSPICE RF (post-ported to HSPICE), which treats all active components (primarily BJT transistors and MOS transistors) as controlled switch logic. With switch simulation, it propagates the power supply excitation to the various nodes of the circuit with logic values, and then converts the obtained logic value into the corresponding voltage value as the initial value of the DC operating point of the circuit. In other words, based on the logic value propagation of the switching stage, it helps to determine the initial state of the partial digital circuit. This method has advantages for some pure digital circuits. However, not all digital circuits can propagate logic values in the switching mode of operation. Moreover, for analog circuits, the logic value is not close to its true operating point and does not apply to the initial value guess of the analog circuit.

Therefore, how to obtain appropriate initial values, which can reduce the computation time when HSPICE solves nonlinear equations, and how to obtain a more effective method has always been a concern of the industry.

The invention provides a method and a device for guessing an initial value of a DC operating point simulation of a circuit, which uses an identification technique to try to divide the analog and digital parts of the circuit, and determine the initial value of each part in different ways to obtain the effective circuit. The initial value. At the same time, the logic simulation of the initial value of the digital part is appropriately modified in the usual logic simulation so that the logical initial value of the digital partial node can be determined to the greatest extent. Traditional methods for solving nonlinear equations, such as the N-R algorithm, are used in analog circuits to find DC operating points. The DC operating point obtained in the digital circuit and the DC operating point obtained in the analog circuit are individually used as the initial guess value of the DC operating circuit to obtain the final solution of the integrated circuit. Since the initial guess values are obtained based on different circuit properties, which are closer to the true solution of the circuit, the convergence speed of the circuit simulator and the calculation time can be greatly increased.

An initial value guessing method for circuit DC operating point simulation according to an embodiment of the present invention includes the following steps: dividing a circuit to be simulated into a digital circuit and an analog circuit by a circuit identification technology or a graph recognition technology; and calculating a DC of the digital circuit by using logic simulation Working point; calculating the DC operating point of the analog circuit by solving the nonlinear equation; and combining the DC operating point of the digital circuit with the DC operating point of the analog circuit as the initial guess value of the circuit to be simulated.

An initial value guessing device for circuit DC operating point simulation according to an embodiment of the present invention includes: an identifying unit, a first calculating unit, a second calculating unit, and a reading unit. The identification unit divides the circuit to be simulated into a digital circuit and an analog circuit according to a circuit identification technology or a pattern recognition technology. The first computing unit calculates the DC operating point of the digital circuit using logic simulation. The second calculating unit calculates the DC operating point of the analog circuit by using a method of solving a nonlinear equation. The reading unit combines the DC operating point of the digital circuit with the DC operating point of the analog circuit as an initial guess for the circuit to be simulated.

The technical features of the present invention have been briefly described above, and the detailed description below will be better understood. Other technical features constituting the subject matter of the patent application of the present invention will be described below. It is to be understood by those of ordinary skill in the art that the present invention may be practiced as a It is to be understood by those of ordinary skill in the art that this invention is not limited to the scope of the invention.

In order to facilitate a better understanding of the spirit of the invention, the following description is further described in conjunction with the preferred embodiments of the invention. The direction of the invention discussed herein is an initial value guessing method and apparatus for circuit DC operating point simulation. In order to thoroughly understand the present invention, detailed steps and compositions will be set forth in the following description. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the art of circuit design. On the other hand, well-known components or steps are not described in detail to avoid unnecessarily limiting the invention. The preferred embodiments of the present invention are described in detail below, but the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited by the scope of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a flow chart for initial value guessing of a DC operating point simulation of a circuit in accordance with an embodiment of the present invention. In step 101, a circuit DC topology is first established to simplify the linear components and prepare for the next analysis. At step 102, a power supply node in the circuit is identified, as well as a dynamically controlled power supply node. These dynamically controlled power supply nodes tend to have non-linear characteristics and are not easy to converge, so it is necessary to identify and control them. At step 103, a pure metal field effect transistor network (MOS network) is established to simplify the circuit. At step 104, a digital logic circuit module is identified from the MOS network. The design of integrated circuits today is usually a hybrid circuit design, that is, the integrated circuit is a collection of analog circuits and digital circuits. This step consists in first identifying the properties of the circuit in the HSPICE analog circuit through circuit identification techniques, for example, the circuit is part of an analog circuit or part of a digital circuit. Next, the DC operating point of the circuit is solved in different ways depending on the properties of the circuit. At step 105, a network of digital logic circuit modules is built and placed in a logic simulator. In general, digital circuit simulation is very mature in logic-level simulation, and the algorithm complexity is not high. The method for solving the DC operating point of the digital circuit is to convert the digital circuit from the transmission stage circuit to the logic level circuit, and use the improved logic simulation technique to obtain the logic value of the digital circuit as the initial value of the DC operating point. The present invention further proposes an improved logic simulation technique which will be further described in the following examples. At step 106, the linear components of the unrecognized portion of the restoration circuit form an analog circuit module. The DC operating point of the analog circuit is solved by a node analysis method describing the behavior of the circuit, and then a set of nonlinear equations is obtained by the N-R algorithm to obtain the DC operating point of the analog circuit. At step 107, an independent power supply stimulus is established and initial propagation is performed. The above steps can be regarded as the identification phase and the preparation phase.

At step 108, it is determined whether the input stimulus of the digital module is determined? If the answer is yes, go to step 109, otherwise go to step 110. At step 109, a modified logic simulator is used to simulate the digital logic circuit module network. These modifications are designed to match the characteristics of the present invention simulation, minimizing the number of uncertain nodes, such as removing logic level simulations. Time delay technology and strictly abide by the digital circuit input and output, the latches (only two states), the nodes at both ends build the appropriate logic values, eliminate the oscillation circuit of the inverter ring, and identify and modify the dynamic circuit as a static digital circuit. (The source voltage has been determined) and a heuristic algorithm is used to determine how it works. At step 110, the analog circuit module is solved using loose tolerances. Since the present invention only requires a relatively reliable initial value, it is not necessary to directly find a precise DC operating point, so a looser tolerance can be used to increase the speed of execution. At step 111, is it judged that the boundary node value is stable? When the analog circuit and the digital circuit in the hybrid circuit have feedback to each other, the circuit simulator passes the multiple iterations, and after the boundary value thereof is stabilized, the stable solution is used as the initial guess value of the associated circuits. If the answer to step 111 is yes, then go to step 112, otherwise go to step 108. At step 112, the logic simulation results are read and converted to corresponding node voltage values. At step 113, the results are written to the HSPICE DC operating point initial guess array. Since the initial guess values are closer to the true solution of the circuit, the convergence speed of the circuit simulator and the calculation time can be greatly increased.

In order to enable those skilled in the art to practice the present disclosure through the teachings of the present embodiments, the flow of the method of the present invention will be further described below in conjunction with FIGS. 2 through 4.

2 is a flow chart of a modified logic simulator in accordance with an embodiment of the present invention. In step 201, the input excitation of the digital circuit module is placed in a propagation queue to prepare for the next analysis. At step 202, the logic simulation subroutine is invoked. At step 203, is it determined whether the logic simulation is successful? If the answer is yes, go to step 204, otherwise judge the simulation fails to exit. At step 204, the latch emulation subroutine is invoked. Because the latch has only two states, it can be preset to one of them. If not, change to another. Therefore, if the end node of the latch is found to be a logical "arbitrary value", a heuristic algorithm is used to determine the logical value of its end node. At step 205, is it determined whether the logic simulation is successful? If the answer is yes, proceed to step 206, otherwise it is determined that the simulation fails to exit. In step 206, all static memory (SRAM) modules are inspected, and the unsteady SRAM is set to the "01" state, and it is judged that the simulation is successfully exited. Since the presence of SRAM does not affect the DC operating point, the initial guess array for determining the DC operating point can circumvent such circuits to greatly increase the convergence speed of the circuit simulator and shorten the computation time.

3 is a flow chart of a logic simulation of an embodiment of the present invention. In step 301, it is determined whether the queue is empty? If the answer is yes, the simulation successfully exits normally, otherwise it proceeds to step 302. At step 302, a node N is sequentially taken from the queue. At step 303, each logical gate connected to node N is examined. At step 304, it is determined whether the logic gate is an inverter? If the answer is yes, go to step 307, otherwise go to step 305. Since the inverter complies with the single-input and single-out, the logic value is flipped, so if the output of the inverter is a determined logic value, its input value can also be obtained by logic simulation. In other words, the logic simulation used in this step can pass the output of some function modules to the input. At step 305, is it determined whether the input of the logic gate is connected to this node? If the answer is yes, then go to step 307, otherwise go to step 306. At step 306, it is determined whether the two-way 逻辑 of the logic gate is connected to the node? If the answer is yes, go to step 307, otherwise go back to step 301. The above steps can be regarded as the preparation phase.

At step 307, the logical value of the 埠 node of the logic gate is calculated. At step 308, each node M is viewed. At step 309, it is determined whether the logical value of the node M has changed. If the answer is yes, then go to step 310, otherwise go to step 312. At step 310, it is determined whether the node M changes from a non-determined state to a logical value (0 or 1)? If the answer is yes, proceed to step 311, otherwise the simulation fails to exit. The purpose of this step is to minimize the situation of the indeterminate state. At step 311, node M is added to the propagation queue. At step 312, it is determined whether all the nodes have been analyzed. If the answer is yes, then go to step 313, otherwise go back to step 308. At step 313, it is determined whether the logic gates connected to the node M are all analyzed. If the answer is yes, then go back to step 301, otherwise go back to step 303.

4 is a flow chart of a latch analog subroutine in accordance with an embodiment of the present invention. At step 401, the latch scan pointer is zero. At step 402, it is determined whether all the latches have been scanned? If the answer is yes, the simulation exits successfully, otherwise it proceeds to step 403. At step 403, the next latch is scanned. At step 404, it is determined whether the latch status is determined? If the answer is yes, then go back to step 402, otherwise go to step 405. At step 405, the latch is stored in the stack. At step 406, it is determined whether the stack is empty? If the answer is yes, the simulation fails to exit, otherwise it proceeds to step 407. At step 407, the latch L of the uppermost layer of the stack is taken out. At step 408, it is determined whether the latch L state is undetermined. If the answer is yes, then go to step 410, otherwise go to step 409. At step 409, it is determined whether the latch L "10" state has been tried? If the answer is yes, then go to step 406, otherwise go to step 411. At step 410, the latch is set to the "01" state. The above steps are all to reduce the instability of the latch as much as possible. At step 411, the latch is set to the "10" state. At step 412, the latch node is added to the logic analog propagation queue and the logic simulation subroutine is called. At step 413, it is determined whether the logic simulation is successful? If the answer is yes, then go back to step 402, otherwise go to step 414. At step 414, because the decision logic simulation fails, the node that must restore the change in the logical value caused by this simulation is the previous logical value. At step 415, the latch L is re-stored in the stack and proceeds to step 402.

Figure 5 is a diagram of an apparatus for guessing the initial value of a DC operating point simulation of a circuit in accordance with an embodiment of the present invention. The device 50 includes an identification unit 51, a first calculation unit 52, a second calculation unit 53, and a reading unit 54, which will be described in detail below.

The identification unit 51 divides the circuit to be simulated into a digital circuit and an analog circuit according to a circuit functional recognition technology or a pattern recognition technology. Circuit identification techniques can be found in L. Yang, C.-J. Richard Shi, "FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits", Technical report, UWEE, Jun 12, 2003, or U. Hubner, HT Vierhaus, "Partitioning and Analysis of Static Digital CMOS Circuits", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 16, NO. 11, NOVEMBER 1997, E., or M. Ohlrich, et al, "SubGemini: Identifying SubCircuits Using a Fast Subgraph Isomorphism Algorithm", 30th ACM/IEEE Design Automation Conference, 1993. As a method, it is not necessary to completely and accurately identify all digital circuit modules. Therefore, a method in which the complexity of the algorithm is low can be employed to ensure the efficiency of the method. The graph recognition technology, because of its high complexity, has little meaning for initial value guessing and can be used in digital circuit recognition that is difficult to identify or easily confused with analog circuits.

The first computing unit 52 calculates the DC operating point of the digital circuit using logic simulation. Digital circuit simulation is very mature in logic level simulation and the algorithm complexity is not high. However, in this method, there are mainly the following modifications:

1. As the initial value of the operating point, the time delay technique in the logic level simulation is not required and the digital circuit input and output are strictly observed. For example, in a logic-level simulation, the inverter follows the rules of single-input and single-out, logical value flipping. However, when applied to this method, if the output of the inverter is a determined logic value, its input value can also be obtained by logic simulation. That is, the logic simulation used in this method can pass the output of some functional modules to the input.

2. In a logic level simulation, a node to which a logical value cannot be transmitted is considered to be "arbitrary value". However, the logic values of some digital circuits can be "self-built". For example, the latch, because the latch has only two states, it can be preset to one of them, if not, then to another. If the nodes at both ends of the latch are not transferred from the stimulus to obtain a logical value, the appropriate logic value can be "built". The logic simulation process of the method detects each identified latch circuit after the initial simulation ends, and uses a heuristic algorithm to determine the logical value of its end node if its end node is a logical "arbitrary value".

3. Some digital circuits do not have a suitable DC operating point, such as an inverter circuit based on an inverter loop. The oscillating circuit is independent of the setting of the DC operating point and can therefore be rejected. After identifying the circuit of this type and determining the output node value, the method removes such circuit from the calculation of the DC operating point of the whole circuit to avoid the convergence failure of the method for solving the nonlinear equation because there is no stable operating point.

4. For dynamic digital circuits, ie the logic function of the circuit is clocked, in the normal logic level simulation, the state of all components in this part is uncertain due to the controlled clock being in the off state. The state uncertainty is one of the important reasons for the failure of the nonlinear equation method. Therefore, the method recognizes these dynamic circuits and uses the heuristic algorithm to determine the working state as a static digital circuit. Although this determined state may not be the true working state of the circuit, it is possible to use the transient analysis to return the circuit to its proper state after assisting in the DC operating point calculation.

The second calculating unit 53 calculates the DC operating point of the analog circuit by using a method of solving a nonlinear equation. For the analog circuit part, an open nonlinear solution with excitation and output is used to obtain the working point with a relatively loose deviation criterion.

The read unit 54 combines the DC operating point of the digital circuit with the DC operating point of the analog circuit as an initial guess for the circuit to be simulated. If the analog circuit part and the digital part have feedback, the respective calculations will make the value of the boundary node unstable. In this case, the boundary node values need to be stabilized under certain deviation criteria by a certain iteration.

Figure 6 is a further schematic diagram of an identification unit 51 in accordance with an embodiment of the present invention. The identification unit 51 includes a functional identification module 511 and a graphic recognition module 512. The functional identification module 511 identifies the position of the digital circuit and the analog circuit primarily via circuit-specific functionality and the aid of some tools (eg, layout versus schematic; LVS). The graphic recognition module 512 recognizes the position of the digital circuit and the analog circuit mainly through the help of circuit-specific graphics and some graphics matching tools. However, the above description is only illustrative, and the type of identification unit known to those skilled in the art is still within the scope of the invention.

FIG. 7 is a further schematic diagram of a first computing unit 52 in accordance with an embodiment of the present invention. The first computing unit 52 includes a bidirectional propagation module 521, a latch management module 522, a filter module 523, and a clock management module 524. The bidirectional propagation module 521 allows signals from some functional modules to be passed from the output to the input. For example, in a logic level simulation, the inverter complies with the rules of single-input and single-out, logic value flipping, so if the output of the inverter is The determined logical value, then its input value can also be obtained by logic simulation. At the same time, the two-way propagation module 521 removes the time delay in the logic level simulation to speed up the simulation execution. The latch management module 522 is responsible for the logic value of the self-built latch, and after detecting the end of the initial simulation, each identified latch circuit is detected, and if its end node is a logical "arbitrary value", it is used. The heuristic algorithm determines the logical value of its end node. The filter module 523 is mainly used for rejecting digital circuits that are independent of the DC operating point, such as an oscillating circuit of the inverter ring, to speed up the simulation execution and avoid the probability of failure of the nonlinear equation convergence. The clock management module 524 converts the logic function clocked circuit into a static digital circuit, and uses a heuristic algorithm to determine its working state. Although the determined state may not be the real working state of the circuit, it can help the DC work. After the point is calculated, the transient analysis is used to return the circuit to its proper working condition.

Modern integrated circuits are usually circuits that are designed with digital and analog hybrids. The solution is to divide the circuit to be simulated into a digital circuit part and an analog circuit part by circuit identification technology. In the digital circuit portion, the method utilizes circuit identification techniques in an attempt to convert a portion of the digital circuit from a transmission stage to a logic gate stage circuit. The operating state of a digital circuit can generally be determined by logic simulation in the case of a fixed excitation. The digital circuit section uses an improved logic simulation technique to calculate its DC operating point under a fixed excitation, ie, using a modified logic simulation to determine the logic value of the digital circuit portion. The rest of the circuit is used as an analog circuit to find its DC operating point using a general solution to the nonlinear equation. If there is feedback between the analog circuit and the digital circuit, the boundary node is stabilized by multiple iterations. The analog circuit node value plus the DC operating point of the digital circuit is combined to solve the initial guess value of the DC operating point of the entire circuit, and then the true DC operating point of the entire circuit is obtained. The initial guess value obtained by dividing the circuit function can be closer to the real working point of the whole circuit, thus improving the speed and convergence of the whole circuit solution.

The technical contents and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as being limited by the scope of the invention, and the invention is intended to

51. . . Identification unit

52. . . First computing unit

53. . . Second computing unit

54. . . Reading unit

101~113. . . step

201~206. . . step

301~313. . . step

401~415. . . step

511. . . Functional identification module

512. . . Graphic recognition module

521. . . Two-way propagation module

522. . . Latch management module

523. . . Filter module

524. . . Clock management module

1 is a flow chart of initial value guessing of a DC operating point simulation of a circuit according to an embodiment of the present invention;

2 is a flow chart of a modified logic simulator in accordance with an embodiment of the present invention;

3 is a flow chart of a logic simulation of an embodiment of the present invention;

4 is a flow chart of a latch analog subroutine according to an embodiment of the present invention;

5 is a diagram of an apparatus for guessing an initial value of a DC operating point simulation of a circuit according to an embodiment of the present invention;

Figure 6 is a further schematic diagram of an identification unit in accordance with an embodiment of the present invention; and

Figure 7 is a further schematic diagram of a first computing unit in accordance with an embodiment of the present invention.

101~113. . . step

Claims (20)

An initial value guessing method for circuit DC operating point simulation includes the following steps: dividing a circuit to be simulated into a digital circuit and an analog circuit by a circuit identification technology or a graph recognition technology; calculating a DC working point of the digital circuit by using logic simulation; The method of the nonlinear equation calculates the DC operating point of the analog circuit; and combines the DC operating point of the digital circuit with the DC operating point of the analog circuit as the initial guess value of the circuit to be simulated. The method of claim 1, wherein the circuit identification technique converts the transmission stage of the digital circuit to a logic gate circuit. According to the method of claim 1, wherein the logic simulation is performed to determine the logic value of the digital circuit in a fixed excitation manner. According to the method of claim 1, wherein if the digital circuit and the analog circuit have mutual feedback, the boundary value is stabilized by multiple iterations. The method of claim 1, wherein the factor of the time delay of the digital circuit is ignored when performing the logic simulation. The method of claim 1, wherein if the output of a module of the digital circuit is a determined logical value, the input value of the module is obtained by using a logic simulation. The method of claim 1, wherein when the logic simulation is performed, when the latch of the digital circuit is determined to be an arbitrary value, the logical value of the end node of the latch is determined using a spontaneous algorithm. The method of claim 1, wherein if the digit circuit is identified as having an inverter loop, the output node value of the inverter loop is determined during logic simulation, and the inverter loop is eliminated. The method of claim 1, wherein if the digital circuit is identified as having a clocked logic circuit, it is converted to a clock circuit that is not clocked during logic simulation, and is calculated using a spontaneous algorithm. Working status. The method of claim 1 further comprising the step of using a looser deviation criterion to calculate a DC operating point of the analog circuit. A device for guessing an initial value of a DC operating point simulation of a circuit, comprising: an identification unit, the circuit to be simulated according to a circuit identification technology or a pattern recognition technology is divided into a digital circuit and an analog circuit; a first computing unit, using logic Simulating and calculating a DC operating point of the digital circuit; a second calculating unit calculating a DC operating point of the analog circuit by solving a nonlinear equation; and a reading unit combining the DC operating point of the digital circuit and the analog circuit The DC operating point is used as the initial guess for the circuit to be simulated. The device of claim 11, wherein the first computing unit converts the transmission stage of the digital circuit to a logic gate circuit. The apparatus of claim 11, wherein the first computing unit determines the logical value of the digital circuit in a fixed excitation manner. The device of claim 11, wherein if the first computing unit and the second computing unit have feedback between each other, the boundary value is stabilized by multiple iterations. The device of claim 11, wherein the first computing unit ignores a factor of time delay. The device of claim 11, wherein if the first computing unit determines that the output of a module of the digital circuit is a determined logical value, the input value of the module is determined by logic simulation. The apparatus according to claim 11, wherein if the first calculating unit determines that the latch of the digit circuit is an arbitrary value, determining a logical value of an end node of the latch using a spontaneous algorithm. The device according to claim 11, wherein if the first calculating unit recognizes that the digital circuit has an inverter ring, the output node value of the inverter ring is determined after logic simulation, and the reverser is eliminated ring. The apparatus of claim 11, wherein if the first computing unit recognizes that the digital circuit has a clocked logic circuit, converting it to a logic circuit that is not clocked during logic simulation, and using the spontaneous The algorithm calculates its working state. The apparatus of claim 11, wherein the second computing unit uses a looser deviation criterion to calculate a DC operating point of the analog circuit.