TWI475809B - Successive approximation register type capacitance to digital converter - Google Patents

Description

Successive comparison type capacitance value to digital converter

The present invention relates to a capacitance-to-digital converter, and more particularly to a detection circuit for measuring an external capacitance value, and has high-speed conversion, low power consumption, and fully linear quantization characteristics.

With the popularization of electronic technology, the electronic device has a high interaction with the user and becomes a necessary function of today's electronic products. The technology that directly provides human-computer interaction is the first to push the touch panel technology.

Taking a touch device as an example, the touch device can be divided into several categories, including a resistive touch device, a capacitive touch device, and a projection touch device. Take a capacitive touch device as an example. The conventional capacitive touch device includes an integrator or an oscillator connected to detect a change in capacitance of a plurality of touch capacitors. When measuring the capacitance with an integrator or oscillator, there is a disadvantage of high power consumption (not suitable for handheld electronic devices) or low speed (slow detection speed and unresponsiveness), which is extremely inconsistent in actual product design and application. Convenience.

In addition, there is currently a charge-redistribution type capacitor digital converter architecture (proposed in 2007), the main method of which is the capacitance comparison method (in 1997, it was applied to the charge redistribution type A/D and D/A converter test). ), the main conversion step is to compare the capacitor bits after the capacitor is sampled, but during the conversion, the capacitor to be tested cannot be continuously changed due to the inevitable change of the capacitor to be tested, resulting in conversion error. Will continue to expand, and this error will be related to the power supply, causing the capacitance measurement results to change due to different power supply and can not compensate for the dilemma, so in order to reduce this effect, it limits the minimum speed of operation, and can not reduce the consumption in standby mode. Electricity.

The main object of the present invention is to provide a successive comparison type capacitance value to digital converter for converting the capacitance value of the capacitance to be tested to a digital value, and sequentially comparing the capacitance values to the digital converter including the capacitor array and the capacitor to be tested. Switch, stray capacitance (optional), comparator, capacitor switch array, control module, and conversion result register, wherein the capacitor array includes a plurality of comparison capacitors of different capacitance values, and the capacitor switch array includes a plurality of capacitors Switches, and each capacitor on relationship is used to control the corresponding comparison capacitor.

The comparator compares the voltage from the capacitor and the capacitor switch array to be tested, and generates a digital bit signal, and is received by the control module and performs a successive comparison operation, according to the digital bit signal to control the capacitance switch and the capacitor switch array to be tested. The capacitors to be tested and the capacitor array are respectively connected to the first or second voltage, and the appropriate comparison capacitors in the capacitor array are selected to generate an output signal. The conversion result register receives and stores the output signal of the control module as the corresponding digital value of the capacitance value of the capacitance to be tested.

The invention further includes a comparator switch across the input and output of the comparator for turning the comparator on or off.

The successive comparison operation performed by the control module includes a first operation and a second operation, wherein the first operation is to turn off the comparison operation of the comparator and perform initial balance voltage setting of the comparator, and control the capacitance switch to be tested to measure the capacitance to be tested. The other end is connected to the second voltage, and controls the capacitor switch array to connect the second end of the capacitor array to the first voltage to implement the sampling function; and the second operation turns on the comparator comparison operation to control the capacitance switch to be tested The other end of the capacitor to be tested is connected to the first voltage, and the capacitor switch array is controlled to connect the second end of the capacitor array to the second voltage, thereby implementing a comparison function.

The invention can implement the sampling function before performing the comparison function of each bit signal conversion, and compares immediately after sampling, thereby minimizing the error, thereby reducing the minimum operating speed and reducing the minimum in the standby mode. Power consumption.

The embodiments of the present invention will be described in more detail below with reference to the drawings and the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

Referring to the first figure, the present invention sequentially compares a capacitance value to a system diagram of a digital converter. As shown in the first figure, the successive comparison type capacitance value to digital converter of the present invention is used for converting the capacitance value of the capacitance C1 to be measured to a digital value, and includes the capacitor array 10, the capacitance switch 20 to be tested, and the stray capacitance. C3, comparator 30, capacitor switch array 40, control module 50, and conversion result register 60.

The capacitor array 10 has a first end N1 and a second end N2, and the first end N1 is connected to one end of the capacitor C1 to be tested, and the capacitor array 20 includes a plurality of comparison capacitors C2N having different capacitance values, and each comparison capacitor C2N One end is connected to the first end N1. The capacitance of the comparison capacitor C2N can be 2 ^N-1 CR, where N is a positive integer and CR is the capacitance of the standard reference capacitor.

The capacitor switch 20 to be tested controls the other end of the capacitor C1 to be connected to be connected to the first voltage V1 or the second voltage V2, wherein the first voltage V1 and the second voltage V2 are externally supplied or by the voltage generating unit of the present invention (in the figure) Not shown), and the first voltage V1 is not equal to the second voltage V2, that is, the first voltage V1 is greater than the second voltage V2, or the first voltage V1 is less than the second voltage V2. The stray capacitance C3 is connected across the first end N1 of the capacitor array 10 and the third voltage V3.

Please refer to the second figure, the schematic diagram of the comparator in the first figure.

The comparator 30 has an input end and an output end, and the input end is connected to the first end N1 of the capacitor array 10, wherein the voltage on the input terminal is the input voltage VIN. The present invention further includes a comparator switch SSH across the input and output of the comparator 30 for enabling comparison or shutdown and operation of the comparator's initial balanced voltage setting comparator 30, while the comparator 30 is operable during comparison The output voltage VO is generated as a digital bit signal and transmitted to the output.

It is to be noted that the comparator 30 can also use a differential input type comparator as shown in the third figure. For clarity of explanation, the comparator in the second diagram will be taken as an example to explain the features of the present invention.

The capacitor switch array 40 controls the second end N2 of the capacitor array 10 to be connected to the first voltage V1 or the second voltage V2, and the capacitor switch array 40 includes a plurality of capacitor switches (not shown), and each capacitor on relationship is used. Control the corresponding comparison capacitor C2N.

The control module 50 receives the output voltage VO generated by the comparator 30, and controls each of the capacitive switch 20 and the capacitive switch array 40 according to the output voltage VO, thereby implementing the first operation and the second operation. The operations are compared successively and an output signal is generated. The conversion result register 60 receives and stores the output signal of the control module 50 as the corresponding digital value of the capacitance value of the capacitor C1 to be tested.

The first operation may be referred to as a sampling operation, as shown in the fourth figure, including: controlling the comparator switch to short the input and output of the comparator 30, thereby turning off the comparison operation of the comparator 30; controlling the test to be tested The capacitor switch 20 connects the other end of the capacitor C1 to be tested to the second voltage V2; and controls the capacitor switch array 40 to connect the second terminal N2 of the capacitor array 10 to the first voltage V1, thereby implementing a sampling function or a capacitor Charging function.

At this time, since the input terminal and the output terminal of the comparator 30 are short-circuited, the input voltage VIN of the comparator 30 can be expressed as: VIN=VT, where VT is the transition point voltage of the comparator 30, and is to be The terminal voltage VC1 of the capacitance C1 is V1-VT, the terminal voltage VC1 of the comparison capacitor C2N is VT-V2, and the terminal voltage VC1 of the stray capacitance C3 is VT-V3.

The second operation may be referred to as a comparison operation, as shown in the fifth figure, including: controlling the comparator switch to make the input end and the output end of the comparator 30 open or open; controlling the capacitance switch to be tested and the capacitance to be tested The other end of C1 is connected to the first voltage V1; and the capacitor switch array 40 is controlled to connect the second terminal N2 of the capacitor array 10 to the second voltage V2, thereby implementing a comparison function.

At this time, the input terminal and the output terminal of the comparator 30 are open circuits, so the terminal voltage VC1 of the capacitor C1 to be tested can be expressed as:

VC1=(V1-VT)-(V2-V1)*(C2+C3)/(C1+C2+C3)-(V1-V2)*C2/(C1+C2+C3),

And the input voltage VIN can be expressed as:

VIN=V2-VC1=VT-(V1-V2)*(C1-C2)/(C1+C2+C3).

If it is assumed that the first voltage V1 is greater than the second voltage V2 in this embodiment, when the input voltage VIN is less than the transition point voltage VT, VIN<VT, indicating that the capacitance of the capacitor C1 to be tested is greater than the comparison capacitor C2N (C2=C2N). The capacitance value is such that the output voltage of the comparator 30 is VO=1, that is, the corresponding bit value of the digital value of the capacitor C1 to be tested is 1; and when the input voltage VIN is greater than the transition point voltage VT, VIN>VT, indicating The capacitance value of the capacitor C1 to be tested is smaller than the capacitance value of the comparison capacitor C2N, so the output voltage VO=0 of the comparator 30, that is, the corresponding bit value of the digit value of the capacitor C1 to be tested is zero. The expression of VIN also knows that the stray capacitance C3 has nothing to do with the comparison of VIN. Therefore, when the capacitor array in C2N has capacitance and does not participate in the comparison, it is only necessary to connect any fixed voltage in the sampling and comparison period.

Meanwhile, when the capacitance value of the capacitor C1 to be tested is greater than the capacitance value of the comparison capacitor C2N, the control module 50 adds the current bit comparison result to the next bit to achieve another comparison capacitor C2N of a larger capacitance value. For the next comparison operation, when the capacitance value of the capacitor C1 to be tested is smaller than the capacitance value of the comparison capacitor C2N, the control module 50 does not add the current bit comparison result to the next bit comparison to achieve the reduction capacitance. Another comparison capacitor C2N for the next comparison operation. Therefore, a binary search method can be implemented to determine the entire digit value of the capacitor C1 to be tested, that is, to sequentially find all the bit values of the digit value sequentially.

Therefore, in the successive comparison type capacitance value to digital converter of the present invention, the conversion order is sampling according to 2 ^N-1 CR capacitance and compared to the sampling of the CR capacitance and comparing the order, which is performed every bit conversion. Sampling action to reduce errors caused by the inability to perform sample hold of the capacitor under test.

The invention is characterized in that the sampling function can be realized before the comparison function of each bit signal conversion, and the comparison is performed immediately after sampling, thereby reducing the error to a minimum, thereby reducing the minimum operation speed and reducing the standby. The lowest power consumption in the mode.

The above is only a preferred embodiment for explaining the present invention, and is not intended to limit the present invention in any way, and any modifications or alterations to the present invention made in the spirit of the same invention. All should still be included in the scope of the intention of the present invention.

10. . . Capacitor array

20. . . Capacitor to be tested

30. . . Comparators

40. . . Capacitor switch array

50. . . Control module

60. . . Conversion result register

C1. . . Capacitance to be tested

C2N. . . Comparison capacitor

C3. . . Stray capacitance

N1. . . First end

N2. . . Second end

SSH. . . Comparator switch

V1. . . First voltage

V2. . . Second voltage

V3. . . Third voltage

VIN. . . Input voltage

VO. . . The output voltage

The first figure is a schematic diagram of the system of the successive comparison type capacitance value to digital converter of the present invention.

The second figure is a schematic diagram of the comparator in the first figure.

The third figure is a schematic diagram of another example of the comparator in the first figure.

The fourth figure is a schematic diagram of the first operational steps of the second figure.

The fifth figure is a schematic diagram of the second operation step of the second figure.

10. . . Capacitor array

20. . . Capacitor to be tested

30. . . Comparators

40. . . Capacitor switch array

50. . . Control module

60. . . Conversion result register

C1. . . Capacitance to be tested

C2N. . . Comparison capacitor

C3. . . Stray capacitance

N1. . . First end

N2. . . Second end

V1. . . First voltage

V2. . . Second voltage

V3. . . Third voltage

VIN. . . Input voltage

VO. . . The output voltage

Claims (3)

A successive comparison type capacitance value to digital converter for converting a capacitance value of a capacitance to be measured to a digit value by successive comparison, wherein the successive comparison type capacitance value to digital converter comprises: a capacitor array having a first end and a second end, wherein the first end is connected to one end of the capacitor to be tested, and the capacitor array comprises a plurality of comparison capacitors having different capacitance values, and one end of each comparison capacitor is connected to a first end of the capacitor array; a capacitor switch to be connected to connect another end of the capacitor to be tested to a first voltage or a second voltage; and a comparator having at least one input end and one output end And an input terminal is connected to the first end of the capacitor array, thereby comparing an input voltage and a reference voltage on the input terminal, and generating a digit bit signal and transmitting to the output terminal; a comparator switch Is used to set an initial comparison balance voltage of the comparator; a capacitor switch array is configured to connect the second end of the capacitor array to the first voltage or the second voltage, and the switch array package a plurality of capacitive switches, wherein each capacitive open relationship is used to control a corresponding comparative capacitor in the capacitor array; a control module receives the digital bit signal generated by the comparator, and according to the digital bit signal Controlling the capacitance switch to be tested and each of the capacitive switch arrays to perform a successive comparison operation, and the successive comparison operations include a first operation and a second operation to generate an output signal; and a conversion a result register receives the output signal of the control module as a corresponding digital value of the capacitance value of the capacitance to be tested, and stores the same; wherein the first operation system controls the comparator switch to make the input of the comparator The terminal and the output terminal are short-circuited, the capacitor switch to be tested is controlled to connect the other end of the capacitor to be tested to the second voltage, and the capacitor switch array is controlled to connect the second end of the capacitor array to the first Voltage, and the second operation system controls the comparator switch to make the input end and the output end of the comparator open or open, and controls the capacitor switch to be tested to be tested The other end of the container is connected to the first voltage, and controlling the switch array and the second capacitor terminal of the capacitor array is connected to the second voltage. The successive comparison type capacitance value to the digital converter according to the first aspect of the patent application, wherein the capacitance value of each capacitor in the capacitor array is 2 ^N-1 CR, and N is a positive integer, and CR is The capacitance value of a standard reference capacitor. The successive comparison type capacitance value to digital converter according to claim 1 of the patent application scope, wherein the conversion order of the converter is sampling according to 2 ^N-1 CR capacitance and comparing to sampling of the CR capacitor and comparing the order, each of which The sampling operation is performed during one-bit conversion to reduce the error caused by the inability to perform sampling and holding of the measured capacitance.