TWI475569B - System, method, and computer program product for delaying an operation that reduces a lifetime of memory - Google Patents

Description

System, method and computer program product for delaying memory life reduction operation

The specific embodiment of the invention relates to memory, and more particularly to memory having a life limit.

Memory is the most limited aspect of the performance of modern enterprise computer computing systems. One of the memory-restricted layers is because many types of memory have lifetime limitations. For example, the lifetime of non-volatile memory such as flash memory, although small, is reduced each time it is erased and rewritten. After thousands of erasures and rewrites, the flash memory may become increasingly unreliable.

Therefore, depending on the type of use (eg, mild or severe), the lifetime of the flash memory may vary considerably, which can cause problems at various levels. For example, flash memory manufacturers typically offer a limited warranty for a period of time. This warranty may be sufficient for the mild to normal use of flash memory, but for heavy use situations (for example, in enterprise applications, etc.), it may be necessary to return and replace the flash memory.

This situation can seriously affect the profitability of flash memory manufacturers. In particular, there is a need to continuously replace warranty flash memory for heavy-duty customers, but it can significantly erode profits from sales to light-to-usage customers. Therefore, it is necessary to address these and/or other problems associated with prior art.

The invention is a system, method and computer program product for delaying memory life reduction operations. When used, at least one level related to the life of the memory is identified. In order to achieve this goal, at least according to this aspect, an operation for delaying the life of the memory is proposed.

Depending on the specific embodiment to be described, various memory life reduction operations can be controlled for extended life. In the present description, such operations may be write operations, erase operations, program operations, and/or any other operations that reduce the aforementioned lifetime.

1 illustrates a method 100 of delaying memory life reduction operations, in accordance with an embodiment. As shown, at least one level related to the lifetime of the memory is identified, see operation 102.

In the present description, the memory lifetime may include any duration of the degree to which the memory exhibits the required utility. For example, in various embodiments, the lifetime may include, but is not limited to, a desired life, actual life, estimated life, and the like. Furthermore, the degree of practicability may refer to any practicability-related parameter, such as the percentage of components (eg, chunks, batteries, etc.) that are still operational, the reliability of the memory or component, and/or any other utility-related parameter.

Additionally, in this description, the life-relevant aspects identified in operation 102 are in various embodiments, which may include a period of time, a memory lifetime reduction operation rate, a memory operation life reduction total number of allowed operations, and Life duration, etc. Moreover, in one illustrative embodiment, the total number of operations allowed in the foregoing, as well as the selected or expected life. In the case, the maximum average operating rate in the number of operations per unit of time can be directly calculated. Of course, the exemplification of this elaboration is for illustrative purposes only, as any other aspect of life is absolutely identifiable, and the reasons for it will soon be clear.

In order to achieve this goal, at least according to this aspect, an operation for delaying the life of the memory is proposed, as shown in operation 104. The delay can therefore be performed in any manner, i.e., at least a portion of the functionality of the memory life level identified in operation 102. In the present description, the aforementioned operational delay is considered to be included in the case of only partial operational delays. For example, in the case of operations that may include multiple components, such delays may apply to one or more (or all) of the components in the operation.

In a specific embodiment, the operation can be delayed by delaying an instruction to initiate a operation. For example, the execution of this instruction can be delayed in response to an acknowledgment of a write or erase instruction. Of course, in other embodiments, the operation itself may be delayed only. With this design, such one or more delays can reduce the life of the memory, which can reduce the life reduction effect, at least partially reducing the effect.

More information on the various available architectures and functions will now be presented, and each user may or may not implement the aforementioned architecture as needed. For example, a number of different techniques can be used to manage the delay in a variety of different ways, as exemplified below. It is important to note that the information presented below is for illustrative purposes and should not be construed as limiting in any way, and any of the following features can be selected for use with other features described above.

2 shows a technique 200 for delaying memory life reduction operations in accordance with another embodiment. The present technique 200 is an implementation option that implements the method 100 of FIG. Of course, the technology 200 can be implemented in any desired environment. It should be noted that the foregoing definitions are applicable to this description. .

As shown, the technique 200 has a total number of operations 202 that take into account the minimum usefulness of memory presentation and the minimum expected lifetime 204. From this data point of view, the maximum average operating rate 206 for achieving the minimum expected life of 204 can be calculated.

In use, the number of life reduction operations can be monitored over time. If at any time the number of such operations exceeds the maximum average operating rate 206, as indicated, any excess operation (which causes the excess ratio) may be calculated by the amount, and by a predetermined amount of time, or adjustatively Delayed based on previous or predicted life reduction operating rates. Such a predetermined amount of time, in one embodiment, may be a period of time that does not exceed a maximum average operating rate of 206.

In various embodiments, it may be determined based on various factors that the operation will be subject to delay (and the length of the delay itself). For example, in one embodiment, the delay may be based on the application that initiated the operation. In such a specific embodiment, operations initiated by applications with lower priority order may be subject to delay, while operations initiated by applications with higher priority are not necessarily subject to delay (when possible) .

Of course, other specific embodiments for controlling the delay between operations in a standalone application manner can be considered. For example, the delay can be applied to a specific type All operations (for example, erase operations, etc.) regardless of the original application. In addition, specific embodiments using a hybrid approach are also contemplated.

Moreover, specific embodiments of delayed operation that may be considered include operations or modes of operation that result in an abnormally reduced life. In a specific embodiment, only these modes will be delayed. For example, in the case where a virus or rough application mode of operation can be detected, only operations from these modes are delayed.

3 illustrates an operation of a time interval based technology 300 that can delay memory life reduction, in accordance with yet another embodiment. As an option, implementing the inventive technology 300 can implement the method 100 of FIG. 1 and/or further implement the techniques 200 of FIG. Of course, the technique 300 can be implemented in any desired environment, and it should also be noted that the foregoing definitions are applicable to this description.

Similar to the technique of FIG. 2, technique 300 has a total number of operations 302 that are considered to result in minimal memory utility and a minimum expected lifetime of 304. From this data point of view, the maximum average operating rate 306 that achieves the minimum expected life of 304 can be calculated. In use, the number of life reduction operations can be monitored over time.

If at any time the number of such operations exceeds the maximum average operating rate 206, as indicated, any excess operation does not have to be delayed in an unconditional manner (similar to Figure 2, technique 200). Conversely, such excess operation can be conditionally delayed depending on the time interval at which the operation is initiated. For example, such time intervals may include, but are not limited to, time of day, one day of the week, one month of the year, and the like. In other embodiments, the time interval can be suitably dynamically adjusted to the optimal period. For example, this fit and dynamic tuning The whole may depend on the frequency histogram of the sub-interval life reduction operation at the time interval.

For example, if an excessive amount of operations is found on Monday, Tuesday, Wednesday, Thursday, etc. by the above method, it is possible to confirm (for example, expected) that the number of operations during subsequent Fridays, Saturdays, and Sundays is small. Therefore, except for unconditionally delaying such excess operation, it can also be performed immediately without exceeding the possible average operating rate of the maximum average operating rate 206 (sampled in one week). Of course, if these can't solve the reality, there may be some delay in the next week. Although the above-described examples are based on the date conditions within one week, it is also possible to consider a larger-scale use memory variation embodiment in a few weeks in the other month, months in a year, and the like.

In other embodiments, the interval conditional delay is not necessarily required, but rather depends on the past usage of the memory, and/or even the intended use of the memory. In such a specific embodiment, in order to predict future usage, past data can be utilized to perform any required statistical analysis to more accurately identify delay excess operations that do not occur.

4 illustrates an integrated technology 400 that can delay memory life reduction operations in accordance with another embodiment. As an option, technique 400 can be implemented to implement method 100 of FIG. 1 and/or further implement techniques 200 and 300 of FIGS. 2-3. Of course, the technology 400 can also be implemented in any desired environment. It should also be noted that the foregoing definitions may apply to this description.

Similar to the foregoing techniques, the technique 400 has operations that take into account the least practicality of memory presentation and the minimum expected life of the memory 404. The total number is 402. From this data point of view, the maximum average operating rate 406 that achieves a minimum expected life of 404 can be calculated. When in use, the number of life reduction operations can be monitored over time.

If, at any time, the number of such operations exceeds the maximum average operating rate 406, as shown (see 408), any excess operations do not have to be unconditionally delayed (similar to Figure 2, technique 200). Conversely, such excess operation can be conditionally delayed depending on the integral function reflecting the memory usage. In particular, based on the ongoing process, the deviation integral between the lifetime reduction timeout operation overall rate and the maximum average operation rate 406 can be calculated. Therefore, if the integration indicates that such an operation may exceed the maximum average operating rate 406, the aforementioned delay does not have to occur.

5 illustrates a system 500 for delaying memory life reduction operations when a desired lifetime duration exceeds an estimated lifetime duration, in accordance with another embodiment. As an option, system 500 can be implemented to implement the method 100 of FIG. 1 and/or further selectively incorporate the techniques of FIGS. 2-4. Of course, system 500 can be used in any desired environment.

As shown, a storage system 503 comprised of a plurality of storage devices 530, 540 is included. At least one storage bus 502 is coupled with at least one controller 511 and at least one computer 501. In various embodiments, the storage bus 502 can include, but is not limited to, a Serial Advanced Addition Technology (SATA) bus, a Serial Attached Small Computer System Interface (SAS) bus, a Fibre Channel bus, and a memory bus interface. , flash memory bus, NAND flash memory bus, integrated drive electronic interface (IDE) bus, advanced add-on technology (ATA) bus, consumer electronics (CE) convergence Row, universal serial bus (USB), smart card bus, multimedia card (MMC) bus, etc. Thus, the controller 511 can be paired with one of a system (eg, computer 501) and a second storage device (eg, at least storage devices 530, 540). Additionally, at least one device 510 associated with the storage devices 530, 540 for extending the life of the memory may be included.

As shown, the device 510 includes a controller 511 coupled to the storage devices 530, 540 via a plurality of corresponding bus bars 521, 522. The controller 511 uses a plurality of bus bars 521, 522 to control and exchange data with the plurality of storage devices 530, 540 to execute instructions received from the computer 501 through the storage bus bar 502. The storage devices 530, 540 each include at least one module or block 531, 532, 533, 541, 542, 543 for storing data. Additionally, at least a portion of the aforementioned instructions are life reduction instructions that adversely affect at least one of the modules or blocks 531, 532, 533, 541, 542, 543. In use, although there is such a life reduction command, device 510 can be used to extend the life of storage devices 530, 540.

To accomplish this, the controller 511 is coupled to the life predictor module 514 via a corresponding bus bar 512. The device 510 also includes a time module 517 coupled to the life predictor module 514 via the bus bar 518 to provide the current time. In use, the life predictor module 514 receives instructions from the computer 501 to communicate with the controller 511 via the storage bus 502. In addition, the life predictor module 514 calculates the estimated life when executing the received command through the bus bar 512.

Referring to FIG. 5 , the life predictor module 514 is connected to the adjustment module 516 through a bus bar 515 . Life Estimator Module 514 uses sink The flow is routed to pass the life expectancy command currently executed by controller 511 to adjustment module 516. The currently executed instructions are the same as received from the life prediction module 514 through the bus 512 in a particular embodiment, even as received from the controller 511 of the computer 501 via the storage bus 502.

The current time module 517 can also be connected to the adjustment module 516 via the bus bar 518. Therefore, the current time obtained by the current time module 517 can be passed to the adjustment module 516. In one embodiment, the current time module 517 can be implemented, for example, in a simple calculator increment mode at a fixed time interval.

The adjustment module 516 can still be connected to the required life module 520 through the bus bar 519, and connected to the controller 511 through the bus bar 513. In use, the desired life module 520 can be adjusted to store the desired life. With this design, the adjustment module 516 can be configured to communicate information to the controller 511 via the bus bar 513 to instruct the controller 511 to delay the current instruction execution.

In one embodiment, the adjustment module 516 of the device 510 can delay the execution of the current command until the end of life execution, such that the estimated lifetime is longer or the same as the required life stored in the desired life module 520. . The function of the adjustment module 516, in a specific embodiment, if the estimated lifetime is received via the bus 515, the delay signal can be simply provided to the shorter than the required lifetime received via the bus 519. Controller 511.

In another embodiment, the functions of the controller 511, the life predictor module 514, and the adjustment module 516 are applicable to a group of predetermined The instruction received in the time interval. This arrangement allows the system 500 to meet the required lifespan without unnecessarily adjusting other short bursts that would result in a life reduction instruction. By selecting time intervals, for example, at one-day intervals, this technique allows system 500 to provide higher instantaneous performance for life-reducing commands because during certain periods of the day (eg, nighttime), the average life-deficiency command frequency is reduced. In contrast, some time intervals may have life-reducing instructions that reduce frequency.

In an alternative embodiment, coherence can be maintained over time. As an example of a coherent method, if the life reduction instruction A is delayed, all instructions that rely on the data A or the value obtained by executing the instruction A (whether or not the life is reduced) are delayed.

In another embodiment, the time may be replaced with various different time approximations, such as disk boot time. In another embodiment, the computer 501, a RAID controller, and/or other devices may provide additional information to increase the accuracy of the tracking time. Thus, when one or more of the storage devices 530, 540 are turned off, the time counter will not be timed. Because the actual time is still running, it may unnecessarily reduce performance. In such an arrangement, computer 501, software, and/or controller can provide time information regarding when system 500 is turned off to address such issues.

In another embodiment, system 500 can configure internal storage redundancy functions to reduce cost and improve performance. In such a particular embodiment, the data is moved between individual storage devices 530, 540 based on any level associated with lifetime (e.g., reference to Figure 1 operation 102, etc.). For example, in one case may involve a first storage device 530 that includes a set and a second storage Device 540 data is more frequently overwritten. In this case, after a predetermined amount of time, the data can be moved from the first storage device 530 to the second storage device 540, and thereafter the first storage device 530 or one or more blocks/modules 531, 532, 533 Can be used to store less frequently written data or not used anymore.

For this purpose, the storage device wear and tear can be appropriately distributed to avoid prematurely depleting one of the storage devices from other related storage devices in the group. Of course, the current technology can be applied not only to different storage devices, but also to a part of it, and finally the life of any memory component can be managed in this way.

In any case, controller 511 can be configured to reduce and/or distribute writes. With this function, the life of the suitable storage device 530, 540 can be extended. An exemplary method of performing this technique will be presented in the description of FIG.

In accordance with another embodiment, FIG. 6 illustrates a method 600 for delaying memory life reduction operations when a desired lifetime duration exceeds an estimated lifetime duration. Another alternative embodiment is to perform the method 600 using the system 500 of FIG. 5 and/or further selectively incorporating any of the techniques of FIGS. 1-4. However, of course, method 600 can be used in any desired manner. Of course, the foregoing definitions may apply to the description herein.

Once operation 601 is initiated, method 600 continues to wait for a command issued by a computer (eg, computer 501, etc.) to at least one storage device (eg, storage device 530, 540, etc.) by a controller (eg, controller 511 of FIG. 5, etc.). 602. Once the controller receives the instruction, the controller determines if the instruction received in operation 602 is a life reduction instruction (eg, erase operation, write When the operation is entered, etc., the method proceeds to decision 603. If it is determined in decision 603 that the currently received instruction is not a life reduction instruction, then the instruction may be processed in operation 607.

On the other hand, if it is determined in decision 603 that the currently received command is indeed a life reduction command, then the life predictor module (eg, life predictor module 514, etc.) is based on operation 602. The estimated life is calculated by the received command, the previous life, and the current time (eg, the time module 517, etc.), see operation 604. In one embodiment, the previous lifetime may represent the previous state of the life predictor module. In another embodiment, the previous lifetime can be achieved by measuring one or more attributes of the at least one storage device.

In any event, the life expectancy estimated by such a life predictor module is provided to an adjustment module (eg, adjustment module 516, etc.). In decision 605, if the life expectancy receiver receives an estimated life that is shorter than the required life of the adjustment module, the adjustment module determines if adjustment is needed. If adjustment is needed, method 600 proceeds to operation 606 by delaying (eg, adjusting) the life reduction instruction. However, if the estimated life is not shorter than the required life, method 600 will process at operation 607, as described above.

Specifically, in operation 606, the adjustment module can adjust the execution of the life reduction command using the controller. In a specific embodiment, such adjustments can be implemented by using a controller to delay the execution of the life reduction command until the lifetime estimated by the life predictor is longer than or equal to the required life.

In another embodiment, the adjustment may be determined for a predetermined period of time and applied to instructions within a subsequent predetermined period. In this specific embodiment In the predetermined time interval, it is possible to limit how much life must be shortened during the predetermined period. In another embodiment, the limit of how much life must be shortened during a predetermined period of time over a predetermined period of time may be determined in one or more previous time intervals. In another embodiment, the determination of whether or not adjustments are needed may be based on an analysis of a number of undetermined operations, such that the non-life reduction operation can be performed prior to the life reduction operation or prior to the operation of such a life reduction operation.

With this design, the data storage system is provided to control the life reduction operation to ensure the minimum life required. It is therefore possible to estimate the effect of the life reduction operation on this minimum required life and to adjustably limit the frequency of the life reduction operation.

Figure 7 illustrates a graphical user interface 700 for metering memory life in accordance with another embodiment. As an option, the graphical user interface 700 can be implemented under the functional and architectural conditions of Figures 1 through 6. However, of course, the graphical user interface 700 can be used in any desired environment. It should also be noted that the foregoing definitions may apply to this description.

As shown, various different indications are displayed to reflect at least one level associated with the life of the memory. In a specific embodiment, the level can be identified in operation 102 of FIG. However, of course, this life-related level may include any desired level that is at least partially related to the life of the memory. For example, in the condition of system 500 of FIG. 5, the controller 511 can reply to the layer from any display processed and/or transmitted to the computer 501, under the control of a software application (eg, a plug-in). The order shows the relevant indications.

For example, in one embodiment, the aforementioned indicia can include a meter 702 that indicates the remaining life of one or more memories. In this particular embodiment, meter 702 can indicate the remaining amount of memory total life as a function of the number of performing life reduction operations over time. In another embodiment, the aforementioned indicia may include an estimate 705 indicative of a lifetime based on a prior usage inference and a hypothetical pause adjustment operation.

In another embodiment, the aforementioned indicia can include a warning 704 for indicating the minimum remaining life of one or more memories. This lifetime can be estimated, for example, based on past usage data of the memory. With this design, the user can be warned to replace the memory within a predetermined amount of time. Of course, other specific embodiments of any desired labeling may be considered to report various different information related to memory life.

FIG. 8 illustrates a method 800 of utilizing different information to reduce write operations in a memory, in accordance with another embodiment. As an option, the method 800 can be selected to perform in conjunction with the functions and architecture of FIGS. 1-7. However, of course, method 800 can be performed in any desired environment. It should also be noted that the foregoing definitions may apply to this description.

As shown in the figure, it can recognize the execution of the data write operation in the memory, please refer to operation 802. In the present description, the write operation may include any operation that causes the stored data in the memory to be modified. Moreover, the write operation can be identified in any desired manner by intercepting the write command associated with the operation, or the write operation itself.

As shown in operation 804, the difference between the write operation result and the memory storage data can be determined. In the context of this note, the aforementioned differences can be reflected to The first state in which a portion of the data is stored in the memory causes a difference between the second state and the aforementioned write operation.

In another embodiment, the difference between any of the data stored in the memory can be determined. For example, a new modified version of the file can be generated and written to a new location in the memory so that the difference in data at different locations in the memory can be determined. As an option, the location of the data can be identified based on hashes, multi-dimensional search filters, and the like. To this end, in an exemplary embodiment, different entities of the same material may be written to different locations in the memory, and the difference in the judgment may include the location of the data, not necessarily the material itself.

In a specific embodiment, the difference-related difference information may be stored in the memory (eg, the stored data is in the same memory). In another embodiment, the difference information may also be stored in an individual buffer in a manner that is later described in the different embodiments. It should be noted that the difference information may include at least a portion of any information that is determined by the difference in the description of operation 804. As will become apparent from the discussion of the specific embodiments described later, the difference information may be stored in a set of instructions using a set of instructions. As described below, such a set of instructions can be adaptively changed and/or dynamically expanded in different embodiments.

To achieve this, you can use the difference information to reduce the write operation. Please refer to operation 806. With this design, the write operation reduces the memory life by selectively extending.

More information about the various architectures and functions will now be presented, and each user can implement or not implement the aforementioned architecture as needed. For example, an exemplary system would be proposed to implement a method of reducing write operations based on differential information. It is important to note that the following information is presented for illustrative purposes and should not be construed as limiting in any way. Any of the following features can be selected to exclude the use of other features described above.

Figure 9 illustrates a system 900 for reducing write operations in memory in accordance with another embodiment. As an option, system 900 can combine any of the methods or techniques of FIGS. 1-7 with method 800 of FIG. 8 and/or further. However, of course, system 900 can be used in any desired environment. However, as such, the foregoing definitions may apply to this description.

As shown, system 900 includes an input/output (I/O) bus 902 that connects computer 901 to storage device 930 in a manner to be described later. The I/O bus 902 includes a read path 903 and a write path 904. The storage device 930 includes a plurality of storage blocks 931, 932, 933. The storage blocks 931, 932, and 933 are written and read by the computer 901.

The reason for this will be quickly understood. A predetermined portion 934 of each of the storage blocks 931, 932, 933 can be allocated for storing different information to reflect the corresponding storage blocks 931, 932 by the computer 901. Any changes to the information stored in the remaining 933 of 933. In various embodiments, the size of the predetermined portion 934 can be set by the user. In addition, the difference information stored therein may take any form.

Table 1 shows a possible format for representing an instance of difference information (a plurality of which may be stored in each predetermined portion 934 of the storage blocks 931, 932, 933) in).

In the above-described embodiments, the operational code may represent operations performed on data stored in the remaining portions 935 of the corresponding storage blocks 931, 932, 933. Examples of such operations may include, but are not limited to, end, replace, move up, move down, delete, insert, and/or any other operation. As an option, each of these operations can be accurately represented by its associated code (e.g., substitution = '001', upshift = '010', etc.).

In addition, the source start address and size may indicate and represent the size (individual) size of the remaining portion 935 of the corresponding storage block 931, 932, 933 that is subject to operation. The data itself can be stored as an element of the difference information even when the operation requires replacement/modification of the data. Another option is to apply a compression algorithm to the difference information for more efficient storage. Another option is to specify when the operation requires moving data. The location of the data source, not necessarily the data itself, as such information is included in the original storage block.

In another embodiment, a new operation is adjustably established. For example, the repeating order of the first operation can be replaced by a new second operation. This new second operation selectively illustrates the first sequence of operations. In this way, new operations can be tunably established, allowing system 900 to optimize self-adjustment to new applications.

Of course, the data structure of Table 1 is presented for illustrative purposes only and should not be construed as limiting in any way. For example, an instance of the difference information may only include information that will be replaced (without any complicated instructions, etc.).

There is also provided an apparatus 910 for reducing write operations in memory. The device 910 includes a bond memory 920 that includes a plurality of bond buffers 921, 922, 923. In one embodiment, each of the bond buffers 921, 922, 923 may be of a predetermined size (eg, 4Kb, etc.) and may be the smallest of each of the storage blocks 931, 932, 933 to be written in a single operation. Partially related. Moreover, in various embodiments, the bond buffer 921 can include storage devices on the wafer, external memory, DRAM, SRAM, and the like.

It will be readily apparent that each of the bonded memory buffers 921, 922, and 923 can store a difference information instance for the corresponding storage blocks 931, 932, and 933 (for example, refer to Table 1). ). In other words, the first bonded memory buffer 921 stores an instance of difference information for the first storage block 931, and the second bonded memory buffer 922 stores an instance of the difference information for the second storage block 932. And the third joint The memory buffer 923 is an example of storing the difference information for the third storage block 933, and so on.

The device 910 further includes an update module 912 connected to the interface memory 920 through the bus bar 914 for writing the difference information stored in the interface memory buffers 921, 922, and 923 to the corresponding storage block 931. 932, and 933. In one embodiment, the writing can be initiated in any of the bonded memory buffers 921, 922, 923 filled with at least one difference information instance (and thus for the appropriate storage blocks 931, 932, and 933) A minimum write size). To complete the writing, the update module 912 is connected to the storage device 930 via the bus 915. As shown further, the output of the update module 912 is coupled to the I/O bus 902 via the read path 903.

In addition, the difference calculation module 911 can be connected to the update module 912 through the read path bus 903, connected to the I/O bus 902 via the write path bus 904, and further coupled to the memory 920 through the bus 913. connection. In use, the difference computing module 911 can read data from the storage device 930 and further reconstruct the difference information from the associated storage blocks 931, 932, and 933, and/or the associated memory buffers 921, 922, 923. The status of the information.

The difference operation module 911 can still use the status of the data first (similar to the above read operation), identify the status and write operation (by the computer 901), and then use the difference between the states, when appropriate. One or more pieces of difference information for updating the associated storage blocks 931, 932, and 933 are filled in the bonded memory buffers 921, 922, 923 so that the data can be written to the storage device 930. More information on such read and write operations will be presented when describing Figures 10 and 11.

In various embodiments, the difference computing module 911 can employ any desired technique to identify the aforementioned differences. For example, various different string matching algorithms, data dynamic estimation techniques, and the like can be applied. In another embodiment, the difference can be determined on a byte by bit basis.

In addition, the difference operation may involve any one or more of the following factors: finding those byte strings inserted, finding those byte strings, deleting those byte strings, finding those byte strings, and judging Whether the byte string is updated by adding a value, discovering a copy of the storage block and establishing a reference to them, discovering a block partition, discovering a block merge, and the like.

10 illustrates a method 1000 of reading memory using different information, in accordance with another embodiment. As an option, method 1000 can be performed using system 900 of FIG. 9 and/or further selectively incorporating any of the techniques of FIGS. 1-8 as needed. However, of course, the method 1000 can be used in any desired environment. Of course, the foregoing definitions may apply to this description.

As shown, when a computer (eg, computer 901, etc.) makes a request, the block can be read by a storage device (eg, storage device 930, etc.) (eg, blocks 931, 932, 933, etc. of FIG. 9) The method 1000 begins in operation 1001. The read storage block data is sent to the update module (for example, update module 912, etc.). Next, in response to the read operation, the difference information is read from the bond buffer (e.g., the bond buffer 921, 922, 923, etc.) corresponding to the storage block (related to the computer request), and/or from the storage block itself. Please refer to operation 1002. The appropriate source of the difference information can be requested when reading the request. Whether the message has been written from the bond buffer to the corresponding memory block. As an option, the difference information can be interspersed between the flash memory data. In addition, differences associated with a particular profile can be organized into one or more groups.

Next, in operation 1003, the update module will apply the difference of the difference information reflected by the operation 1002 when the corresponding block is read in operation 1001. To achieve this, the data reconstructed in operation 1003 is sent to the computer via a read path (eg, read path 903, etc.), as described in operation 1004.

In various embodiments, the aforementioned data reading operations may involve mapping from a logical storage block number to a physical storage block number. In addition, method 1000 can be combined with reading to provide error detection and error correction. The error detection and correction of the read data may further include a re-read operation of attempting to restore the data, and resetting the restored data to another storage location. For example, resetting the restored data may involve translation of the logical storage block and/or based on error rate information of the candidate storage block.

FIG. 11 illustrates a method 1100 of writing memory using different information, in accordance with another embodiment. As an option, method 1100 can be implemented using the system 900 of FIG. 9 and/or further, if desired, selectively incorporating the techniques of FIGS. 1-8, 10. However, of course, the method 1100 can be used in any desired environment. Of course, the foregoing definitions may apply to this description.

Similar to the reading method 1000 of FIG. 10, the method 1100 can begin by reading a block from a storage device (eg, storage device 930, etc.) in operation 1101 (such as 931, 932, 933, etc. of FIG. 9). According to the write request of the computer (such as computer 901, etc.), then the storage block data will be sent. Up to an update module (for example, update module 912, etc.). Next, in operation 1102, the difference information is read from the bonding buffer (eg, the bonding buffers 921, 922, 923, etc.) corresponding to the storage block (related to the computer request), and/or the difference information is read from the storage block itself. . Next, in operation 1103, the update module applies the difference from the difference information reflected by operation 1002 when the corresponding block is read in operation 1001 to reconstruct the read or written data.

To this end, the data reconstructed in operation 1103 is sent to a difference computing module (e.g., difference computing module 911, etc.) and compared to the state of the data obtained by performing a write operation requested by the computer. See operation 1104. To this end, the difference between the reconstructed data and the state of the data obtained after the write operation is identified. In one embodiment, the difference is caused by an application that updates the data (executed on a computer). The update may include, but is not limited to, replacing a byte string, inserting a byte string, deleting a byte string, copying a byte string, and the like.

In operation 1105, the difference-related difference information is computed in operation 1104 and may be appended to the appropriate splicing buffer corresponding to the block so that at least one difference must be computed in operation 1104. This addition can be accomplished by writing to the end of the bond buffer of the bond memory. In a specific embodiment, such an addition may include decompressing the bond buffer, attaching the material, and then recompressing the appropriate bond buffer. As an option, the bond buffer memory can be reset to the bond buffer as required.

In an alternative embodiment, the difference information may be stored when performing descriptive functional operations (e.g., writing, etc.) on the material. For example, the difference information reflects the changes made to perform operations within B-Trees, and therefore explains The difference in this operation. Such B-Trees can be used by databases, mail servers, file systems, and the like.

Next in decision 1106, the bond buffer is tested to determine if it is full. If no splicing buffer is filled, method 1100 proceeds to operation 1110. On the other hand, if at least one of the splicing buffers is full, then method 1100 proceeds to operation 1107. In operation 1107, any filled splicing buffers are appended to the difference information. Additionally, as shown in operation 1112, the filled bond buffer will be emptied (for reuse, etc.).

It will further determine if the difference information has been filled (operation 1114). If it is determined that the difference information has not been filled, method 1100 proceeds to operation 1110. However, in response to the judgement that the difference information has been filled, the changes from the difference information will be applied to the data, please note operation 1116. In addition, as shown in operation 1118, the data block with the applied change is written and the old data is discarded. Additionally, as shown in operation 1120, the difference information will be cleared. To this end, a data storage system can be provided in which the difference between the written and existing data can be used to reduce the writing and interspersed between the memory blocks to improve the reliability of the block storage device. Sex.

In various embodiments, the memory referred to in the foregoing embodiments may include a mechanical storage device (eg, a disk, including a SATA disk, a SAS disk, a Fibre Channel disk, an IDE disk, an ATA). A disk, a CE disk, a USB disk, a smart card disk, an MMC disk, etc., and/or a non-mechanical storage device (for example, based on a semiconductor). For example, such non-mechanical memory can include volatile or non-volatile memory. In various embodiments, the non-volatile memory device can include flash memory (eg, For example, each unit of unit NOR flash memory, multi-bit NOR flash memory per unit, NAND flash memory per unit unit, multi-bit NAND flash memory per unit, multi-level multi-level per unit Meta NAND flash memory, large block flash memory, etc.). Although various different memory examples are presented herein, it should be noted that while any type of memory can be applied to a variety of different principles, its lifetime may be reduced by performing various different operations.

FIG. 12 illustrates an exemplary system 1200 in which various architectures and/or functions of various prior embodiments may be implemented. For example, the exemplary system 1200 can be a computer as set forth in some of the previous specific embodiments. Additionally, the various devices described above may even be an element of system 1200.

As shown, system 1200 includes at least one host processor 1201 that is coupled to communication bus 1202. System 1200 also includes a main memory 1204. Control logic (software) and data are stored in main memory 1204, which is in the form of random access memory (RAM).

System 1200 also includes a graphics processor 1206 and a display 1208, a computer screen. System 1200 can also include a second storage device 1210. The second storage device 1210, for example, may include a hard disk drive and/or a removable storage disk, that is, a floppy disk drive, a tape drive, an optical disk drive, and the like. The removable disk can be read and/or written from the removable storage module in a conventional manner.

The computer program, or computer control logic algorithm, can be stored in the main memory 1204 and/or the second storage device 1210. When the computer program is executed, the system 1200 can perform various functions. Memory 1204, storage The 1210 and/or other storage devices can be used as examples of computer readable media.

In a specific embodiment, the architecture and/or functions of the various previous figures may be implemented in the host processor 1201, the graphics processor 1206, the second storage device 1210, and the host processor 1201 and the graphics processor 1206. At least some of the functional integrated circuits (not shown), a chipset (ie, a modular circuit that is designed to operate and sell in a modular manner to perform related functions, etc.), and/or any other integrated circuit Environment.

In addition, the architecture and/or functions of the various previous diagrams may be implemented in general computer systems, circuit board systems, game console systems for entertainment purposes, application specific application systems, and/or any other desired system environment. in. For example, system 1200 can take the form of a desktop computer, a laptop, and/or other types of logic. Additionally, system 1200 can take the form of a variety of other devices including, but not limited to, personal digital assistant (PDA) devices, mobile telephone devices, televisions, and the like.

Additionally, although not shown, system 1200 can also be networked (eg, telecommunications networks, regional networks (LANs), wireless networks, wide area networks (WANs), such as the Internet, peer-to-peer networks, and cable networks. Etc.] to connect for communication purposes.

While the specific embodiments have been described above, it is to be understood that Therefore, the breadth and scope of the preferred embodiments should not be limited by any of the above-described exemplary embodiments, and should be defined only in the scope of the following claims.

100‧‧‧How to delay memory life reduction operations

102‧‧‧ Operation - Identify a level related to the life of the memory

104‧‧‧ Operation - At least one delay memory life reduction operation is proposed based on this level of delay

200‧‧‧Delayed memory life reduction operation technology

202‧‧‧ Total operations

204‧‧‧Minimum life expectancy

206‧‧‧Maximum average operating rate

300‧‧‧Time-based technology

302‧‧‧ Total operations

304‧‧‧Minimum life expectancy

306‧‧‧Maximum average operating rate

400‧‧‧Integrated technology

402‧‧‧ Total operations

404‧‧‧Minimum life expectancy

406‧‧‧Maximum average operating rate

408‧‧‧The number of operations exceeds the maximum average operating rate

500‧‧‧ system

501‧‧‧ computer

502‧‧‧Storage busbar

503‧‧‧Storage system

510‧‧‧ device

511‧‧‧ Controller

512‧‧‧ busbar

513‧‧ ‧ busbar

514‧‧‧Life Estimator Module

515‧‧ ‧ busbar

516‧‧‧Adjustment module

517‧‧‧Time module

518‧‧ ‧ busbar

519‧‧‧ busbar

520‧‧‧Required life module

521‧‧ ‧ busbar

522‧‧ ‧ busbar

530‧‧‧Storage device

531‧‧‧Modules or blocks

532‧‧‧Modules or blocks

533‧‧‧Modules or blocks

540‧‧‧Storage device

541‧‧‧Modules or blocks

542‧‧‧Modules or blocks

543‧‧‧Modules or blocks

600‧‧‧Memory life reduction operation method

601‧‧‧Starting operation

602‧‧‧Instructions, Operations-Waiting Instructions

603‧‧‧ decided

604‧‧‧Operation - Life expectancy

605‧‧‧ decided

606‧‧‧Operation-Adjust Life Reduction Instructions

607‧‧‧Operation-Processing Instructions

700‧‧‧ graphical user interface

702‧‧‧meter

704‧‧‧ Warning

705‧‧‧ Estimated value

800‧‧‧How to reduce memory write operations

802‧‧‧ Operation - Identify the write operation of the data stored in the execution memory

804‧‧‧ Operation - Determine the difference between the write operation result and the memory storage data

806‧‧‧ Operation - Use difference information to reduce write operations

900‧‧‧System for reducing write operations in memory

901‧‧‧ computer

902‧‧‧Input/Output (I/O) Busbars

903‧‧‧Read path, read path bus

904‧‧‧Write path, busbar

910‧‧‧Device for reducing write operations in memory

911‧‧‧Differential Computing Module

912‧‧‧Update Module

913‧‧ ‧ busbar

914‧‧ ‧ busbar

915‧‧ ‧ busbar

920‧‧‧Connected memory

921‧‧‧ Bonding buffer, bonding memory buffer

922‧‧‧ Bonding buffer, bonding memory buffer

923‧‧‧ Bonding buffer, bonding memory buffer

930‧‧‧Storage device

931‧‧‧ Storage Blocks

932‧‧‧ storage block

933‧‧‧ storage block

934‧‧‧Predetermined part

935‧‧‧The rest of the storage blocks 931, 932, 933

1000‧‧‧How to read memory using different information

1001‧‧‧Operation - Reading blocks from the storage device

1002‧‧‧Operation-Reading Difference Information

1003‧‧‧ Operation - Differences apply to information

1004‧‧‧Operation-reconstruction data was sent back

1100‧‧‧ A method of writing data using different information

1101‧‧‧Operation - reading blocks from storage devices

1102‧‧‧Operation - Reading Difference Information

1103‧‧‧ Operation - Differences apply to information

1104‧‧‧Operation - Calculate the difference between the write and the previous block

1105‧‧‧Operation-difference information attached to the joint buffer

1106‧‧‧Decision

1107‧‧‧Operation-bonding buffer is attached to the difference information

1110‧‧‧ operation

1112‧‧‧Operation - Empty the junction buffer

1114‧‧‧Operation - judge whether the difference information has been filled

1116‧‧‧Operation-Changes in the difference information applied to the data

1118‧‧‧Operation - The changed data block will be written and the old data will be discarded

1120‧‧‧Operation - Clearing Difference Information

1200‧‧‧ Systems that implement various architectures and/or functions of various previous embodiments

1202‧‧‧Communication bus

1201‧‧‧Host processor

1204‧‧‧ main memory

1206‧‧‧Drawing processor

1208‧‧‧ display

1210‧‧‧Second storage device

1 shows a method for delaying a memory life reduction operation, in accordance with an embodiment.

2 illustrates a technique for delaying memory life reduction operations in accordance with another embodiment.

3 illustrates a time interval technique for delaying memory life reduction operations, in accordance with another embodiment.

Figure 4 illustrates an integrated operational technique that delays memory life reduction in accordance with yet another embodiment.

Figure 5 illustrates a system for memory life reduction operation if the lifetime of the life expectancy exceeds the estimated life duration, in accordance with another embodiment.

Figure 6 illustrates a method for delaying memory life reduction operations if the lifetime of the life expectancy exceeds the estimated life duration, in accordance with another embodiment.

Figure 7 illustrates a graphical user interface for accurately metering the life of a memory, in accordance with another embodiment.

Figure 8 illustrates a method of utilizing different information to reduce memory write operations, in accordance with another embodiment.

Figure 9 illustrates a system for reducing memory write operations in accordance with another embodiment.

Figure 10 illustrates a method for reading memory using different information, in accordance with another embodiment.

Figure 11 illustrates a method for writing to a memory using different information, in accordance with another embodiment.

Figure 12 illustrates a specific embodiment using a processor based system.

100‧‧‧How to delay memory life reduction operations

102‧‧‧ Operation - Identify a level related to the life of the memory

104‧‧‧ Operation - At least one operation for delaying memory life reduction is proposed based on this level

Claims (20)

A method of delaying the life of a storage device, comprising: receiving an instruction from a host processor to initiate operation to be applied to one of a plurality of storage devices; determining whether the operation is related to a lifetime of one of the storage devices a life reduction operation; determining an overall rate of life reduction operations associated with the storage devices; determining a maximum average operation rate of one of the life reduction operations based on an expected life of the storage devices; and operating according to a life reduction operation The integral function of the overall rate conditionally delays at least a portion of the operation, wherein the overall rate of the life reduction operation is selectively allowed to dynamically exceed the maximum average operating rate of the life reduction operation. The method of claim 1, wherein the life span comprises at least one life expectancy, one actual life, and an estimated life. The method of claim 1, wherein conditionally delaying at least a portion of the operation comprises conditionally delaying the initiating the operation. The method of claim 1, wherein the delay is based on an application that initiates the operation. The method of claim 1, wherein the delay is independent of an application that initiates the operation. The method of claim 1, wherein the operation comprises an erase operation. The method of claim 1, wherein the operation comprises a program operation. The method of claim 1, further comprising conditionally delaying at least a portion of the operation based on past usage records of the storage devices. The method of claim 1, further comprising conditionally delaying at least a portion of the operation based on an expected usage record of the storage devices. The method of claim 1, further comprising conditionally delaying at least a portion of the operation in accordance with a time interval at which the operation is initiated. The method of claim 1, wherein only the portion of the operation is delayed. The method of claim 1, wherein the storage devices comprise a mechanical storage device. The method of claim 1, wherein the storage device comprises a non-volatile memory device. The method of claim 13, wherein the non-volatile memory device comprises NOR flash memory per unit unit, NOR flash memory per unit multi-bit, NAND flash memory per unit unit, At least one of a multi-level multi-bit multi-bit NAND type flash memory per unit and a large block flash memory. A storage system that delays the life of a storage device, including: Means for receiving an instruction from a host processor, wherein the instruction is to initiate an operation to be applied to one of the plurality of storage devices; and determining whether the operation is related to a lifetime of one of the storage devices Means for operating; means for determining an overall rate of life reduction operations associated with the storage devices; means for determining a maximum average operating rate of one of the life reduction operations based on an expected life of the storage devices; Means for conditionally delaying at least a portion of the operation in accordance with an integral function including the overall rate of the life reduction operation, wherein the overall rate of the life reduction operation is selectively allowed to dynamically exceed the life reduction operation The maximum average operating rate. The storage system of claim 15, wherein conditionally delaying at least a portion of the operation comprises conditionally delaying the initiating the operation. The storage system of claim 15 wherein the operation comprises an erasing operation. The storage system of claim 15 wherein the operation comprises a program operation. The storage system of claim 15 wherein the storage device comprises a non-volatile memory device. The storage system of claim 19, wherein the non-volatile memory device comprises NOR flash memory per unit unit, NOR flash memory per unit multi-bit, NAND flash memory per unit unit cell , multi-bit NAND flash memory per unit At least one of a multi-level multi-bit NAND flash memory per unit and a large block flash memory.